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lvzhengyang
riscv-gcc-1
Commits
3edf8a98
Commit
3edf8a98
authored
Oct 12, 2017
by
Jan Hubicka
Committed by
Jan Hubicka
Oct 12, 2017
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* x86-tune-sched.c (ix86_adjust_cost): Fix Zen support.
From-SVN: r253684
parent
7159f19c
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33 additions
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1 deletions
+33
-1
gcc/ChangeLog
+4
-0
gcc/config/i386/x86-tune-sched.c
+29
-1
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gcc/ChangeLog
View file @
3edf8a98
2017
-
10
-
12
Jan
Hubicka
<
hubicka
@
ucw
.
cz
>
*
x86
-
tune
-
sched
.
c
(
ix86_adjust_cost
):
Fix
Zen
support
.
2017
-
10
-
12
Uros
Bizjak
<
ubizjak
@
gmail
.
com
>
*
config
/
alpha
/
alpha
.
c
(
alpha_split_conditional_move
):
gcc/config/i386/x86-tune-sched.c
View file @
3edf8a98
...
...
@@ -352,7 +352,6 @@ ix86_adjust_cost (rtx_insn *insn, int dep_type, rtx_insn *dep_insn, int cost,
case
PROCESSOR_BDVER2
:
case
PROCESSOR_BDVER3
:
case
PROCESSOR_BDVER4
:
case
PROCESSOR_ZNVER1
:
case
PROCESSOR_BTVER1
:
case
PROCESSOR_BTVER2
:
case
PROCESSOR_GENERIC
:
...
...
@@ -392,6 +391,35 @@ ix86_adjust_cost (rtx_insn *insn, int dep_type, rtx_insn *dep_insn, int cost,
}
break
;
case
PROCESSOR_ZNVER1
:
/* Stack engine allows to execute push&pop instructions in parall. */
if
((
insn_type
==
TYPE_PUSH
||
insn_type
==
TYPE_POP
)
&&
(
dep_insn_type
==
TYPE_PUSH
||
dep_insn_type
==
TYPE_POP
))
return
0
;
memory
=
get_attr_memory
(
insn
);
/* Show ability of reorder buffer to hide latency of load by executing
in parallel with previous instruction in case
previous instruction is not needed to compute the address. */
if
((
memory
==
MEMORY_LOAD
||
memory
==
MEMORY_BOTH
)
&&
!
ix86_agi_dependent
(
dep_insn
,
insn
))
{
enum
attr_unit
unit
=
get_attr_unit
(
insn
);
int
loadcost
;
if
(
unit
==
UNIT_INTEGER
||
unit
==
UNIT_UNKNOWN
)
loadcost
=
4
;
else
loadcost
=
7
;
if
(
cost
>=
loadcost
)
cost
-=
loadcost
;
else
cost
=
0
;
}
break
;
case
PROCESSOR_CORE2
:
case
PROCESSOR_NEHALEM
:
case
PROCESSOR_SANDYBRIDGE
:
...
...
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