predicates.md (rl78_cmp_operator_signed): New.

* config/rl78/predicates.md (rl78_cmp_operator_signed): New.
(rl78_stack_based_mem): New.
* config/rl78/constraints.md (Iv08): New.
(Iv16): New.
(Iv24): New.
(Is09): New.
(Is17): New.
(Is25): New.
(ISsi): New.
(IShi): New.
(ISqi): New.
* config/rl78/rl78-expand.md (movqi): Reject more SUBREG operands.
(movhi): Likewise.
(movsi): Change from expand to insn-and-split.
(ashrsi3): Clobber AX.
(lshrsi3): New.
(ashlsi3): New.
(cbranchsi4): New.
* config/rl78/rl78.md (CC_REG): Fix.
(addsi3): Allow memory and immediate operands.
(addsi3_internal): Split into...
(addsi3_internal_virt): ...new, and ...
(addsi3_internal_real): ...new.
(subsi): New.
(subsi3_internal_virt): New.
(subsi3_internal_real): New.
(mulsi3): Add memory operand.
(mulsi3_rl78): Likewise.
(mulsi3_g13): Likewise.
* config/rl78/rl78-real.md (cbranchqi4_real_signed): New.
(cbranchqi4_real): Add more constraint options.
(cbranchhi4_real): Expand pattern.
(cbranchhi4_real_signed): New.
(cbranchhi4_real_inverted): New.
(cbranchsi4_real_lt): New.
(cbranchsi4_real_ge): New.
(cbranchsi4_real_signed): New.
(cbranchsi4_real): New.
(peephole2): New.
* config/rl78/rl78-virt.md (ashrsi3_virt): Add custom cases for constant shifts.
(lshrsi3_virt): Likewise.
(ashlsi3_virt): Likewise.
(cbranchqi4_virt_signed): New.
(cbranchhi4_virt_signed): New.
(cbranchsi4_virt): New.
* config/rl78/rl78.c: Whitespace fixes throughout.
(move_elim_pass): New.
(pass_data_rl78_move_elim): New.
(pass_rl78_move_elim): New.
(make_pass_rl78_move_elim): New.
(rl78_devirt_info): Run devirt earlier.
(rl78_move_elim_info): New.
(rl78_asm_file_start): Register it.
(rl78_split_movsi): New.
(rl78_as_legitimate_address): Allow virtual base registers when
appropriate.
(rl78_addr_space_convert): Remove spurious debug stuff.
(rl78_print_operand_1): Add z,s,S,r,E modifiers.
(rl78_print_operand): More cases for not printing '#'.
(rl78_expand_compare): Remove most of the logic.
(content_memory): New.
(clear_content_memory): New.
(get_content_index): New.
(get_content_name): New.
(display_content_memory): New.
(update_content): New.
(record_content): New.
(already_contains): New.
(insn_ok_now): Re-recog insns with virtual registers.
(add_postponed_content_update): New.
(process_postponed_content_update): New.
(gen_and_emit_move): New.
(transcode_memory_rtx): Record new location content.  Use
gen_and_emit_move.
(force_into_acc): New.
(move_to_acc): Use gen_and_emit_move.
(move_from_acc): Likewise.
(move_acc_to_reg): Likewise.
(move_to_x): Likewise.
(move_to_hl): Likewise.
(move_to_de): Likewise.
(rl78_alloc_physical_registers_op1): Record location content.
(has_constraint): New.
(rl78_alloc_physical_registers_op2): Record location content.
Optimize use of HL.
(rl78_alloc_physical_registers_ro1): Likewise.
(rl78_alloc_physical_registers_cmp): Likewise.
(rl78_alloc_physical_registers_umul): Likewise.
(rl78_alloc_address_registers_macax): New.
(rl78_alloc_physical_registers): Initialize and set location
content memory as needed.
(rl78_reorg): Make sure split2 is called.
(rl78_rtx_costs): New.

Co-Authored-By: Nick Clifton <nickc@redhat.com>

From-SVN: r202511

gcc/ChangeLog

+2013-09-11  DJ Delorie  <dj@redhat.com>
+	    Nick Clifton  <nickc@redhat.com>
+
+	* config/rl78/predicates.md (rl78_cmp_operator_signed): New.
+	(rl78_stack_based_mem): New.
+	* config/rl78/constraints.md (Iv08): New.
+	(Iv16): New.
+	(Iv24): New.
+	(Is09): New.
+	(Is17): New.
+	(Is25): New.
+	(ISsi): New.
+	(IShi): New.
+	(ISqi): New.
+	* config/rl78/rl78-expand.md (movqi): Reject more SUBREG operands.
+	(movhi): Likewise.
+	(movsi): Change from expand to insn-and-split.
+	(ashrsi3): Clobber AX.
+	(lshrsi3): New.
+	(ashlsi3): New.
+	(cbranchsi4): New.
+	* config/rl78/rl78.md (CC_REG): Fix.
+	(addsi3): Allow memory and immediate operands.
+	(addsi3_internal): Split into...
+	(addsi3_internal_virt): ...new, and ...
+	(addsi3_internal_real): ...new.
+	(subsi): New.
+	(subsi3_internal_virt): New.
+	(subsi3_internal_real): New.
+	(mulsi3): Add memory operand.
+	(mulsi3_rl78): Likewise.
+	(mulsi3_g13): Likewise.
+	* config/rl78/rl78-real.md (cbranchqi4_real_signed): New.
+	(cbranchqi4_real): Add more constraint options.
+	(cbranchhi4_real): Expand pattern.
+	(cbranchhi4_real_signed): New.
+	(cbranchhi4_real_inverted): New.
+	(cbranchsi4_real_lt): New.
+	(cbranchsi4_real_ge): New.
+	(cbranchsi4_real_signed): New.
+	(cbranchsi4_real): New.
+	(peephole2): New.
+	* config/rl78/rl78-virt.md (ashrsi3_virt): Add custom cases for constant shifts.
+	(lshrsi3_virt): Likewise.
+	(ashlsi3_virt): Likewise.
+	(cbranchqi4_virt_signed): New.
+	(cbranchhi4_virt_signed): New.
+	(cbranchsi4_virt): New.
+	* config/rl78/rl78.c: Whitespace fixes throughout.
+	(move_elim_pass): New.
+	(pass_data_rl78_move_elim): New.
+	(pass_rl78_move_elim): New.
+	(make_pass_rl78_move_elim): New.
+	(rl78_devirt_info): Run devirt earlier.
+	(rl78_move_elim_info): New.
+	(rl78_asm_file_start): Register it.
+	(rl78_split_movsi): New.
+	(rl78_as_legitimate_address): Allow virtual base registers when
+	appropriate.
+	(rl78_addr_space_convert): Remove spurious debug stuff.
+	(rl78_print_operand_1): Add z,s,S,r,E modifiers.
+	(rl78_print_operand): More cases for not printing '#'.
+	(rl78_expand_compare): Remove most of the logic.
+	(content_memory): New.
+	(clear_content_memory): New.
+	(get_content_index): New.
+	(get_content_name): New.
+	(display_content_memory): New.
+	(update_content): New.
+	(record_content): New.
+	(already_contains): New.
+	(insn_ok_now): Re-recog insns with virtual registers.
+	(add_postponed_content_update): New.
+	(process_postponed_content_update): New.
+	(gen_and_emit_move): New.
+	(transcode_memory_rtx): Record new location content.  Use
+	gen_and_emit_move.
+	(force_into_acc): New.
+	(move_to_acc): Use gen_and_emit_move.
+	(move_from_acc): Likewise.
+	(move_acc_to_reg): Likewise.
+	(move_to_x): Likewise.
+	(move_to_hl): Likewise.
+	(move_to_de): Likewise.
+	(rl78_alloc_physical_registers_op1): Record location content.
+	(has_constraint): New.
+	(rl78_alloc_physical_registers_op2): Record location content.
+	Optimize use of HL.
+	(rl78_alloc_physical_registers_ro1): Likewise.
+	(rl78_alloc_physical_registers_cmp): Likewise.
+	(rl78_alloc_physical_registers_umul): Likewise.
+	(rl78_alloc_address_registers_macax): New.
+	(rl78_alloc_physical_registers): Initialize and set location
+	content memory as needed.
+	(rl78_reorg): Make sure split2 is called.
+	(rl78_rtx_costs): New.
+
 2013-09-11  Richard Sandiford  <rdsandiford@googlemail.com>
 
 	* simplify-rtx.c (simplify_unary_operation_1): Use simplify_gen_binary

gcc/config/rl78/constraints.md

@@ -43,6 +43,7 @@
 ; Y - any valid memory
 ; Wxx - various memory addressing modes
 ; Qxx - conditionals
+; U = usual memory references mov-able to/from AX
 ; v = virtual registers
 ; Zxx = specific virtual registers
 
@@ -56,6 +57,56 @@
   (and (match_code "const_int")
        (match_test "IN_RANGE (ival, 1, 7)")))
 
+(define_constraint "Iv08"
+  "@internal
+   Integer constant equal to 8."
+  (and (match_code "const_int")
+       (match_test "IN_RANGE (ival, 8, 8)")))
+(define_constraint "Iv16"
+  "@internal
+   Integer constant equal to 16."
+  (and (match_code "const_int")
+       (match_test "IN_RANGE (ival, 16, 16)")))
+(define_constraint "Iv24"
+  "@internal
+   Integer constant equal to 24."
+  (and (match_code "const_int")
+       (match_test "IN_RANGE (ival, 24, 24)")))
+
+(define_constraint "Is09"
+  "@internal
+   Integer constant in the range 9 @dots{} 15 (for shifts)."
+  (and (match_code "const_int")
+       (match_test "IN_RANGE (ival, 9, 15)")))
+(define_constraint "Is17"
+  "@internal
+   Integer constant in the range 17 @dots{} 23 (for shifts)."
+  (and (match_code "const_int")
+       (match_test "IN_RANGE (ival, 17, 23)")))
+(define_constraint "Is25"
+  "@internal
+   Integer constant in the range 25 @dots{} 31 (for shifts)."
+  (and (match_code "const_int")
+       (match_test "IN_RANGE (ival, 25, 31)")))
+
+(define_constraint "ISsi"
+  "@internal
+   Integer constant with bit 31 set."
+  (and (match_code "const_int")
+       (match_test "(ival & 0x80000000) != 0")))
+
+(define_constraint "IShi"
+  "@internal
+   Integer constant with bit 15 set."
+  (and (match_code "const_int")
+       (match_test "(ival & 0x8000) != 0")))
+
+(define_constraint "ISqi"
+  "@internal
+   Integer constant with bit 7 set."
+  (and (match_code "const_int")
+       (match_test "(ival & 0x80) != 0")))
+
 (define_constraint "J"
   "Integer constant in the range -255 @dots{} 0"
   (and (match_code "const_int")

gcc/config/rl78/predicates.md

@@ -46,6 +46,8 @@
        (and (match_code "const_int")
 	    (match_test "IN_RANGE (INTVAL (op), 0, 65536)"))))
 
+(define_predicate "rl78_cmp_operator_signed"
+  (match_code "gt,ge,lt,le"))
 (define_predicate "rl78_cmp_operator_real"
   (match_code "eq,ne,gtu,ltu,geu,leu"))
 (define_predicate "rl78_cmp_operator"
@@ -58,3 +60,12 @@
 (define_predicate "rl78_addw_operand"
   (and (match_code "reg")
        (match_test "REGNO (op) == AX_REG || REGNO (op) == SP_REG || REGNO (op) >= FIRST_PSEUDO_REGISTER")))
+
+(define_predicate "rl78_stack_based_mem"
+  (and (match_code "mem")
+       (ior (and (match_code "reg" "0")
+		 (match_test "REGNO (XEXP (op, 0)) == SP_REG"))
+	    (and (match_code "plus" "0")
+		 (and (match_code "reg" "00")
+		      (match_test "REGNO (XEXP (XEXP (op, 0), 0)) == SP_REG")
+		      (match_code "const_int" "01"))))))

gcc/config/rl78/rl78-expand.md

@@ -35,9 +35,24 @@
     if (GET_CODE (operand1) == SUBREG
         && GET_CODE (XEXP (operand1, 0)) == SYMBOL_REF)
       FAIL;
+    /* Similarly for (SUBREG (CONST (PLUS (SYMBOL_REF)))).
+       cf. g++.dg/abi/packed.C.  */
+    if (GET_CODE (operand1) == SUBREG
+	&& GET_CODE (XEXP (operand1, 0)) == CONST
+        && GET_CODE (XEXP (XEXP (operand1, 0), 0)) == PLUS
+        && GET_CODE (XEXP (XEXP (XEXP (operand1, 0), 0), 0)) == SYMBOL_REF)
+      FAIL;
+
+    /* Similarly for (SUBREG (CONST (PLUS (SYMBOL_REF)))).
+       cf. g++.dg/abi/packed.C.  */
+    if (GET_CODE (operand1) == SUBREG
+	&& GET_CODE (XEXP (operand1, 0)) == CONST
+        && GET_CODE (XEXP (XEXP (operand1, 0), 0)) == PLUS
+        && GET_CODE (XEXP (XEXP (XEXP (operand1, 0), 0), 0)) == SYMBOL_REF)
+      FAIL;
 
     if (CONST_INT_P (operand1) && ! IN_RANGE (INTVAL (operand1), (-1 << 8) + 1, (1 << 8) - 1))
-      gcc_unreachable();
+      FAIL;
   }
 )
 
@@ -56,17 +71,27 @@
     if (GET_CODE (operand1) == SUBREG
         && GET_CODE (XEXP (operand1, 0)) == SYMBOL_REF)
       FAIL;
+    /* Similarly for (SUBREG (CONST (PLUS (SYMBOL_REF)))).  */
+    if (GET_CODE (operand1) == SUBREG
+	&& GET_CODE (XEXP (operand1, 0)) == CONST
+        && GET_CODE (XEXP (XEXP (operand1, 0), 0)) == PLUS
+        && GET_CODE (XEXP (XEXP (XEXP (operand1, 0), 0), 0)) == SYMBOL_REF)
+      FAIL;
   }
 )
 
-(define_expand "movsi"
-  [(set (match_operand:SI 0 "nonimmediate_operand")
-	(match_operand:SI 1 "general_operand"))]
+(define_insn_and_split "movsi"
+  [(set (match_operand:SI 0 "nonimmediate_operand" "=vYS,v,Wfr")
+	(match_operand:SI 1 "general_operand" "viYS,Wfr,v"))]
   ""
-  {
-    rl78_expand_movsi (operands);
-    DONE;
-  }
+  "#"
+  ""
+  [(set (match_operand:HI 2 "nonimmediate_operand")
+	(match_operand:HI 4 "general_operand"))
+   (set (match_operand:HI 3 "nonimmediate_operand")
+	(match_operand:HI 5 "general_operand"))]
+  "rl78_split_movsi (operands);"
+  [(set_attr "valloc" "op1")]
 )
 
 ;;---------- Conversions ------------------------
@@ -200,13 +225,33 @@
 )
 
 (define_expand "ashrsi3"
-  [(set (match_operand:SI               0 "register_operand")
-	(ashiftrt:SI (match_operand:SI  1 "register_operand")
-		      (match_operand:SI 2 "immediate_operand")))
+  [(parallel [(set (match_operand:SI               0 "nonimmediate_operand")
+		   (ashiftrt:SI (match_operand:SI  1 "nonimmediate_operand")
+				(match_operand:SI  2 "nonmemory_operand")))
+	      (clobber (reg:HI X_REG))])
    ]
   ""
-  "if (GET_CODE (operands[2]) != CONST_INT)
-     FAIL;"
+  ""
+)
+
+(define_expand "lshrsi3"
+  [(parallel [(set (match_operand:SI               0 "nonimmediate_operand")
+		   (lshiftrt:SI (match_operand:SI  1 "nonimmediate_operand")
+				(match_operand:SI  2 "nonmemory_operand")))
+	      (clobber (reg:HI X_REG))])
+   ]
+  ""
+  ""
+)
+
+(define_expand "ashlsi3"
+  [(parallel [(set (match_operand:SI               0 "nonimmediate_operand")
+	(ashift:SI (match_operand:SI  1 "nonimmediate_operand")
+		      (match_operand:SI 2 "nonmemory_operand")))
+	      (clobber (reg:HI X_REG))])
+   ]
+  ""
+  ""
 )
 
 ;;---------- Branching ------------------------
@@ -254,3 +299,16 @@
   ""
   "rl78_expand_compare (operands);"
 )
+
+(define_expand "cbranchsi4"
+  [(parallel [(set (pc) (if_then_else
+			 (match_operator 0 "rl78_cmp_operator"
+					 [(match_operand:SI 1 "general_operand")
+					  (match_operand:SI 2 "nonmemory_operand")])
+			 (label_ref (match_operand 3 "" ""))
+			 (pc)))
+	      (clobber (reg:HI AX_REG))
+	      ])]
+  "1"
+  "rl78_expand_compare (operands);"
+)

gcc/config/rl78/rl78-protos.h

@@ -21,6 +21,7 @@
 void		rl78_emit_eh_epilogue (rtx);
 void		rl78_expand_compare (rtx *);
 void		rl78_expand_movsi (rtx *);
+void		rl78_split_movsi (rtx *);
 int		rl78_force_nonfar_2 (rtx *, rtx (*gen)(rtx,rtx));
 int		rl78_force_nonfar_3 (rtx *, rtx (*gen)(rtx,rtx,rtx));
 void		rl78_expand_eh_epilogue (rtx);

gcc/config/rl78/rl78-real.md

@@ -312,11 +312,26 @@
    call\t%A1"
   )
 
+(define_insn "cbranchqi4_real_signed"
+  [(set (pc) (if_then_else
+	      (match_operator 0 "rl78_cmp_operator_signed"
+			      [(match_operand:QI 1 "general_operand" "A,A,A")
+			       (match_operand:QI 2 "general_operand" "ISqi,i,v")])
+              (label_ref (match_operand 3 "" ""))
+	      (pc)))]
+  "rl78_real_insns_ok ()"
+  "@
+   cmp\t%1, %2 \;xor1 CY,%1.7\;not1 CY\;sk%c0 \;br\t!!%3
+   cmp\t%1, %2 \;xor1 CY,%1.7\;sk%c0 \;br\t!!%3
+   cmp\t%1, %2 \;xor1 CY,%1.7\;xor1 CY,%2.7\;sk%c0 \;br\t!!%3"
+  )
+
+
 (define_insn "*cbranchqi4_real"
   [(set (pc) (if_then_else
 	      (match_operator 0 "rl78_cmp_operator_real"
-			      [(match_operand:QI 1 "general_operand" "Wabvaxbc,a,          v,bcdehl")
-			       (match_operand:QI 2 "general_operand" "M,       irWhlWh1Whb,i,a")])
+			      [(match_operand:QI 1 "general_operand" "Wabvaxbc,a,              v,bcdehl")
+			       (match_operand:QI 2 "general_operand" "M,       irvWabWhlWh1Whb,i,a")])
               (label_ref (match_operand 3 "" ""))
 	      (pc)))]
   "rl78_real_insns_ok ()"
@@ -327,13 +342,120 @@
    cmp\t%1, %2 \;sk%c0 \;br\t!!%3"
   )
 
-(define_insn "*cbranchhi4_real"
+(define_insn "cbranchhi4_real_signed"
   [(set (pc) (if_then_else
-	      (match_operator 0 "rl78_cmp_operator_real"
-			      [(match_operand:HI 1 "general_operand" "A")
-			       (match_operand:HI 2 "general_operand" "iBDTWhlWh1")])
-              (label_ref (match_operand 3 "" ""))
+	      (match_operator 0 "rl78_cmp_operator_signed"
+			      [(match_operand:HI 1 "general_operand" "A,A,A,vR")
+			       (match_operand:HI 2 "general_operand" "IShi,i,v,1")])
+              (label_ref (match_operand 3))
 	      (pc)))]
   "rl78_real_insns_ok ()"
+  "@
+   cmpw\t%1, %2 \;xor1 CY,%Q1.7\;not1 CY\;sk%c0 \;br\t!!%3
+   cmpw\t%1, %2 \;xor1 CY,%Q1.7\;sk%c0 \;br\t!!%3
+   cmpw\t%1, %2 \;xor1 CY,%Q1.7\;xor1 CY,%Q2.7\;sk%c0 \;br\t!!%3
+   %z0\t!!%3"
+  )
+
+(define_insn "cbranchhi4_real"
+  [(set (pc) (if_then_else
+	      (match_operator                    0 "rl78_cmp_operator_real"
+			      [(match_operand:HI 1 "general_operand" "A,vR")
+			       (match_operand:HI 2 "general_operand" "iBDTvWabWhlWh1,1")])
+              (label_ref (match_operand          3 "" ""))
+	      (pc)))]
+  "rl78_real_insns_ok ()"
+  "@
+  cmpw\t%1, %2 \;sk%c0 \;br\t!!%3
+  %z0\t!!%3"
+  )
+
+(define_insn "cbranchhi4_real_inverted"  
+  [(set (pc) (if_then_else
+	      (match_operator                    0 "rl78_cmp_operator_real"
+			      [(match_operand:HI 1 "general_operand" "A")
+			       (match_operand:HI 2 "general_operand" "iBDTvWabWhlWh1")])
+	      (pc)
+              (label_ref (match_operand          3 "" ""))))]
+  "rl78_real_insns_ok ()"
   "cmpw\t%1, %2 \;sk%c0 \;br\t!!%3"
   )
+
+(define_insn "cbranchsi4_real_lt"
+  [(set (pc) (if_then_else
+	      (lt (match_operand:SI 0 "general_operand" "U,vWabWhlWh1")
+		  (const_int 0))
+              (label_ref (match_operand 1 "" ""))
+	      (pc)))
+   (clobber (reg:HI AX_REG))
+   ]
+  "rl78_real_insns_ok ()"
+  "@
+   mov a, %E0 \;mov1 CY,a.7 \;sknc \;br\t!!%1
+   mov1 CY,%E0.7 \;sknc \;br\t!!%1"
+  )
+
+(define_insn "cbranchsi4_real_ge"
+  [(set (pc) (if_then_else
+	      (ge (match_operand:SI 0 "general_operand" "U,vWabWhlWh1")
+		  (const_int 0))
+              (label_ref (match_operand 1 "" ""))
+	      (pc)))
+   (clobber (reg:HI AX_REG))
+   ]
+  "rl78_real_insns_ok ()"
+  "@
+   mov a, %E0 \;mov1 CY,a.7 \;skc \;br\t!!%1
+   mov1 CY,%E0.7 \;skc \;br\t!!%1"
+  )
+
+(define_insn "cbranchsi4_real_signed"
+  [(set (pc) (if_then_else
+	      (match_operator 0 "rl78_cmp_operator_signed"
+			      [(match_operand:SI 1 "nonimmediate_operand" "vU,vU,vU")
+			       (match_operand:SI 2 "nonmemory_operand" "ISsi,i,v")])
+              (label_ref (match_operand 3 "" ""))
+	      (pc)))
+   (clobber (reg:HI AX_REG))
+   ]
+  "rl78_real_insns_ok ()"
+  "@
+   movw ax,%H1 \;cmpw  ax, %H2 \;xor1 CY,a.7\;not1 CY\;      movw ax,%h1 \;sknz \;cmpw  ax, %h2 \;sk%c0 \;br\t!!%3
+   movw ax,%H1 \;cmpw  ax, %H2 \;xor1 CY,a.7\;               movw ax,%h1 \;sknz \;cmpw  ax, %h2 \;sk%c0 \;br\t!!%3
+   movw ax,%H1 \;cmpw  ax, %H2 \;xor1 CY,a.7\;xor1 CY,%E2.7\;movw ax,%h1 \;sknz \;cmpw  ax, %h2 \;sk%c0 \;br\t!!%3"
+  )
+
+(define_insn "cbranchsi4_real"
+  [(set (pc) (if_then_else
+	      (match_operator 0 "rl78_cmp_operator_real"
+			      [(match_operand:SI 1 "general_operand" "vUi")
+			       (match_operand:SI 2 "general_operand" "iWhlWh1v")])
+              (label_ref (match_operand 3 "" ""))
+	      (pc)))
+   (clobber (reg:HI AX_REG))
+   ]
+  "rl78_real_insns_ok ()"
+  "movw ax,%H1 \;cmpw  ax, %H2 \;movw ax,%h1 \;sknz \;cmpw  ax, %h2 \;sk%c0 \;br\t!!%3"
+  )
+
+;; Peephole to match:
+;;
+;;     (set (mem (sp)) (ax))
+;;     (set (ax) (mem (sp)))
+;; or:
+;;     (set (mem (plus (sp) (const)) (ax))
+;;     (set (ax) (mem (plus (sp) (const))))
+;;
+;; which can be generated as the last instruction of the conversion
+;; of one virtual insn into a real insn and the first instruction of
+;; the conversion of the following virtual insn.
+
+(define_peephole2
+  [(set (match_operand:HI 0 "rl78_stack_based_mem")
+	(reg:HI AX_REG))
+   (set (reg:HI AX_REG)
+	(match_dup 0))]
+  ""
+  [(set (match_dup 0) (reg:HI AX_REG))]
+  )
+

gcc/config/rl78/rl78.md

@@ -35,7 +35,7 @@
 
    (FP_REG 22)
    (SP_REG 32)
-   (CC_REG 33)
+   (CC_REG 34)
    (ES_REG 35)
    (CS_REG 36)
 
@@ -205,33 +205,76 @@
 ;; efficient than anything else.
 
 (define_expand "addsi3"
-  [(set (match_operand:SI          0 "register_operand" "=&v")
-	(plus:SI (match_operand:SI 1 "nonmemory_operand" "vi")
-		 (match_operand    2 "nonmemory_operand" "vi")))
+  [(set (match_operand:SI          0 "nonimmediate_operand" "=&vm")
+	(plus:SI (match_operand:SI 1 "general_operand"      "vim")
+		 (match_operand    2 "general_operand"      "vim")))
    ]
   ""
-  "if (!nonmemory_operand (operands[1], SImode))
-     operands[1] = force_reg (SImode, operands[1]);
-   if (!nonmemory_operand (operands[1], SImode))
-     operands[2] = force_reg (SImode, operands[2]);"
+  "emit_insn (gen_addsi3_internal_virt (operands[0], operands[1], operands[2]));
+   DONE;"
 )
 
-(define_insn "addsi3_internal"
-  [(set (match_operand:SI          0 "register_operand" "=&v")
-	(plus:SI (match_operand:SI 1 "nonmemory_operand" "vi")
-		 (match_operand:SI 2 "nonmemory_operand" "vi")))
+(define_insn "addsi3_internal_virt"
+  [(set (match_operand:SI          0 "nonimmediate_operand" "=v,&vm, vm")
+	(plus:SI (match_operand:SI 1 "general_operand"      "0, vim, vim")
+		 (match_operand    2 "general_operand"      "vim,vim,vim")))
+   (clobber (reg:HI AX_REG))
+   (clobber (reg:HI BC_REG))
    ]
+  "rl78_virt_insns_ok ()"
   ""
-  "; addSI macro %0 = %1 + %2
-	movw	ax, %h1
-	addw	ax, %h2
-	movw	%h0, ax
-	movw	ax,%H1
-	sknc
-	incw	ax
-	addw	ax,%H2
-	movw	%H0,ax
-	; end of addSI macro"
+  [(set_attr "valloc" "macax")]
+)
+
+(define_insn "addsi3_internal_real"
+  [(set (match_operand:SI          0 "nonimmediate_operand" "=v,&vU, vU")
+	(plus:SI (match_operand:SI 1 "general_operand"      "+0, viU, viU")
+		 (match_operand    2 "general_operand"      "viWabWhlWh1,viWabWhlWh1,viWabWhlWh1")))
+   (clobber (reg:HI AX_REG))
+   (clobber (reg:HI BC_REG))
+   ]
+  "rl78_real_insns_ok ()"
+  "@
+   movw ax,%h1 \;addw ax,%h2 \;movw %h0, ax \;movw ax,%H1 \;sknc \;incw ax \;addw ax,%H2 \;movw %H0,ax
+   movw ax,%h1 \;addw ax,%h2 \;movw %h0, ax \;movw ax,%H1 \;sknc \;incw ax \;addw ax,%H2 \;movw %H0,ax
+   movw ax,%h1 \;addw ax,%h2 \;movw bc,  ax \;movw ax,%H1 \;sknc \;incw ax \;addw ax,%H2 \;movw %H0,ax \;movw ax,bc \;movw %h0, ax"
+  [(set_attr "valloc" "macax")]
+)
+
+(define_expand "subsi3"
+  [(set (match_operand:SI           0 "nonimmediate_operand" "=&vm")
+	(minus:SI (match_operand:SI 1 "general_operand"      "vim")
+		  (match_operand    2 "general_operand"    "vim")))
+   ]
+  ""
+  "emit_insn (gen_subsi3_internal_virt (operands[0], operands[1], operands[2]));
+  DONE;"
+)
+
+(define_insn "subsi3_internal_virt"
+  [(set (match_operand:SI           0 "nonimmediate_operand" "=v,&vm, vm")
+	(minus:SI (match_operand:SI 1 "general_operand"      "0, vim, vim")
+		  (match_operand    2 "general_operand"      "vim,vim,vim")))
+   (clobber (reg:HI AX_REG))
+   (clobber (reg:HI BC_REG))
+   ]
+  "rl78_virt_insns_ok ()"
+  ""
+  [(set_attr "valloc" "macax")]
+)
+
+(define_insn "subsi3_internal_real"
+  [(set (match_operand:SI           0 "nonimmediate_operand" "=v,&vU, vU")
+	(minus:SI (match_operand:SI 1 "general_operand"      "+0, viU, viU")
+		  (match_operand    2 "general_operand"      "viWabWhlWh1,viWabWhlWh1,viWabWhlWh1")))
+   (clobber (reg:HI AX_REG))
+   (clobber (reg:HI BC_REG))
+   ]
+  "rl78_real_insns_ok ()"
+  "@
+   movw ax,%h1 \;subw ax,%h2 \;movw %h0, ax \;movw ax,%H1 \;sknc \;decw ax \;subw ax,%H2 \;movw %H0,ax
+   movw ax,%h1 \;subw ax,%h2 \;movw %h0, ax \;movw ax,%H1 \;sknc \;decw ax \;subw ax,%H2 \;movw %H0,ax
+   movw ax,%h1 \;subw ax,%h2 \;movw bc,  ax \;movw ax,%H1 \;sknc \;decw ax \;subw ax,%H2 \;movw %H0,ax \;movw ax,bc \;movw %h0, ax"
   [(set_attr "valloc" "macax")]
 )
 
@@ -255,7 +298,7 @@
 
 (define_expand "mulsi3"
   [(set (match_operand:SI          0 "register_operand" "=&v")
-	(mult:SI (match_operand:SI 1 "nonmemory_operand" "vi")
+	(mult:SI (match_operand:SI 1 "general_operand" "+vim")
 		 (match_operand:SI 2 "nonmemory_operand" "vi")))
    ]
   "! RL78_MUL_NONE"
@@ -319,8 +362,8 @@
 ;; bits of the result).
 (define_insn "mulsi3_rl78"
   [(set (match_operand:SI          0 "register_operand" "=&v")
-	(mult:SI (match_operand:SI 1 "nonmemory_operand" "vi")
-		 (match_operand:SI 2 "nonmemory_operand" "vi")))
+	(mult:SI (match_operand:SI 1 "general_operand" "+viU")
+		 (match_operand:SI 2 "general_operand" "vi")))
    ]
   "RL78_MUL_RL78"
   "; mulsi macro %0 = %1 * %2
@@ -349,8 +392,8 @@
 ;; Warning: this matches the silicon not the documentation.
 (define_insn "mulsi3_g13"
   [(set (match_operand:SI          0 "register_operand" "=&v")
-	(mult:SI (match_operand:SI 1 "nonmemory_operand" "vi")
-		 (match_operand:SI 2 "nonmemory_operand" "vi")))
+	(mult:SI (match_operand:SI 1 "general_operand" "viU")
+		 (match_operand:SI 2 "general_operand" "viU")))
    ]
   "RL78_MUL_G13"
   "; mulsi macro %0 = %1 * %2