Fix gcc.dg/vect/vect-shift-1.c failure.

* config/ia64/vect.md (ashl<mode>3, ashr<mode>3, lshr<mode>3): Use
DImode not VECINT24 for operand 2.

From-SVN: r105113

gcc/ChangeLog

 2005-10-07  James E. Wilson  <wilson@specifix.com>
 
+	* config/ia64/vect.md (ashl<mode>3, ashr<mode>3, lshr<mode>3): Use
+	DImode not VECINT24 for operand 2.
+
 	PR target/23644
 	* doc/invoke.texi (IA-64 Options, item -mtune): Renamed from
 	-mtune-arch.

gcc/config/ia64/vect.md

@@ -318,7 +318,7 @@
   [(set (match_operand:VECINT24 0 "gr_register_operand" "=r")
 	(ashift:VECINT24
 	  (match_operand:VECINT24 1 "gr_register_operand" "r")
-	  (match_operand:VECINT24 2 "gr_reg_or_5bit_operand" "rn")))]
+	  (match_operand:DI 2 "gr_reg_or_5bit_operand" "rn")))]
   ""
   "pshl<vecsize> %0 = %1, %2"
   [(set_attr "itanium_class" "mmshf")])
@@ -327,7 +327,7 @@
   [(set (match_operand:VECINT24 0 "gr_register_operand" "=r")
 	(ashiftrt:VECINT24
 	  (match_operand:VECINT24 1 "gr_register_operand" "r")
-	  (match_operand:VECINT24 2 "gr_reg_or_5bit_operand" "rn")))]
+	  (match_operand:DI 2 "gr_reg_or_5bit_operand" "rn")))]
   ""
   "pshr<vecsize> %0 = %1, %2"
   [(set_attr "itanium_class" "mmshf")])
@@ -336,7 +336,7 @@
   [(set (match_operand:VECINT24 0 "gr_register_operand" "=r")
 	(lshiftrt:VECINT24
 	  (match_operand:VECINT24 1 "gr_register_operand" "r")
-	  (match_operand:VECINT24 2 "gr_reg_or_5bit_operand" "rn")))]
+	  (match_operand:DI 2 "gr_reg_or_5bit_operand" "rn")))]
   ""
   "pshr<vecsize>.u %0 = %1, %2"
   [(set_attr "itanium_class" "mmshf")])