Skip to content

R
riscv-gcc-1
Commit 3daa7bbf by Trevor Saunders Committed by Trevor Saunders
Options

remove score-* support 

libgcc/ChangeLog:

2014-10-04  Trevor Saunders  <tsaunders@mozilla.com>

	* config.host: Remove support for score-*.

contrib/ChangeLog:

2014-10-04  Trevor Saunders  <tsaunders@mozilla.com>

	* compare-all-tests: Don't test score-*.
	* config-list.mk: Likewise.

gcc/ChangeLog:

2014-10-04  Trevor Saunders  <tsaunders@mozilla.com>

	* common/config/score/score-common.c: Remove.
	* config.gcc: Remove support for score-*.
	* config/score/constraints.md: Remove.
	* config/score/elf.h: Remove.
	* config/score/predicates.md: Remove.
	* config/score/score-conv.h: Remove.
	* config/score/score-generic.md: Remove.
	* config/score/score-modes.def: Remove.
	* config/score/score-protos.h: Remove.
	* config/score/score.c: Remove.
	* config/score/score.h: Remove.
	* config/score/score.md: Remove.
	* config/score/score.opt: Remove.
	* doc/md.texi: Don't document score-*.

From-SVN: r215889
parent bf55b4a0
Showing with 33 additions and 794 deletions
contrib/ChangeLog
2014-10-04 Trevor Saunders <tsaunders@mozilla.com>
* compare-all-tests: Don't test score-*.
* config-list.mk: Likewise.
2014-10-02 Segher Boessenkool <segher@kernel.crashing.org>
* dg-extract-results.py (output_variation): Always sort if do_sum.
......
contrib/compare-all-tests
......@@ -31,12 +31,11 @@ mn10300_opts='-mam33 -mam33-2'
pa_opts='-march=2.0 -march=1.0 -march=1.1'
ppc_opts='-m32 -m64'
s390_opts='-m31 -m31/-mzarch -m64'
score_opts='-mscore3 -mscore7'
sh64_opts='-m5-32media -m5-32media-nofpu -m5-64media -m5-64media-nofpu -m5-compact -m5-compact-nofpu'
sh_opts='-m3 -m3e -m4 -m4a -m4al -m4/-mieee -m1 -m1/-mno-cbranchdi -m2a -m2a/-mieee -m2e -m2e/-mieee'
sparc_opts='-mcpu=v8/-m32 -mcpu=v9/-m32 -m64'
all_targets='alpha arm avr bfin cris fr30 frv h8300 ia64 iq2000 m32c m32r m68k mcore mips mmix mn10300 pa pdp11 ppc score sh sh64 sparc spu v850 vax xstormy16 xtensa' # e500
all_targets='alpha arm avr bfin cris fr30 frv h8300 ia64 iq2000 m32c m32r m68k mcore mips mmix mn10300 pa pdp11 ppc sh sh64 sparc spu v850 vax xstormy16 xtensa' # e500
test_one_file ()
{
......
contrib/config-list.mk
......@@ -76,7 +76,7 @@ LIST = aarch64-elf aarch64-linux-gnu \
x86_64-knetbsd-gnu x86_64-w64-mingw32 \
x86_64-mingw32OPT-enable-sjlj-exceptions=yes xstormy16-elf xtensa-elf \
xtensa-linux \
i686-interix3OPT-enable-obsolete score-elfOPT-enable-obsolete
i686-interix3OPT-enable-obsolete
LOGFILES = $(patsubst %,log/%-make.out,$(LIST))
all: $(LOGFILES)
......
gcc/ChangeLog
2014-10-04 Trevor Saunders <tsaunders@mozilla.com>
* common/config/score/score-common.c: Remove.
* config.gcc: Remove support for score-*.
* config/score/constraints.md: Remove.
* config/score/elf.h: Remove.
* config/score/predicates.md: Remove.
* config/score/score-conv.h: Remove.
* config/score/score-generic.md: Remove.
* config/score/score-modes.def: Remove.
* config/score/score-protos.h: Remove.
* config/score/score.c: Remove.
* config/score/score.h: Remove.
* config/score/score.md: Remove.
* config/score/score.opt: Remove.
* doc/md.texi: Don't document score-*.
2014-10-04 Trevor Saunders <tsaunders@mozilla.com>
PR pch/63429
* genconditions.c: Directly include ggc.h before rtl.h.
PR pch/63429
* genconditions.c: Directly include ggc.h before rtl.h.
2014-10-03 Jan Hubicka <hubicka@ucw.cz>
gcc/common/config/score/score-common.c deleted 100644 → 0
/* Common hooks for Sunplus S+CORE.
Copyright (C) 2005-2014 Free Software Foundation, Inc.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
You should have received a copy of the GNU General Public License
along with GCC; see the file COPYING3. If not see
<http://www.gnu.org/licenses/>. */
#include "config.h"
#include "system.h"
#include "coretypes.h"
#include "tm.h"
#include "common/common-target.h"
#include "common/common-target-def.h"
#include "opts.h"
#include "flags.h"
/* Implement TARGET_OPTION_OPTIMIZATION_TABLE. */
static const struct default_options score_option_optimization_table[] =
{
{ OPT_LEVELS_1_PLUS, OPT_fomit_frame_pointer, NULL, 1 },
{ OPT_LEVELS_NONE, 0, NULL, 0 }
};
#undef TARGET_DEFAULT_TARGET_FLAGS
#define TARGET_DEFAULT_TARGET_FLAGS TARGET_DEFAULT
#undef TARGET_HANDLE_OPTION
#define TARGET_HANDLE_OPTION score_handle_option
#undef TARGET_OPTION_OPTIMIZATION_TABLE
#define TARGET_OPTION_OPTIMIZATION_TABLE score_option_optimization_table
#define MASK_ALL_CPU_BITS (MASK_SCORE7 | MASK_SCORE7D)
/* Implement TARGET_HANDLE_OPTION. */
static bool
score_handle_option (struct gcc_options *opts,
struct gcc_options *opts_set ATTRIBUTE_UNUSED,
const struct cl_decoded_option *decoded,
location_t loc ATTRIBUTE_UNUSED)
{
size_t code = decoded->opt_index;
int value = decoded->value;
switch (code)
{
case OPT_mscore7d:
opts->x_target_flags &= ~(MASK_ALL_CPU_BITS);
opts->x_target_flags |= MASK_SCORE7 | MASK_SCORE7D;
return true;
case OPT_march_:
opts->x_target_flags &= ~(MASK_ALL_CPU_BITS);
opts->x_target_flags |= value;
return true;
default:
return true;
}
}
struct gcc_targetm_common targetm_common = TARGETM_COMMON_INITIALIZER;
gcc/config.gcc
......@@ -236,7 +236,8 @@ md_file=
# Obsolete configurations.
case ${target} in
score-* \
# Currently there are no obsolete targets.
nothing \
)
if test "x$enable_obsolete" != xyes; then
echo "*** Configuration ${target} is obsolete." >&2
......@@ -432,10 +433,6 @@ powerpc*-*-*)
rs6000*-*-*)
extra_options="${extra_options} g.opt fused-madd.opt rs6000/rs6000-tables.opt"
;;
score*-*-*)
cpu_type=score
extra_options="${extra_options} g.opt"
;;
sparc*-*-*)
cpu_type=sparc
c_target_objs="sparc-c.o"
......@@ -2441,11 +2438,6 @@ s390x-ibm-tpf*)
thread_file='tpf'
extra_options="${extra_options} s390/tpf.opt"
;;
score-*-elf)
gas=yes
gnu_ld=yes
tm_file="dbxelf.h elfos.h score/elf.h score/score.h newlib-stdint.h"
;;
sh-*-elf* | sh[12346l]*-*-elf* | \
sh-*-linux* | sh[2346lbe]*-*-linux* | \
sh-*-netbsdelf* | shl*-*-netbsdelf* | sh5-*-netbsd* | sh5l*-*-netbsd* | \
......
gcc/config/score/constraints.md deleted 100644 → 0
;; Constraint definitions for S+CORE
;; Copyright (C) 2005-2014 Free Software Foundation, Inc.
;; Contributed by Sunnorth.
;; This file is part of GCC.
;; GCC is free software; you can redistribute it and/or modify it
;; under the terms of the GNU General Public License as published
;; by the Free Software Foundation; either version 3, or (at your
;; option) any later version.
;; GCC is distributed in the hope that it will be useful, but WITHOUT
;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
;; License for more details.
;; You should have received a copy of the GNU General Public License
;; along with GCC; see the file COPYING3. If not see
;; <http://www.gnu.org/licenses/>. */
;; -------------------------------------------------------------------------
;; Constraints
;; -------------------------------------------------------------------------
;; Register constraints.
(define_register_constraint "d" "G32_REGS"
"r0 to r31")
(define_register_constraint "e" "G16_REGS"
"r0 to r15")
(define_register_constraint "t" "T32_REGS"
"r8 to r11 | r22 to r27")
(define_register_constraint "h" "HI_REG"
"hi")
(define_register_constraint "l" "LO_REG"
"lo")
(define_register_constraint "x" "CE_REGS"
"hi + lo")
(define_register_constraint "q" "CN_REG"
"cnt")
(define_register_constraint "y" "LC_REG"
"lcb")
(define_register_constraint "z" "SC_REG"
"scb")
(define_register_constraint "a" "SP_REGS"
"cnt + lcb + scb")
(define_register_constraint "c" "CR_REGS"
"cr0 to cr15")
;; Integer constant constraints.
(define_constraint "I"
"High 16-bit constant (32-bit constant with 16 LSBs zero)."
(and (match_code "const_int")
(match_test "(ival & 0xffff) == 0")))
(define_constraint "J"
"Unsigned 5 bit integer (in the range 0 to 31)."
(and (match_code "const_int")
(match_test "ival >= 0 && ival <= 31")))
(define_constraint "K"
"Unsigned 16 bit integer (in the range 0 to 65535)."
(and (match_code "const_int")
(match_test "ival >= 0 && ival <= 65535")))
(define_constraint "L"
"Signed 16 bit integer (in the range −32768 to 32767)."
(and (match_code "const_int")
(match_test "ival >= -32768 && ival <= 32767")))
(define_constraint "M"
"Unsigned 14 bit integer (in the range 0 to 16383)."
(and (match_code "const_int")
(match_test "ival >= 0 && ival <= 16383")))
(define_constraint "N"
"Signed 14 bit integer (in the range −8192 to 8191)."
(and (match_code "const_int")
(match_test "ival >= -8192 && ival <= 8191")))
(define_constraint "Z"
"Any SYMBOL_REF."
(and (match_code "symbol_ref")
(match_test "GET_CODE (op) == SYMBOL_REF")))
gcc/config/score/elf.h deleted 100644 → 0
/* elf.h for Sunplus S+CORE processor
Copyright (C) 2005-2014 Free Software Foundation, Inc.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
You should have received a copy of the GNU General Public License
along with GCC; see the file COPYING3. If not see
<http://www.gnu.org/licenses/>. */
#define OBJECT_FORMAT_ELF
/* Biggest alignment supported by the object file format of this machine. */
#undef MAX_OFILE_ALIGNMENT
#define MAX_OFILE_ALIGNMENT (32768 * 8)
/* Switch into a generic section. */
#undef TARGET_ASM_NAMED_SECTION
#define TARGET_ASM_NAMED_SECTION default_elf_asm_named_section
/* The following macro defines the format used to output the second
operand of the .type assembler directive. */
#define TYPE_OPERAND_FMT "@%s"
#undef TYPE_ASM_OP
#define TYPE_ASM_OP "\t.type\t"
#undef SIZE_ASM_OP
#define SIZE_ASM_OP "\t.size\t"
/* A c expression whose value is a string containing the
assembler operation to identify the following data as
uninitialized global data. */
#ifndef BSS_SECTION_ASM_OP
#define BSS_SECTION_ASM_OP "\t.section\t.bss"
#endif
#ifndef ASM_OUTPUT_ALIGNED_BSS
#define ASM_OUTPUT_ALIGNED_BSS asm_output_aligned_bss
#endif
#define ASM_OUTPUT_DEF(FILE, LABEL1, LABEL2) \
do { \
fputc ('\t', FILE); \
assemble_name (FILE, LABEL1); \
fputs (" = ", FILE); \
assemble_name (FILE, LABEL2); \
fputc ('\n', FILE); \
} while (0)
/* This is how we tell the assembler that a symbol is weak. */
#undef ASM_WEAKEN_LABEL
#define ASM_WEAKEN_LABEL(FILE, NAME) ASM_OUTPUT_WEAK_ALIAS (FILE, NAME, 0)
#define ASM_OUTPUT_WEAK_ALIAS(FILE, NAME, VALUE) \
do { \
fputs ("\t.weak\t", FILE); \
assemble_name (FILE, NAME); \
if (VALUE) \
{ \
fputc (' ', FILE); \
assemble_name (FILE, VALUE); \
} \
fputc ('\n', FILE); \
} while (0)
#define MAKE_DECL_ONE_ONLY(DECL) (DECL_WEAK (DECL) = 1)
/* On elf, we *do* have support for the .init and .fini sections, and we
can put stuff in there to be executed before and after `main'. We let
crtstuff.c and other files know this by defining the following symbols.
The definitions say how to change sections to the .init and .fini
sections. This is the same for all known elf assemblers. */
#undef INIT_SECTION_ASM_OP
#define INIT_SECTION_ASM_OP "\t.section\t.init"
#undef FINI_SECTION_ASM_OP
#define FINI_SECTION_ASM_OP "\t.section\t.fini"
/* Don't set the target flags, this is done by the linker script */
#undef LIB_SPEC
#define LIB_SPEC ""
#undef STARTFILE_SPEC
#define STARTFILE_SPEC "crti%O%s crtbegin%O%s"
#undef ENDFILE_SPEC
#define ENDFILE_SPEC "crtend%O%s crtn%O%s"
gcc/config/score/predicates.md deleted 100644 → 0
;; Predicate definitions for Sunplus S+CORE.
;; Copyright (C) 2005-2014 Free Software Foundation, Inc.
;;
;; This file is part of GCC.
;;
;; GCC is free software; you can redistribute it and/or modify
;; it under the terms of the GNU General Public License as published by
;; the Free Software Foundation; either version 3, or (at your option)
;; any later version.
;;
;; GCC is distributed in the hope that it will be useful,
;; but WITHOUT ANY WARRANTY; without even the implied warranty of
;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
;; GNU General Public License for more details.
;;
;; You should have received a copy of the GNU General Public License
;; along with GCC; see the file COPYING3. If not see
;; <http://www.gnu.org/licenses/>.
(define_predicate "const_uimm5"
(match_code "const_int")
{
return IMM_IN_RANGE (INTVAL (op), 5, 0);
})
(define_predicate "const_simm12"
(match_code "const_int")
{
return IMM_IN_RANGE (INTVAL (op), 12, 1);
})
(define_predicate "const_simm15"
(match_code "const_int")
{
return IMM_IN_RANGE (INTVAL (op), 15, 1);
})
(define_predicate "arith_operand"
(ior (match_code "const_int")
(match_operand 0 "register_operand")))
(define_predicate "score_register_operand"
(match_code "reg,subreg")
{
if (GET_CODE (op) == SUBREG)
op = SUBREG_REG (op);
return (GET_CODE (op) == REG)
&& (REGNO (op) != CC_REGNUM);
})
(define_predicate "const_call_insn_operand"
(match_code "const,symbol_ref,label_ref")
{
enum score_symbol_type symbol_type;
return (score_symbolic_constant_p (op, &symbol_type)
&& (symbol_type == SYMBOL_GENERAL));
})
(define_predicate "call_insn_operand"
(ior (match_operand 0 "const_call_insn_operand")
(match_operand 0 "register_operand")))
(define_predicate "hireg_operand"
(and (match_code "reg")
(match_test "REGNO (op) == HI_REGNUM")))
(define_predicate "loreg_operand"
(and (match_code "reg")
(match_test "REGNO (op) == LO_REGNUM")))
(define_predicate "sr0_operand"
(and (match_code "reg")
(match_test "REGNO (op) == CN_REGNUM")))
(define_predicate "g32reg_operand"
(and (match_code "reg")
(match_test "GP_REG_P (REGNO (op))")))
(define_predicate "branch_n_operator"
(match_code "lt,ge"))
(define_predicate "branch_nz_operator"
(match_code "eq,ne,lt,ge"))
(define_predicate "score_load_multiple_operation"
(match_code "parallel")
{
int count = XVECLEN (op, 0);
int dest_regno;
int i;
/* Perform a quick check so we don't blow up below. */
if (count <= 1
|| GET_CODE (XVECEXP (op, 0, 0)) != SET
|| GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG
|| GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != MEM)
return 0;
dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0)));
for (i = 1; i < count; i++)
{
rtx elt = XVECEXP (op, 0, i);
if (GET_CODE (elt) != SET
|| GET_CODE (SET_DEST (elt)) != REG
|| GET_MODE (SET_DEST (elt)) != SImode
|| REGNO (SET_DEST (elt)) != (unsigned) (dest_regno + i)
|| GET_CODE (SET_SRC (elt)) != MEM
|| GET_MODE (SET_SRC (elt)) != SImode
|| GET_CODE (XEXP (SET_SRC (elt), 0)) != POST_INC)
return 0;
}
return 1;
})
(define_predicate "score_store_multiple_operation"
(match_code "parallel")
{
int count = XVECLEN (op, 0);
int src_regno;
int i;
/* Perform a quick check so we don't blow up below. */
if (count <= 1
|| GET_CODE (XVECEXP (op, 0, 0)) != SET
|| GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != MEM
|| GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != REG)
return 0;
src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0)));
for (i = 1; i < count; i++)
{
rtx elt = XVECEXP (op, 0, i);
if (GET_CODE (elt) != SET
|| GET_CODE (SET_SRC (elt)) != REG
|| GET_MODE (SET_SRC (elt)) != SImode
|| REGNO (SET_SRC (elt)) != (unsigned) (src_regno + i)
|| GET_CODE (SET_DEST (elt)) != MEM
|| GET_MODE (SET_DEST (elt)) != SImode
|| GET_CODE (XEXP (SET_DEST (elt), 0)) != PRE_DEC)
return 0;
}
return 1;
})
gcc/config/score/score-conv.h deleted 100644 → 0
/* score-conv.h for Sunplus S+CORE processor
Copyright (C) 2005-2014 Free Software Foundation, Inc.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
You should have received a copy of the GNU General Public License
along with GCC; see the file COPYING3. If not see
<http://www.gnu.org/licenses/>. */
#ifndef GCC_SCORE_CONV_H
#define GCC_SCORE_CONV_H
#define GP_REG_FIRST 0U
#define GP_REG_LAST 31U
#define GP_REG_NUM (GP_REG_LAST - GP_REG_FIRST + 1U)
#define GP_DBX_FIRST 0U
#define CE_REG_FIRST 48U
#define CE_REG_LAST 49U
#define CE_REG_NUM (CE_REG_LAST - CE_REG_FIRST + 1U)
#define ARG_REG_FIRST 4U
#define ARG_REG_LAST 7U
#define ARG_REG_NUM (ARG_REG_LAST - ARG_REG_FIRST + 1U)
#define REG_CONTAIN(REGNO, FIRST, NUM) \
((unsigned int)((int) (REGNO) - (FIRST)) < (NUM))
#define GP_REG_P(REGNO) REG_CONTAIN (REGNO, GP_REG_FIRST, GP_REG_NUM)
#define G8_REG_P(REGNO) REG_CONTAIN (REGNO, GP_REG_FIRST, 8)
#define G16_REG_P(REGNO) REG_CONTAIN (REGNO, GP_REG_FIRST, 16)
#define CE_REG_P(REGNO) REG_CONTAIN (REGNO, CE_REG_FIRST, CE_REG_NUM)
#define GR_REG_CLASS_P(C) ((C) == G16_REGS || (C) == G32_REGS)
#define SP_REG_CLASS_P(C) \
((C) == CN_REG || (C) == LC_REG || (C) == SC_REG || (C) == SP_REGS)
#define CP_REG_CLASS_P(C) \
((C) == CP1_REGS || (C) == CP2_REGS || (C) == CP3_REGS || (C) == CPA_REGS)
#define CE_REG_CLASS_P(C) \
((C) == HI_REG || (C) == LO_REG || (C) == CE_REGS)
#define UIMM_IN_RANGE(V, W) \
((V) >= 0 \
&& ((unsigned HOST_WIDE_INT) (V) \
<= (((unsigned HOST_WIDE_INT) 2 << ((W) - 1)) - 1)))
#define SIMM_IN_RANGE(V, W) \
((V) >= ((HOST_WIDE_INT) -1 << ((W) - 1)) \
&& (V) <= (((HOST_WIDE_INT) 1 << ((W) - 1)) - 1))
#define IMM_IN_RANGE(V, W, S) \
((S) ? SIMM_IN_RANGE (V, W) : UIMM_IN_RANGE (V, W))
#define IMM_IS_POW_OF_2(V, E1, E2) \
((V) >= ((unsigned HOST_WIDE_INT) 1 << (E1)) \
&& (V) <= ((unsigned HOST_WIDE_INT) 1 << (E2)) \
&& ((V) & ((V) - 1)) == 0)
enum score_symbol_type
{
SYMBOL_GENERAL,
SYMBOL_SMALL_DATA /* The symbol refers to something in a small data section */
};
#endif
gcc/config/score/score-generic.md deleted 100644 → 0
;; Machine description for Sunplus S+CORE
;; Sunplus S+CORE Pipeline Description
;; Copyright (C) 2005-2014 Free Software Foundation, Inc.
;; Contributed by Sunnorth.
;; This file is part of GCC.
;; GCC is free software; you can redistribute it and/or modify
;; it under the terms of the GNU General Public License as published by
;; the Free Software Foundation; either version 3, or (at your option)
;; any later version.
;; GCC is distributed in the hope that it will be useful,
;; but WITHOUT ANY WARRANTY; without even the implied warranty of
;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
;; GNU General Public License for more details.
;; You should have received a copy of the GNU General Public License
;; along with GCC; see the file COPYING3. If not see
;; <http://www.gnu.org/licenses/>.
(define_automaton "score")
(define_cpu_unit "core" "score")
(define_insn_reservation "memory" 3
(eq_attr "type" "load")
"core")
(define_insn_reservation "mul" 3
(eq_attr "type" "mul,div")
"core")
(define_insn_reservation "fce" 1
(eq_attr "type" "fce")
"core")
(define_insn_reservation "tsr" 1
(eq_attr "type" "tsr,fsr")
"core")
(define_insn_reservation "up_c" 1
(eq_attr "up_c" "yes")
"core")
gcc/config/score/score-modes.def deleted 100644 → 0
/* score-modes.def for Sunplus S+CORE processor
Copyright (C) 2005-2014 Free Software Foundation, Inc.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
You should have received a copy of the GNU General Public License
along with GCC; see the file COPYING3. If not see
<http://www.gnu.org/licenses/>. */
/* CC_NZmode should be used if the N (sign) and Z (zero) flag is set correctly.
CC_Nmode should be used if only the N flag is set correctly. */
CC_MODE (CC_N);
CC_MODE (CC_NZ);
gcc/config/score/score-protos.h deleted 100644 → 0
/* score-protos.h for Sunplus S+CORE processor
Copyright (C) 2005-2014 Free Software Foundation, Inc.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
You should have received a copy of the GNU General Public License
along with GCC; see the file COPYING3. If not see
<http://www.gnu.org/licenses/>. */
#ifndef GCC_SCORE_PROTOS_H
#define GCC_SCORE_PROTOS_H
/* Machine Print. */
enum score_mem_unit {SCORE_BYTE = 0, SCORE_HWORD = 1, SCORE_WORD = 2};
#define SCORE_ALIGN_UNIT(V, UNIT) !(V & ((1 << UNIT) - 1))
extern void score_prologue (void);
extern void score_epilogue (int sibcall_p);
extern void score_call (rtx *ops, bool sib);
extern void score_call_value (rtx *ops, bool sib);
extern void score_movdi (rtx *ops);
extern void score_zero_extract_andi (rtx *ops);
extern const char * score_linsn (rtx *ops, enum score_mem_unit unit, bool sign);
extern const char * score_sinsn (rtx *ops, enum score_mem_unit unit);
extern const char * score_limm (rtx *ops);
extern const char * score_move (rtx *ops);
extern bool score_unaligned_load (rtx* ops);
extern bool score_unaligned_store (rtx* ops);
extern bool score_block_move (rtx* ops);
extern int score_address_cost (rtx addr, enum machine_mode mode,
addr_space_t as, bool speed);
extern int score_address_p (enum machine_mode mode, rtx x, int strict);
extern int score_reg_class (int regno);
extern int score_hard_regno_mode_ok (unsigned int, enum machine_mode);
extern int score_const_ok_for_letter_p (HOST_WIDE_INT value, char c);
extern int score_extra_constraint (rtx op, char c);
extern rtx score_return_addr (int count, rtx frame);
extern int score_regno_mode_ok_for_base_p (int regno, int strict);
extern void score_init_cumulative_args (CUMULATIVE_ARGS *cum,
tree fntype, rtx libname);
extern void score_declare_object (FILE *stream, const char *name,
const char *directive, const char *fmt, ...);
extern int score_output_external (FILE *file, tree decl, const char *name);
extern enum reg_class score_secondary_reload_class (enum reg_class rclass,
enum machine_mode mode,
rtx x);
extern rtx score_function_value (const_tree valtype, const_tree func,
enum machine_mode mode);
extern enum reg_class score_preferred_reload_class (rtx x,
enum reg_class rclass);
extern HOST_WIDE_INT score_initial_elimination_offset (int from, int to);
extern void score_print_operand (FILE *file, rtx op, int letter);
extern void score_print_operand_address (FILE *file, rtx addr);
extern int score_symbolic_constant_p (rtx x,
enum score_symbol_type *symbol_type);
extern void score_movsicc (rtx *ops);
extern const char * score_select_add_imm (rtx *ops, bool set_cc);
extern const char * score_select (rtx *ops, const char *inst_pre, bool commu,
const char *letter, bool set_cc);
extern const char * score_output_casesi (rtx *operands);
extern const char * score_rpush (rtx *ops);
extern const char * score_rpop (rtx *ops);
extern bool score_rtx_costs (rtx x, int code, int outer_code, int opno,
int *total, bool speed);
#ifdef RTX_CODE
extern enum machine_mode score_select_cc_mode (enum rtx_code op, rtx x, rtx y);
#endif
extern struct extern_list *extern_head;
#endif /* GCC_SCORE_PROTOS_H */
gcc/config/score/score.opt deleted 100644 → 0
; Options for the Sunnorth port of the compiler.
; Copyright (C) 2005-2014 Free Software Foundation, Inc.
;
; This file is part of GCC.
;
; GCC is free software; you can redistribute it and/or modify it under
; the terms of the GNU General Public License as published by the Free
; Software Foundation; either version 3, or (at your option) any later
; version.
;
; GCC is distributed in the hope that it will be useful, but WITHOUT ANY
; WARRANTY; without even the implied warranty of MERCHANTABILITY or
; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
; for more details.
;
; You should have received a copy of the GNU General Public License
; along with GCC; see the file COPYING3. If not see
; <http://www.gnu.org/licenses/>.
meb
Target RejectNegative Report InverseMask(LITTLE_ENDIAN)
Generate big-endian code
mel
Target RejectNegative Report Mask(LITTLE_ENDIAN)
Generate little-endian code
mnhwloop
Target RejectNegative Report Mask(NHWLOOP)
Disable bcnz instruction
muls
Target RejectNegative Report Mask(ULS)
Enable unaligned load/store instruction
mscore7
Target RejectNegative Report Mask(SCORE7)
Support SCORE 7 ISA
mscore7d
Target RejectNegative Report Mask(SCORE7D)
Support SCORE 7D ISA
march=
Target RejectNegative Joined Enum(score_arch)
Specify the name of the target architecture
Enum
Name(score_arch) Type(int)
Known SCORE architectures (for use with the -march= option):
EnumValue
Enum(score_arch) String(score7) Value(MASK_SCORE7)
EnumValue
Enum(score_arch) String(score7d) Value(MASK_SCORE7 | MASK_SCORE7D)
gcc/doc/md.texi
......@@ -3673,75 +3673,6 @@ Shift count operand.
@end table
@item Score family---@file{config/score/score.h}
@table @code
@item d
Registers from r0 to r32.
@item e
Registers from r0 to r16.
@item t
r8---r11 or r22---r27 registers.
@item h
hi register.
@item l
lo register.
@item x
hi + lo register.
@item q
cnt register.
@item y
lcb register.
@item z
scb register.
@item a
cnt + lcb + scb register.
@item c
cr0---cr15 register.
@item b
cp1 registers.
@item f
cp2 registers.
@item i
cp3 registers.
@item j
cp1 + cp2 + cp3 registers.
@item I
High 16-bit constant (32-bit constant with 16 LSBs zero).
@item J
Unsigned 5 bit integer (in the range 0 to 31).
@item K
Unsigned 16 bit integer (in the range 0 to 65535).
@item L
Signed 16 bit integer (in the range @minus{}32768 to 32767).
@item M
Unsigned 14 bit integer (in the range 0 to 16383).
@item N
Signed 14 bit integer (in the range @minus{}8192 to 8191).
@item Z
Any SYMBOL_REF.
@end table
@item Xstormy16---@file{config/stormy16/stormy16.h}
@table @code
@item a
......
gcc/testsuite/g++.dg/cpp0x/constexpr-rom.C
// PR c++/49673: check that test_data goes into .rodata
// { dg-do compile { target c++11 } }
// { dg-additional-options -G0 { target { { alpha*-*-* frv*-*-* ia64-*-* lm32*-*-* m32r*-*-* microblaze*-*-* mips*-*-* nios2-*-* powerpc*-*-* rs6000*-*-* score*-*-* } && { ! { *-*-darwin* *-*-aix* alpha*-*-*vms* } } } } }
// { dg-additional-options -G0 { target { { alpha*-*-* frv*-*-* ia64-*-* lm32*-*-* m32r*-*-* microblaze*-*-* mips*-*-* nios2-*-* powerpc*-*-* rs6000*-*-* } && { ! { *-*-darwin* *-*-aix* alpha*-*-*vms* } } } } }
// { dg-final { scan-assembler "\\.rdata" { target mips*-*-* } } }
// { dg-final { scan-assembler "rodata" { target { { *-*-linux-gnu *-*-gnu* *-*-elf } && { ! mips*-*-* } } } } }
......
libgcc/ChangeLog
2014-10-04 Trevor Saunders <tsaunders@mozilla.com>
* config.host: Remove support for score-*.
2014-09-22 Joseph Myers <joseph@codesourcery.com>
* dfp-bit.h (LIBGCC2_LONG_DOUBLE_TYPE_SIZE): Remove.
......
libgcc/config.host
......@@ -167,9 +167,6 @@ powerpc*-*-*)
;;
rs6000*-*-*)
;;
score*-*-*)
cpu_type=score
;;
sparc64*-*-*)
cpu_type=sparc
;;
......@@ -1051,10 +1048,6 @@ s390x-ibm-tpf*)
extra_parts="crtbeginS.o crtendS.o"
md_unwind_header=s390/tpf-unwind.h
;;
score-*-elf)
tmake_file="${tmake_file} t-softfp-sfdf t-softfp-excl t-softfp"
extra_parts="$extra_parts crti.o crtn.o"
;;
sh-*-elf* | sh[12346l]*-*-elf*)
tmake_file="$tmake_file sh/t-sh t-crtstuff-pic t-fdpbit"
extra_parts="$extra_parts crt1.o crti.o crtn.o crtbeginS.o crtendS.o \
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment