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Commit 3d33d06b by Sofiane Naci Committed by Sofiane Naci
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aarch64-simd.md (aarch64_dup_lane<mode>): Add r<-w alternative and update. 

	gcc/
	* config/aarch64/aarch64-simd.md (aarch64_dup_lane<mode>): Add r<-w
	alternative and update.
	(aarch64_dup_lanedi): Delete.
	* config/aarch64/arm_neon.h (vdup<bhsd>_lane_*): Update.
	* config/aarch64/aarch64-simd-builtins.def: Update.

	testsuite/
	* gcc.target/aarch64/scalar_intrinsics.c: Update.

From-SVN: r200152
parent ee03e71d
Showing with 34 additions and 33 deletions
gcc/ChangeLog
2013-06-17 Sofiane Naci <sofiane.naci@arm.com>
* config/aarch64/aarch64-simd.md (aarch64_dup_lane<mode>): Add r<-w
alternative and update.
(aarch64_dup_lanedi): Delete.
* config/aarch64/arm_neon.h (vdup<bhsd>_lane_*): Update.
* config/aarch64/aarch64-simd-builtins.def: Update.
2013-06-17 Richard Biener <rguenther@suse.de>
* lto-streamer.h (enum LTO_tags): Add LTO_tree_scc.
......
gcc/config/aarch64/aarch64-simd-builtins.def
......@@ -64,7 +64,7 @@
BUILTIN_VQ (REINTERP, reinterpretv2df, 0)
BUILTIN_VDQ_I (BINOP, dup_lane, 0)
BUILTIN_SDQ_I (BINOP, dup_lane, 0)
BUILTIN_VDQ_I (BINOP, dup_lane_scalar, 0)
/* Implemented by aarch64_<sur>q<r>shl<mode>. */
BUILTIN_VSDQ_I (BINOP, sqshl, 0)
BUILTIN_VSDQ_I (BINOP, uqshl, 0)
......
gcc/config/aarch64/aarch64-simd.md
......@@ -357,29 +357,18 @@
(set_attr "simd_mode" "<MODE>")]
)
(define_insn "aarch64_dup_lane<mode>"
[(set (match_operand:ALLX 0 "register_operand" "=w")
(define_insn "aarch64_dup_lane_scalar<mode>"
[(set (match_operand:<VEL> 0 "register_operand" "=w, r")
(vec_select:<VEL>
(match_operand:<VCON> 1 "register_operand" "w")
(parallel [(match_operand:SI 2 "immediate_operand" "i")])
(match_operand:VDQ 1 "register_operand" "w, w")
(parallel [(match_operand:SI 2 "immediate_operand" "i, i")])
))]
"TARGET_SIMD"
"dup\\t%<v>0<Vmtype>, %1.<Vetype>[%2]"
[(set_attr "simd_type" "simd_dup")
(set_attr "simd_mode" "<MODE>")]
)
(define_insn "aarch64_dup_lanedi"
[(set (match_operand:DI 0 "register_operand" "=w,r")
(vec_select:DI
(match_operand:V2DI 1 "register_operand" "w,w")
(parallel [(match_operand:SI 2 "immediate_operand" "i,i")])))]
"TARGET_SIMD"
"@
dup\\t%<v>0<Vmtype>, %1.<Vetype>[%2]
umov\t%0, %1.d[%2]"
[(set_attr "simd_type" "simd_dup")
(set_attr "simd_mode" "DI")]
dup\\t%<Vetype>0, %1.<Vetype>[%2]
umov\\t%<vw>0, %1.<Vetype>[%2]"
[(set_attr "simd_type" "simd_dup, simd_movgp")
(set_attr "simd_mode" "<MODE>")]
)
(define_insn "aarch64_simd_dup<mode>"
......
gcc/config/aarch64/arm_neon.h
......@@ -20234,49 +20234,49 @@ vcvtpq_u64_f64 (float64x2_t __a)
__extension__ static __inline int8x1_t __attribute__ ((__always_inline__))
vdupb_lane_s8 (int8x16_t a, int const b)
{
return __builtin_aarch64_dup_laneqi (a, b);
return __builtin_aarch64_dup_lane_scalarv16qi (a, b);
}
__extension__ static __inline uint8x1_t __attribute__ ((__always_inline__))
vdupb_lane_u8 (uint8x16_t a, int const b)
{
return (uint8x1_t) __builtin_aarch64_dup_laneqi ((int8x16_t) a, b);
return (uint8x1_t) __builtin_aarch64_dup_lane_scalarv16qi ((int8x16_t) a, b);
}
__extension__ static __inline int16x1_t __attribute__ ((__always_inline__))
vduph_lane_s16 (int16x8_t a, int const b)
{
return __builtin_aarch64_dup_lanehi (a, b);
return __builtin_aarch64_dup_lane_scalarv8hi (a, b);
}
__extension__ static __inline uint16x1_t __attribute__ ((__always_inline__))
vduph_lane_u16 (uint16x8_t a, int const b)
{
return (uint16x1_t) __builtin_aarch64_dup_lanehi ((int16x8_t) a, b);
return (uint16x1_t) __builtin_aarch64_dup_lane_scalarv8hi ((int16x8_t) a, b);
}
__extension__ static __inline int32x1_t __attribute__ ((__always_inline__))
vdups_lane_s32 (int32x4_t a, int const b)
{
return __builtin_aarch64_dup_lanesi (a, b);
return __builtin_aarch64_dup_lane_scalarv4si (a, b);
}
__extension__ static __inline uint32x1_t __attribute__ ((__always_inline__))
vdups_lane_u32 (uint32x4_t a, int const b)
{
return (uint32x1_t) __builtin_aarch64_dup_lanesi ((int32x4_t) a, b);
return (uint32x1_t) __builtin_aarch64_dup_lane_scalarv4si ((int32x4_t) a, b);
}
__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
vdupd_lane_s64 (int64x2_t a, int const b)
{
return __builtin_aarch64_dup_lanedi (a, b);
return __builtin_aarch64_dup_lane_scalarv2di (a, b);
}
__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
vdupd_lane_u64 (uint64x2_t a, int const b)
{
return (uint64x1_t) __builtin_aarch64_dup_lanedi ((int64x2_t) a, b);
return (uint64x1_t) __builtin_aarch64_dup_lane_scalarv2di ((int64x2_t) a, b);
}
/* vldn */
......
gcc/testsuite/ChangeLog
2013-06-17 Sofiane Naci <sofiane.naci@arm.com>
* gcc.target/aarch64/scalar_intrinsics.c: Update.
2013-06-17 Paolo Carlini <paolo.carlini@oracle.com>
PR c++/16128
......
gcc/testsuite/gcc.target/aarch64/scalar_intrinsics.c
/* { dg-do compile } */
/* { dg-options "-O2" } */
/* { dg-options "-O2 -dp" } */
#include <arm_neon.h>
......@@ -181,7 +181,7 @@ test_vcltzd_s64 (int64x1_t a)
return res;
}
/* { dg-final { scan-assembler-times "\\tdup\\tb\[0-9\]+, v\[0-9\]+\.b" 2 } } */
/* { dg-final { scan-assembler-times "aarch64_dup_lane_scalarv16qi" 2 } } */
int8x1_t
test_vdupb_lane_s8 (int8x16_t a)
......@@ -195,7 +195,7 @@ test_vdupb_lane_u8 (uint8x16_t a)
return vdupb_lane_u8 (a, 2);
}
/* { dg-final { scan-assembler-times "\\tdup\\th\[0-9\]+, v\[0-9\]+\.h" 2 } } */
/* { dg-final { scan-assembler-times "aarch64_dup_lane_scalarv8hi" 2 } } */
int16x1_t
test_vduph_lane_s16 (int16x8_t a)
......@@ -209,7 +209,7 @@ test_vduph_lane_u16 (uint16x8_t a)
return vduph_lane_u16 (a, 2);
}
/* { dg-final { scan-assembler-times "\\tdup\\ts\[0-9\]+, v\[0-9\]+\.s" 2 } } */
/* { dg-final { scan-assembler-times "aarch64_dup_lane_scalarv4si" 2 } } */
int32x1_t
test_vdups_lane_s32 (int32x4_t a)
......@@ -223,7 +223,7 @@ test_vdups_lane_u32 (uint32x4_t a)
return vdups_lane_u32 (a, 2);
}
/* { dg-final { scan-assembler-times "\\tumov\\tx\[0-9\]+, v\[0-9\]+\.d" 2 } } */
/* { dg-final { scan-assembler-times "aarch64_dup_lane_scalarv2di" 2 } } */
int64x1_t
test_vdupd_lane_s64 (int64x2_t a)
......
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