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riscv-gcc-1
Commit 3cdf0c62 by Uros Bizjak
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i386.md (unnamed peephole2): Do not force memory operands of arith or logical… 

i386.md (unnamed peephole2): Do not force memory operands of arith or logical instructions into registers...

	* config/i386/i386.md (unnamed peephole2): Do not force memory
	operands of arith or logical instructions into registers for
	non-TARGET_READ_MODIFY targets.

	(ffs_cmove): Change operand 0 predicate to register_operand.
	Change operand 1 predicate to nonimmediate_operand.
	(ffsdi2): Ditto.
	(*ffs_no_cmove): Change operand 0 predicate to register_operand.

From-SVN: r141213
parent 73a5f199
Showing with 34 additions and 23 deletions
MAINTAINERS
......@@ -220,8 +220,8 @@ auto-vectorizer Dorit Nuzman dorit@il.ibm.com
loop infrastructure Zdenek Dvorak ook@ucw.cz
OpenMP Jakub Jelinek jakub@redhat.com
Note that individuals who maintain parts of the compiler need approval to check
in changes outside of the parts of the compiler they maintain.
Note that individuals who maintain parts of the compiler need approval to
check in changes outside of the parts of the compiler they maintain.
Non-Algorithmic Maintainers
......
gcc/ChangeLog
2008-10-18 Uros Bizjak <ubizjak@gmail.com>
* config/i386/i386.md (unnamed peephole2): Do not force memory
operands of arith or logical instructions into registers for
non-TARGET_READ_MODIFY targets.
(ffs_cmove): Change operand 0 predicate to register_operand.
Change operand 1 predicate to nonimmediate_operand.
(ffsdi2): Ditto.
(*ffs_no_cmove): Change operand 0 predicate to register_operand.
2008-10-18 Richard Guenther <rguenther@suse.de>
* tree-ssa-forwprop.c (forward_propagate_addr_expr_1): Guard
......@@ -69,8 +80,7 @@
mark_hard_reg_early_clobbers): New functions.
(process_bb_node_lives): Call
make_early_clobber_and_input_conflicts and
mark_hard_reg_early_clobbers. Make hard register inputs live
again.
mark_hard_reg_early_clobbers. Make hard register inputs live again.
* doc/rtl.texi (clobber): Change descriotion of RA behaviour for
early clobbers of pseudo-registers.
......@@ -332,13 +342,14 @@
* config/ia64/ia64.opt (msched_fp_mem_deps_zero_cost): New option.
(msched-stop-bits-after-every-cycle): Likewise.
(msched-max-memory-insns,
msched-max-memory-insns-hard-limit): Likewise.
(msched-max-memory-insns, msched-max-memory-insns-hard-limit):
Likewise.
(msched-spec-verbose): Remove.
(msched-prefer-non-data-spec-insns,
msched-prefer-non-control-spec-insns, msched-count-spec-in-critical-path,
msel-sched-dont-check-control-spec): Use Target
Report Var instead of Common Report Var.
msched-prefer-non-control-spec-insns,
msched-count-spec-in-critical-path,
msel-sched-dont-check-control-spec): Use Target Report Var
instead of Common Report Var.
* config/ia64/itanium2.md: Remove incorrect bypass.
......@@ -373,7 +384,8 @@
(-mwarn-cell-microcode): Document.
* cfglayout.c (locator_location): Export.
* rtl.h (locator_location): Define prototype.
* config/rs6000/predicates.md (cc_reg_not_micro_cr0_operand): New predicate.
* config/rs6000/predicates.md (cc_reg_not_micro_cr0_operand):
New predicate.
* rs6000/rs6000-protos.h (rs6000_final_prescan_insn): Define prototype.
* config/rs6000/rs6000.opt (mgen-cell-microcode): New option.
(mwarn-cell-microcode): New option.
......@@ -386,9 +398,10 @@
* config/rs6000/rs6000.h (FINAL_PRESCAN_INSN): Define.
* config/rs6000/rs6000.md
Replace cc_reg_not_cr0_operand with cc_reg_not_micro_cr0_operand if
the instruction would have been microcoded on the Cell.
Set cell_micro to always on unnamed patterns for the string instructions.
(cell_micro): Update definition, remove load/store conditional microcoded.
the instruction would have been microcoded on the Cell. Set cell_micro
to always on unnamed patterns for the string instructions.
(cell_micro): Update definition, remove load/store conditional
microcoded.
(sign_extend:DI): Define new pattern for non microcoded version.
(sign_extend:SI): Likewise.
(compare (div:P)): Set cell_micro to not.
......@@ -522,8 +535,7 @@
DF_REF_CLASS, DF_REF_TYPE, DF_REF_CHAIN, DF_REF_ID, DF_REF_FLAGS,
DF_REF_ORDER, DF_REF_IS_ARTIFICIAL, DF_REF_NEXT_REG,
DF_REF_PREV_REG, DF_REF_EXTRACT_WIDTH, DF_REF_EXTRACT_OFFSET,
DF_REF_EXTRACT_MODE): Replaced definition to access union
df_ref_d.
DF_REF_EXTRACT_MODE): Replaced definition to access union df_ref_d.
(DF_MWS_REG_DEF_P, DF_MWS_REG_USE_P, DF_MWS_TYPE): New macros.
(df_scan_bb_info, df_bb_regno_first_def_find,
df_bb_regno_last_def_find, df_find_def, df_find_use,
......@@ -548,8 +560,7 @@
df_ref * with df_ref.
(df_ref_record, df_uses_record, df_ref_create_structure): Added
df_ref_class parameter.
(df_scan_problem_data): Added new pools for different types of
refs.
(df_scan_problem_data): Added new pools for different types of refs.
(df_scan_free_internal, df_scan_alloc, df_free_ref,
df_ref_create_structure): Processed new ref pools.
(df_scan_start_dump): Added counts of refs and insns.
......
gcc/config/i386/i386.md
......@@ -15366,9 +15366,9 @@
(define_expand "ffs_cmove"
[(set (match_dup 2) (const_int -1))
(parallel [(set (reg:CCZ FLAGS_REG)
(compare:CCZ (match_operand:SI 1 "register_operand" "")
(compare:CCZ (match_operand:SI 1 "nonimmediate_operand" "")
(const_int 0)))
(set (match_operand:SI 0 "nonimmediate_operand" "")
(set (match_operand:SI 0 "register_operand" "")
(ctz:SI (match_dup 1)))])
(set (match_dup 0) (if_then_else:SI
(eq (reg:CCZ FLAGS_REG) (const_int 0))
......@@ -15380,7 +15380,7 @@
"operands[2] = gen_reg_rtx (SImode);")
(define_insn_and_split "*ffs_no_cmove"
[(set (match_operand:SI 0 "nonimmediate_operand" "=r")
[(set (match_operand:SI 0 "register_operand" "=r")
(ffs:SI (match_operand:SI 1 "nonimmediate_operand" "rm")))
(clobber (match_scratch:SI 2 "=&q"))
(clobber (reg:CC FLAGS_REG))]
......@@ -15416,9 +15416,9 @@
(define_expand "ffsdi2"
[(set (match_dup 2) (const_int -1))
(parallel [(set (reg:CCZ FLAGS_REG)
(compare:CCZ (match_operand:DI 1 "register_operand" "")
(compare:CCZ (match_operand:DI 1 "nonimmediate_operand" "")
(const_int 0)))
(set (match_operand:DI 0 "nonimmediate_operand" "")
(set (match_operand:DI 0 "register_operand" "")
(ctz:DI (match_dup 1)))])
(set (match_dup 0) (if_then_else:DI
(eq (reg:CCZ FLAGS_REG) (const_int 0))
......@@ -20684,7 +20684,7 @@
[(match_dup 0)
(match_operand:SI 1 "memory_operand" "")]))
(clobber (reg:CC FLAGS_REG))])]
"optimize_insn_for_speed_p ()"
"optimize_insn_for_speed_p () && ! TARGET_READ_MODIFY"
[(set (match_dup 2) (match_dup 1))
(parallel [(set (match_dup 0)
(match_op_dup 3 [(match_dup 0) (match_dup 2)]))
......
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