re PR target/65871 (bzhi builtin/intrinsic wrongly assumes bzhi instruction…

re PR target/65871 (bzhi builtin/intrinsic wrongly assumes bzhi instruction doesn't set the ZF flag)

	PR target/65871
	* config/i386/i386.md (*bmi_bextr_<mode>_cczonly): New pattern.
	(*bmi2_bzhi_<mode>3_1_cczonly): Ditto.

testsuite/ChangeLog:

	PR target/65871
	* gcc.target/i386/pr65871-1.c: New test
	* gcc.target/i386/pr65871-2.c: Ditto.

From-SVN: r222588

gcc/ChangeLog

+2015-04-29  Uros Bizjak  <ubizjak@gmail.com>
+
+	PR target/65871
+	* config/i386/i386.md (*bmi_bextr_<mode>_cczonly): New pattern.
+	(*bmi2_bzhi_<mode>3_1_cczonly): Ditto.
+
 2015-04-29  Thomas Schwinge  <thomas@codesourcery.com>
 
 	PR libgomp/65099

gcc/config/i386/i386.md

@@ -12594,6 +12594,20 @@
    (set_attr "btver2_decode" "direct, double")
    (set_attr "mode" "<MODE>")])
 
+(define_insn "*bmi_bextr_<mode>_cczonly"
+  [(set (reg:CCZ FLAGS_REG)
+	(compare:CCZ
+	  (unspec:SWI48 [(match_operand:SWI48 1 "nonimmediate_operand" "r,m")
+			 (match_operand:SWI48 2 "register_operand" "r,r")]
+			UNSPEC_BEXTR)
+	  (const_int 0)))
+   (clobber (match_scratch:SWI48 0 "=r,r"))]
+  "TARGET_BMI"
+  "bextr\t{%2, %1, %0|%0, %1, %2}"
+  [(set_attr "type" "bitmanip")
+   (set_attr "btver2_decode" "direct, double")
+   (set_attr "mode" "<MODE>")])
+
 (define_insn "*bmi_blsi_<mode>"
   [(set (match_operand:SWI48 0 "register_operand" "=r")
         (and:SWI48
@@ -12667,6 +12681,7 @@
    (set_attr "mode" "<MODE>")])
 
 (define_mode_attr k [(SI "k") (DI "q")])
+
 (define_insn "*bmi2_bzhi_<mode>3_1"
   [(set (match_operand:SWI48 0 "register_operand" "=r")
 	(zero_extract:SWI48
@@ -12682,6 +12697,23 @@
    (set_attr "prefix" "vex")
    (set_attr "mode" "<MODE>")])
 
+(define_insn "*bmi2_bzhi_<mode>3_1_cczonly"
+  [(set (reg:CCZ FLAGS_REG)
+	(compare:CCZ
+	  (zero_extract:SWI48
+	    (match_operand:SWI48 1 "nonimmediate_operand" "rm")
+	    (umin:SWI48
+	      (zero_extend:SWI48 (match_operand:QI 2 "register_operand" "r"))
+	      (match_operand:SWI48 3 "const_int_operand" "n"))
+	    (const_int 0))
+	(const_int 0)))
+   (clobber (match_scratch:SWI48 0 "=r"))]
+  "TARGET_BMI2 && INTVAL (operands[3]) == <MODE_SIZE> * BITS_PER_UNIT"
+  "bzhi\t{%<k>2, %1, %0|%0, %1, %<k>2}"
+  [(set_attr "type" "bitmanip")
+   (set_attr "prefix" "vex")
+   (set_attr "mode" "<MODE>")])
+
 (define_insn "bmi2_pdep_<mode>3"
   [(set (match_operand:SWI48 0 "register_operand" "=r")
         (unspec:SWI48 [(match_operand:SWI48 1 "register_operand" "r")

gcc/testsuite/ChangeLog

+2015-04-29  Uros Bizjak  <ubizjak@gmail.com>
+
+	PR target/65871
+	* gcc.target/i386/pr65871-1.c: New test
+	* gcc.target/i386/pr65871-2.c: Ditto.
+
 2015-04-29  Marek Polacek  <polacek@redhat.com>
 
 	PR c/64610

gcc/testsuite/gcc.target/i386/pr65871-1.c

+/* { dg-do compile } */
+/* { dg-options "-O2 -mbmi" } */
+
+int foo (unsigned int x, unsigned int y)
+{
+  if (__builtin_ia32_bextr_u32 (x, y))
+    return 1;
+
+  return 0;
+}
+
+/* { dg-final { scan-assembler-not "test" } } */

gcc/testsuite/gcc.target/i386/pr65871-2.c

+/* { dg-do compile } */
+/* { dg-options "-O2 -mbmi2" } */
+
+int foo (unsigned int x, unsigned int y)
+{
+  if (__builtin_ia32_bzhi_si (x, y))
+    return 1;
+
+  return 0;
+}
+
+/* { dg-final { scan-assembler-not "test" } } */