fold-vec-extract-char.p7.c: New.

[testsuite]
	* gcc.target/powerpc/fold-vec-extract-char.p7.c: New.
	* gcc.target/powerpc/fold-vec-extract-char.p8.c: New.
	* gcc.target/powerpc/fold-vec-extract-char.p9.c: New.
	* gcc.target/powerpc/fold-vec-extract-double.p7.c: New.
	* gcc.target/powerpc/fold-vec-extract-double.p8.c: New.
	* gcc.target/powerpc/fold-vec-extract-double.p9.c: New.
	* gcc.target/powerpc/fold-vec-extract-float.p7.c: New.
	* gcc.target/powerpc/fold-vec-extract-float.p8.c: New.
	* gcc.target/powerpc/fold-vec-extract-float.p9.c: New.
	* gcc.target/powerpc/fold-vec-extract-int.p7.c: New.
	* gcc.target/powerpc/fold-vec-extract-int.p8.c: New.
	* gcc.target/powerpc/fold-vec-extract-int.p9.c: New.
	* gcc.target/powerpc/fold-vec-extract-longlong.p7.c: New.
	* gcc.target/powerpc/fold-vec-extract-longlong.p8.c: New.
	* gcc.target/powerpc/fold-vec-extract-longlong.p9.c: New.
	* gcc.target/powerpc/fold-vec-extract-short.p7.c: New.
	* gcc.target/powerpc/fold-vec-extract-short.p8.c: New.
	* gcc.target/powerpc/fold-vec-extract-short.p9.c: New.

From-SVN: r265066

gcc/testsuite/ChangeLog

 2018-10-11  Will Schmidt  <will_schmidt@vnet.ibm.com>
 
+	* gcc.target/powerpc/fold-vec-extract-char.p7.c: New.
+	* gcc.target/powerpc/fold-vec-extract-char.p8.c: New.
+	* gcc.target/powerpc/fold-vec-extract-char.p9.c: New.
+	* gcc.target/powerpc/fold-vec-extract-double.p7.c: New.
+	* gcc.target/powerpc/fold-vec-extract-double.p8.c: New.
+	* gcc.target/powerpc/fold-vec-extract-double.p9.c: New.
+	* gcc.target/powerpc/fold-vec-extract-float.p7.c: New.
+	* gcc.target/powerpc/fold-vec-extract-float.p8.c: New.
+	* gcc.target/powerpc/fold-vec-extract-float.p9.c: New.
+	* gcc.target/powerpc/fold-vec-extract-int.p7.c: New.
+	* gcc.target/powerpc/fold-vec-extract-int.p8.c: New.
+	* gcc.target/powerpc/fold-vec-extract-int.p9.c: New.
+	* gcc.target/powerpc/fold-vec-extract-longlong.p7.c: New.
+	* gcc.target/powerpc/fold-vec-extract-longlong.p8.c: New.
+	* gcc.target/powerpc/fold-vec-extract-longlong.p9.c: New.
+	* gcc.target/powerpc/fold-vec-extract-short.p7.c: New.
+	* gcc.target/powerpc/fold-vec-extract-short.p8.c: New.
+	* gcc.target/powerpc/fold-vec-extract-short.p9.c: New.
+
+2018-10-11  Will Schmidt  <will_schmidt@vnet.ibm.com>
+
 	* gcc.target/powerpc/fold-vec-select-char.c: New.
 	* gcc.target/powerpc/fold-vec-select-double.c: New.
 	* gcc.target/powerpc/fold-vec-select-float.c: New.

gcc/testsuite/gcc.target/powerpc/fold-vec-extract-char.p7.c

+/* Verify that overloaded built-ins for vec_extract() with char
+   inputs produce the right code with a power7 (BE) target.  */
+
+/* { dg-do compile { target { powerpc*-*-linux* } } } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power7" } } */
+/* { dg-options "-mcpu=power7 -O2" } */
+
+// Six tests total. Targeting P7 (BE).
+// P7 variable offset:  addi, li,       stxvw4x, rldicl, add, lbz, (extsb)
+// P7 const offset:           li, addi, stxvw4x,              lbz, (extsb)
+/* one extsb (extend sign-bit) instruction generated for each test against
+   unsigned types */
+
+/* { dg-final { scan-assembler-times {\maddi\M} 6 } } */
+/* { dg-final { scan-assembler-times {\mli\M} 6 } } */
+/* { dg-final { scan-assembler-times {\mstxvw4x\M|\mstvx\M|\mstxv\M} 6 } } */
+/* -m32 target uses rlwinm in place of rldicl. */
+/* { dg-final { scan-assembler-times {\mrldicl\M|\mrlwinm\M} 3 } } */
+/* { dg-final { scan-assembler-times {\madd\M} 3 } } */
+/* { dg-final { scan-assembler-times {\mlbz\M} 6 } } */
+/* { dg-final { scan-assembler-times {\mextsb\M} 2 } } */
+
+#include <altivec.h>
+
+unsigned char
+testbc_var (vector bool char vbc2, signed int si)
+{
+  return vec_extract (vbc2, si);
+}
+
+signed char
+testsc_var (vector signed char vsc2, signed int si)
+{
+  return vec_extract (vsc2, si);
+}
+
+unsigned char
+testuc_var (vector unsigned char vuc2, signed int si)
+{
+  return vec_extract (vuc2, si);
+}
+
+unsigned char
+testbc_cst (vector bool char vbc2)
+{
+  return vec_extract (vbc2, 12);
+}
+
+signed char
+testsc_cst (vector signed char vsc2)
+{
+  return vec_extract (vsc2, 12);
+}
+
+unsigned char
+testuc_cst (vector unsigned char vuc2)
+{
+  return vec_extract (vuc2, 12);
+}
+

gcc/testsuite/gcc.target/powerpc/fold-vec-extract-char.p8.c

+/* Verify that overloaded built-ins for vec_extract() with char
+   inputs produce the right code with a P8 (LE or BE) target.  */
+
+/* { dg-do compile { target { powerpc*-*-linux* } } } */
+/* { dg-require-effective-target powerpc_p8vector_ok } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */
+/* { dg-options "-mcpu=power8 -O2" } */
+
+// six tests total. Targeting P8LE / P8BE.
+// P8 LE variable offset: rldicl, subfic, sldi, mtvsrd, xxpermdi, vslo, mfvsrd, sradi, (extsb)
+// P8 LE constant offset: vspltb, mfvsrd, rlwinm, (extsb)
+// P8 BE variable offset:                 sldi, mtvsrd, xxpermdi, vslo, mfvsrd, sradi, (extsb)
+// P8 BE constant offset: vspltb, mfvsrd, rlwinm, (extsb)
+
+/* { dg-final { scan-assembler-times {\mrldicl\M} 3 { target { le } } } } */
+/* { dg-final { scan-assembler-times {\msubfic\M} 3 { target { le } } } } */
+/* { dg-final { scan-assembler-times {\msldi\M} 3 { target lp64 } } } */
+/* { dg-final { scan-assembler-times {\mmtvsrd\M} 3 { target lp64 } } } */
+/* { dg-final { scan-assembler-times {\mxxpermdi\M} 3 { target lp64 } } } */
+/* { dg-final { scan-assembler-times {\mvslo\M} 3 { target lp64 } } } */
+/* { dg-final { scan-assembler-times {\mmfvsrd\M} 6 { target lp64 } } } */
+/* { dg-final { scan-assembler-times {\msradi\M} 3 { target lp64 } } } */
+/* { dg-final { scan-assembler-times "extsb" 2 } } */
+/* { dg-final { scan-assembler-times {\mvspltb\M} 3 { target lp64 } } } */
+/* { dg-final { scan-assembler-times {\mrlwinm\M} 2 { target lp64} } } */
+
+/* multiple codegen variations for -m32. */
+/* { dg-final { scan-assembler-times {\mrlwinm\M} 3 { target ilp32} } } */
+/* { dg-final { scan-assembler-times {\mstxvw4x\M} 6 { target ilp32} } } */
+/* { dg-final { scan-assembler-times {\mlbz\M} 6 { target ilp32} } } */
+
+
+#include <altivec.h>
+
+unsigned char
+testbc_var (vector bool char vbc2,signed int si)
+{
+  return vec_extract (vbc2, si);
+}
+
+signed char
+testsc_var (vector signed char vsc2, signed int si)
+{
+  return vec_extract (vsc2, si);
+}
+
+unsigned char
+testuc_var (vector unsigned char vuc2, signed int si)
+{
+  return vec_extract (vuc2, si);
+}
+
+unsigned char
+testbc_cst (vector bool char vbc2)
+{
+  return vec_extract (vbc2, 12);
+}
+
+signed char
+testsc_cst (vector signed char vsc2)
+{
+  return vec_extract (vsc2, 12);
+}
+
+unsigned char
+testuc_cst (vector unsigned char vuc2)
+{
+  return vec_extract (vuc2, 12);
+}
+

gcc/testsuite/gcc.target/powerpc/fold-vec-extract-char.p9.c

+/* Verify that overloaded built-ins for vec_extract() with char
+   inputs produce the right code with a P9 (LE) target.  */
+
+/* { dg-do compile { target { powerpc*-*-linux* } } } */
+/* { dg-require-effective-target powerpc_p9vector_ok } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
+/* { dg-options "-mcpu=power9 -O2 " } */
+
+/* { dg-final { scan-assembler-times {\mli\M} 3 { target lp64 } } } */
+/*  Endian sensitive, vextubrx or vextublx.  */
+/* { dg-final { scan-assembler-times "vextubrx|vextublx" 6 { target lp64 } } } */
+/* { dg-final { scan-assembler-times "extsb" 2 } } */
+
+/* { dg-final { scan-assembler-times "stxv" 6 { target ilp32 } } } */
+/* { dg-final { scan-assembler-times "lbz" 6 { target ilp32 } } } */
+/* { dg-final { scan-assembler-times "addi" 6 { target ilp32 } } } */
+
+
+#include <altivec.h>
+
+unsigned char
+testbc_var (vector bool char vbc2,signed int si)
+{
+  return vec_extract (vbc2, si);
+}
+
+signed char
+testsc_var (vector signed char vsc2, signed int si)
+{
+  return vec_extract (vsc2, si);
+}
+
+unsigned char
+testuc_var (vector unsigned char vuc2, signed int si)
+{
+  return vec_extract (vuc2, si);
+}
+
+unsigned char
+testbc_cst (vector bool char vbc2)
+{
+  return vec_extract (vbc2, 12);
+}
+
+signed char
+testsc_cst (vector signed char vsc2)
+{
+  return vec_extract (vsc2, 12);
+}
+
+unsigned char
+testuc_cst (vector unsigned char vuc2)
+{
+  return vec_extract (vuc2, 12);
+}
+

gcc/testsuite/gcc.target/powerpc/fold-vec-extract-double.p7.c

+/* Verify that overloaded built-ins for vec_extract() with
+   double inputs produce the right code.  */
+
+/* { dg-do compile { target { powerpc*-*-linux* } } } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power7" } } */
+/* { dg-options "-mcpu=power7 -O2 -mbig-endian" } */
+
+// targeting P7 (BE), 2 tests.
+// P7 constants: xxpermdi
+// P7 variables: li, addi, rldic, addi, stxvd2x, lfdx
+
+/* { dg-final { scan-assembler-times {\mxxpermdi\M} 1 } } */
+/* { dg-final { scan-assembler-times {\mli\M} 1 } } */
+/* -m32 target has an 'add' in place of one of the 'addi'. */
+/* { dg-final { scan-assembler-times {\maddi\M|\madd\M} 2 } } */
+/* -m32 target has a rlwinm in place of a rldic .  */
+/* { dg-final { scan-assembler-times {\mrldic\M|\mrlwinm\M} 1 } } */
+/* { dg-final { scan-assembler-times {\mstxvd2x\M} 1 } } */
+/* { dg-final { scan-assembler-times {\mlfdx\M|\mlfd\M} 1 } } */
+
+#include <altivec.h>
+
+double
+testd_var (vector double vd2, signed int si)
+{
+  return vec_extract (vd2, si);
+}
+
+double
+testd_cst (vector double vd2)
+{
+  return vec_extract (vd2, 1);
+}
+

gcc/testsuite/gcc.target/powerpc/fold-vec-extract-double.p8.c

+/* Verify that overloaded built-ins for vec_extract() with
+   double inputs produce the right code with a P8 (LE or BE) target.  */
+
+/* { dg-do compile { target { powerpc*-*-linux* } } } */
+/* { dg-require-effective-target powerpc_p8vector_ok } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */
+/* { dg-options "-mcpu=power8 -O2" } */
+
+// targeting P8, BE and LE. 2 tests.
+// P8 (LE) constants: xxlor
+// P8 (LE) variables: xori, rldic, mtvsrd, xxpermdi, vslo, xxlor
+// P8 (BE) constants: xxpermdi
+// P8 (BE) variables:       rldic, mtvsrd, xxpermdi, vslo, xxlor
+
+/* { dg-final { scan-assembler-times {\mxxlor\M} 2 { target { le && lp64 } } } } */
+/* { dg-final { scan-assembler-times {\mxxlor\M} 1 { target { be && lp64 } } } } */
+/* { dg-final { scan-assembler-times {\mxori\M} 1 { target { le } } } } */
+/* { dg-final { scan-assembler-times {\mrldic\M|\mrlwinm\M} 1 } } */
+/* { dg-final { scan-assembler-times {\mmtvsrd\M} 1 { target lp64 } } } */
+/* { dg-final { scan-assembler-times {\mxxpermdi\M} 1 { target { le } } } } */
+/* { dg-final { scan-assembler-times {\mxxpermdi\M} 2 { target { lp64 && be } } } } */
+/* { dg-final { scan-assembler-times {\mvslo\M} 1 { target lp64 } } } */
+
+/* { dg-final { scan-assembler-times {\mstxvd2x\M} 1 { target ilp32 } } } */
+/* { dg-final { scan-assembler-times {\mxxpermdi\M} 1 { target ilp32 } } } */
+
+#include <altivec.h>
+
+double
+testd_var (vector double vd2, signed int si)
+{
+  return vec_extract (vd2, si);
+}
+
+double
+testd_cst (vector double vd2)
+{
+  return vec_extract (vd2, 1);
+}
+

gcc/testsuite/gcc.target/powerpc/fold-vec-extract-double.p9.c

+/* Verify that overloaded built-ins for vec_extract() with
+   double inputs produce the right code.  */
+
+/* { dg-do compile { target { p9vector_hw } } } */
+/* { dg-require-effective-target p9vector_hw } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
+/* { dg-options "-mcpu=power9 -O2 " } */
+
+/* { dg-final { scan-assembler-times {\mxxlor\M} 2 } } */
+/* { dg-final { scan-assembler-times {\mrldic\M} 1 } } */
+/* { dg-final { scan-assembler-times {\mmtvsrdd\M} 1 } } */
+/* { dg-final { scan-assembler-times {\mvslo\M} 1 } } */
+
+#include <altivec.h>
+
+double
+testd_var (vector double vd2, signed int si)
+{
+  return vec_extract (vd2, si);
+}
+
+double
+testd_cst (vector double vd2)
+{
+  return vec_extract (vd2, 1);
+}
+

gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p7.c

+/* Verify that overloaded built-ins for vec_extract() with float
+   inputs produce the right code with a P7 (BE) target.  */
+
+/* { dg-do compile { target { powerpc*-*-linux* } } } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power7" } } */
+/* { dg-options "-mcpu=power7 -O2 " } */
+
+// targeting P7 (BE), 2 tests.
+// P7 constants: xscvspdp
+// P7 variables: li, addi, stxvd2x, rldic, addi, lfsx
+
+/* { dg-final { scan-assembler-times {\mxscvspdp\M} 1 } } */
+/* { dg-final { scan-assembler-times {\mli\M} 1 } } */
+/* -m32 as an add in place of an addi. */
+/* { dg-final { scan-assembler-times {\maddi\M|\madd\M} 2 } } */
+/* { dg-final { scan-assembler-times {\mstxvd2x\M|\mstvx\M|\mstxv\M} 1 } } */
+/* -m32 uses rlwinm in place of rldic */
+/* { dg-final { scan-assembler-times {\mrldic\M|\mrlwinm\M} 1 } } */
+/* -m32 has lfs in place of lfsx */
+/* { dg-final { scan-assembler-times {\mlfsx\M|\mlfs\M} 1 } } */
+
+#include <altivec.h>
+
+float
+testf_var (vector float vf2, signed int si)
+{
+  return vec_extract (vf2, si);
+}
+
+float
+testf_cst (vector float vf2)
+{
+  return vec_extract (vf2, 12);
+}
+

gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p8.c

+/* Verify that overloaded built-ins for vec_extract() with float
+   inputs produce the right code with a P8 (LE or BE) target.  */
+
+/* { dg-do compile { target { powerpc*-*-linux* } } } */
+/* { dg-require-effective-target powerpc_p8vector_ok } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */
+/* { dg-options "-mcpu=power8 -O2" } */
+
+// targeting P8, BE and LE. 2 tests.
+// P8 (LE) constants: xxsldwi, xscvspdp
+// P8 (LE) variables: rldicl, subfic, sldi, mtvsrd, xxpermdi, vslo, xscvspdp
+// P8 (BE) constants:          xscvspdp
+// P8 (BE) variables:                 sldi, mtvsrd, xxpermdi, vslo, xscvspdp
+
+/* { dg-final { scan-assembler-times {\mxxsldwi\M} 1 { target { le } } } } */
+/* { dg-final { scan-assembler-times {\mxscvspdp\M} 2 { target lp64 } } } */
+/* { dg-final { scan-assembler-times {\mrldicl\M} 1 { target { le } } } } */
+/* { dg-final { scan-assembler-times {\msubfic\M} 1 { target { le } } } } */
+/* { dg-final { scan-assembler-times {\msldi\M} 1 { target lp64 } } } */
+/* { dg-final { scan-assembler-times {\mmtvsrd\M} 1 { target lp64 } } } */
+/* { dg-final { scan-assembler-times {\mxxpermdi\M} 1 { target lp64 } } } */
+/* { dg-final { scan-assembler-times {\mvslo\M} 1 { target lp64 } } } */
+
+/* { dg-final { scan-assembler-times {\mxscvspdp\M} 1 { target ilp32 } } } */
+/* { dg-final { scan-assembler-times {\mli\M} 1 { target ilp32 } } } */
+/* { dg-final { scan-assembler-times {\mrlwinm\M} 1 { target ilp32 } } } */
+/* { dg-final { scan-assembler-times {\mstxvd2x\M} 1 { target ilp32 } } } */
+/* { dg-final { scan-assembler-times {\madd\M} 1 { target ilp32 } } } */
+/* { dg-final { scan-assembler-times {\mlfs\M} 1 { target ilp32 } } } */
+/* { dg-final { scan-assembler-times {\maddi\M} 1 { target ilp32 } } } */
+
+
+#include <altivec.h>
+
+float
+testf_var (vector float vf2, signed int si)
+{
+  return vec_extract (vf2, si);
+}
+
+float
+testf_cst (vector float vf2)
+{
+  return vec_extract (vf2, 12);
+}
+

gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p9.c

+/* Verify that overloaded built-ins for vec_extract() with float
+   inputs produce the right code.  */
+
+/* { dg-do compile { target { powerpc*-*-linux* && le } } } */
+/* { dg-require-effective-target powerpc_p9vector_ok } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
+/* { dg-options "-mcpu=power9 -O2 " } */
+
+/* { dg-final { scan-assembler-times {\mxscvspdp\M} 2 } } */
+/* { dg-final { scan-assembler-times {\mrldicl\M} 1 } } */
+/* { dg-final { scan-assembler-times {\msubfic\M} 1 } } */
+/* { dg-final { scan-assembler-times {\msldi\M} 1 } } */
+/* { dg-final { scan-assembler-times {\mmtvsrdd\M} 1 } } */
+/* { dg-final { scan-assembler-times {\mvslo\M} 1 } } */
+
+#include <altivec.h>
+
+float
+testf_var (vector float vf2, signed int si)
+{
+  return vec_extract (vf2, si);
+}
+
+float
+testf_cst (vector float vf2)
+{
+  return vec_extract (vf2, 12);
+}
+

gcc/testsuite/gcc.target/powerpc/fold-vec-extract-int.p7.c

+/* Verify that overloaded built-ins for vec_extract() with int
+   inputs produce the right code with a P7 (BE) target.  */
+
+/* { dg-do compile { target { powerpc*-*-linux* } } } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power7" } } */
+/* { dg-options "-mcpu=power7 -O2 " } */
+
+// Targeting P7 (BE).  6 tests total.
+// P7 constant:   li, addi, stxvw4x, rldic, addi, lwzx/lwax
+// P7 variables:  li, addi, stxvw4x, lwa/lwz
+
+/* { dg-final { scan-assembler-times {\mli\M} 6 } } */
+/* { dg-final { scan-assembler-times {\maddi\M|\madd\M} 9 } } */
+/* { dg-final { scan-assembler-times {\mstxvw4x\M|\mstvx\M|\mstxv\M} 6 } } */
+/* { dg-final { scan-assembler-times {\mrldic\M|\mrlwinm\M} 3 } } */
+/* { dg-final { scan-assembler-times {\mlwz\M|\mlwa\M|\mlwzx\M|\mlwax\M} 6 } } */
+
+#include <altivec.h>
+
+unsigned int
+testbi_var (vector bool int vbi2, signed int si)
+{
+  return vec_extract (vbi2, si);
+}
+
+signed int
+testsi_var (vector signed int vsi2, signed int si)
+{
+  return vec_extract (vsi2, si);
+}
+
+unsigned int
+testui_var (vector unsigned int vui2, signed int si)
+{
+  return vec_extract (vui2, si);
+}
+
+unsigned int
+testbi_cst (vector bool int vbi2)
+{
+  return vec_extract (vbi2, 12);
+}
+
+signed int
+testsi_cst (vector signed int vsi2)
+{
+  return vec_extract (vsi2, 12);
+}
+
+unsigned int
+testui_cst (vector unsigned int vui2)
+{
+  return vec_extract (vui2, 12);
+}
+

gcc/testsuite/gcc.target/powerpc/fold-vec-extract-int.p8.c

+/* Verify that overloaded built-ins for vec_extract() with int
+   inputs produce the right code with a P8 (LE or BE) target.  */
+
+/* { dg-do compile { target { powerpc*-*-linux* } } } */
+/* { dg-require-effective-target powerpc_p8vector_ok } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */
+/* { dg-options "-mcpu=power8 -O2" } */
+
+// Targeting P8 (LE) and (BE).  6 tests total.
+// P8 LE constant:  vspltw, mfvsrwz, (1:extsw/2:rldicl)
+// P8 LE variables: rldicl, subfic,  sldi, mtvsrd, xxpermdi, vslo, mfvsrd, sradi, (1:extsw)
+// P8 BE constant:  vspltw, mfvsrwz, (1:extsw/2:rldicl)
+// P8 BE variables:                  sldi, mtvsrd, xxpermdi, vslo, mfvsrd, sradi, (1:extsw)
+
+/* { dg-final { scan-assembler-times {\mvspltw\M} 3 { target lp64 } } } */
+/* { dg-final { scan-assembler-times {\mmfvsrwz\M} 3 { target lp64 } } } */
+/* { dg-final { scan-assembler-times {\mrldicl\M} 5 { target { le } } } } */
+/* { dg-final { scan-assembler-times {\mrldicl\M} 2 { target { lp64 && be } } } } */
+/* { dg-final { scan-assembler-times {\msubfic\M} 3 { target { le } } } } */
+/* { dg-final { scan-assembler-times {\msldi\M} 3  { target lp64 } } } */
+/* { dg-final { scan-assembler-times {\mmtvsrd\M} 3 { target lp64 } } } */
+/* { dg-final { scan-assembler-times {\mxxpermdi\M} 3 { target lp64 } } } */
+/* { dg-final { scan-assembler-times {\mvslo\M} 3 { target lp64 } } } */
+/* { dg-final { scan-assembler-times {\mmfvsrd\M} 3 { target lp64 } } } */
+/* { dg-final { scan-assembler-times {\msradi\M} 3 { target lp64 } } } */
+/* { dg-final { scan-assembler-times {\mextsw\M} 2 { target lp64 } } } */
+
+
+/* { dg-final { scan-assembler-times {\mli\M} 6 { target ilp32 } } } */
+/* { dg-final { scan-assembler-times {\mrlwinm\M} 3 { target ilp32 } } } */
+/* { dg-final { scan-assembler-times {\mstxvw4x\M} 6 { target ilp32 } } } */
+/* { dg-final { scan-assembler-times {\madd\M} 3 { target ilp32 } } } */
+/* { dg-final { scan-assembler-times {\mlwz\M} 6 { target ilp32 } } } */
+/* { dg-final { scan-assembler-times {\maddi\M} 6 { target ilp32 } } } */
+
+
+
+#include <altivec.h>
+
+unsigned int
+testbi_var (vector bool int vbi2, signed int si)
+{
+  return vec_extract (vbi2, si);
+}
+
+signed int
+testsi_var (vector signed int vsi2, signed int si)
+{
+  return vec_extract (vsi2, si);
+}
+
+unsigned int
+testui_var (vector unsigned int vui2, signed int si)
+{
+  return vec_extract (vui2, si);
+}
+
+unsigned int
+testbi_cst (vector bool int vbi2)
+{
+  return vec_extract (vbi2, 12);
+}
+
+signed int
+testsi_cst (vector signed int vsi2)
+{
+  return vec_extract (vsi2, 12);
+}
+
+unsigned int
+testui_cst (vector unsigned int vui2)
+{
+  return vec_extract (vui2, 12);
+}
+

gcc/testsuite/gcc.target/powerpc/fold-vec-extract-int.p9.c

+/* Verify that overloaded built-ins for vec_extract() with int
+   inputs produce the right code with a P9 (LE) target.  */
+
+/* { dg-do compile { target { powerpc*-*-linux* } } } */
+/* { dg-require-effective-target powerpc_p9vector_ok } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
+/* { dg-options "-mcpu=power9 -O2 " } */
+
+// Targeting P9 (LE).  6 tests total.
+// P9 constant:   li, vextuwrx, (1:extsw)
+// P9 variables:  slwi, vextuwrx, (1:extsw)
+
+/* { dg-final { scan-assembler-times {\mli\M} 3 { target lp64 } } } */
+/* { dg-final { scan-assembler-times {\mslwi\M} 3 { target lp64 } } } */
+/* { dg-final { scan-assembler-times {\mvextuwrx\M|\mvextuwlx\M} 6 { target lp64 } } } */
+/* { dg-final { scan-assembler-times {\mextsw\M} 2 { target lp64 } } } */
+
+/* { dg-final { scan-assembler-times {\mrlwinm\M} 3 { target ilp32 } } } */
+/* { dg-final { scan-assembler-times {\madd\M} 3 { target ilp32 } } } */
+/* { dg-final { scan-assembler-times {\mstxv\M} 6 { target ilp32 } } } */
+/* { dg-final { scan-assembler-times {\mlwz\M} 6 { target ilp32 } } } */
+/* { dg-final { scan-assembler-times {\maddi\M} 6 { target ilp32 } } } */
+
+
+#include <altivec.h>
+
+unsigned int
+testbi_var (vector bool int vbi2, signed int si)
+{
+  return vec_extract (vbi2, si);
+}
+
+signed int
+testsi_var (vector signed int vsi2, signed int si)
+{
+  return vec_extract (vsi2, si);
+}
+
+unsigned int
+testui_var (vector unsigned int vui2, signed int si)
+{
+  return vec_extract (vui2, si);
+}
+
+unsigned int
+testbi_cst (vector bool int vbi2)
+{
+  return vec_extract (vbi2, 12);
+}
+
+signed int
+testsi_cst (vector signed int vsi2)
+{
+  return vec_extract (vsi2, 12);
+}
+
+unsigned int
+testui_cst (vector unsigned int vui2)
+{
+  return vec_extract (vui2, 12);
+}
+

gcc/testsuite/gcc.target/powerpc/fold-vec-extract-longlong.p7.c

+/* Verify that overloaded built-ins for vec_extract() with long long
+   inputs produce the right code with a P8 (LE or BE) target.  */
+
+/* { dg-do compile { target { powerpc*-*-linux* } } } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power7" } } */
+/* { dg-options "-mcpu=power7 -O2" } */
+
+// Targeting P7. six tests total.
+// P7 (m64) with constants: xxpermdi, stfd, ld
+// P7 (m64) with variables: li, addi, stxvd2x, rldic, addi, ldx
+
+// P7 (m32) with constants: [xxpermdi or li/lwz,li/lwz],stxvw4x/stfd,lwz,lwz, addi
+// P7 (m32) with variables: li, addi/rlwinm, stxvd2x, rldic, addi/add, ldx/lwz
+
+/* results. */
+/* { dg-final { scan-assembler-times {\mstfd\M} 3 { target lp64 } } } */
+/* -m32 target with constant test has a stxvw4x in place of a stfd. */
+/* { dg-final { scan-assembler-times {\mstfd\M} 2 { target ilp32 } } } */
+/* { dg-final { scan-assembler-times {\mld\M} 3 { target lp64 } } } */
+/* { dg-final { scan-assembler-times {\mlwz\M} 11 { target ilp32 } } } */
+/* { dg-final { scan-assembler-times {\mli\M} 3 { target lp64 } } } */
+/* -m32 target with constant test uses (+2)li where the -m64 has an ld */
+/* { dg-final { scan-assembler-times {\mli\M} 5 { target ilp32 } } } */
+/* { dg-final { scan-assembler-times {\maddi\M} 6 } } */
+/* { dg-final { scan-assembler-times {\mstxvd2x\M|\mstvx\M} 3 } } */
+/* { dg-final { scan-assembler-times {\mrldic\M|\mrlwinm\M} 3 } } */
+/* { dg-final { scan-assembler-times {\mldx\M} 3 { target lp64 } } } */
+
+
+#include <altivec.h>
+
+unsigned long long
+testbl_var (vector bool long long vbl2, signed int si)
+{
+  return vec_extract (vbl2, si);
+}
+
+signed long long
+testsl_var (vector signed long long vsl2, signed int si)
+{
+  return vec_extract (vsl2, si);
+}
+
+unsigned long long
+testul_var (vector unsigned long long vul2, signed int si)
+{
+  return vec_extract (vul2, si);
+}
+
+unsigned long long
+testbl_cst (vector bool long long vbl2)
+{
+  return vec_extract (vbl2, 1);
+}
+
+signed long long
+testsl_cst (vector signed long long vsl2)
+{
+  return vec_extract (vsl2, 1);
+}
+
+unsigned long long
+testul_cst (vector unsigned long vul2)
+{
+  return vec_extract (vul2, 1);
+}
+

gcc/testsuite/gcc.target/powerpc/fold-vec-extract-longlong.p8.c

+/* Verify that overloaded built-ins for vec_extract() with long long
+   inputs produce the right code with a P8 (LE or BE) target.  */
+
+/* { dg-do compile { target { powerpc*-*-linux* } } } */
+/* { dg-require-effective-target powerpc_p8vector_ok } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */
+/* { dg-options "-mcpu=power8 -O2" } */
+
+// targeting P8, both LE and BE. six tests.
+// P8 (LE) constants: mfvsrd
+// P8 (LE) variables: xori, rldic, mtvsrd, xxpermdi, vslo, mfvsrd
+// P8 (BE) constants: xxpermdi, mfvsrd
+// P8 (BE) Variables:       rldic, mtvsrd, xxpermdi, vslo, mfvsrd
+
+/* results. */
+/* { dg-final { scan-assembler-times {\mxori\M} 3 { target le } } } */
+/* { dg-final { scan-assembler-times {\mrldic\M|\mrlwinm\M} 3 } } */
+/* { dg-final { scan-assembler-times {\mstxvd2x\M|\mstxvw4x\M} 4 { target ilp32 } } } */
+/* { dg-final { scan-assembler-times {\madd\M} 3 { target ilp32 } } } */
+/* { dg-final { scan-assembler-times {\mlwz\M} 11 { target ilp32 } } } */
+/* { dg-final { scan-assembler-times {\maddi\M} 6 { target ilp32 } } } */
+/* { dg-final { scan-assembler-times {\mmfvsrd\M} 6 { target lp64 } } } */
+/* { dg-final { scan-assembler-times {\mmtvsrd\M} 3 { target lp64 } } } */
+/* { dg-final { scan-assembler-times {\mxxpermdi\M} 3 { target le } } } */
+/* { dg-final { scan-assembler-times {\mxxpermdi\M} 6 { target { be && lp64 } } } } */
+/* { dg-final { scan-assembler-times {\mxxpermdi\M} 2 { target { be && ilp32 } } } } */
+/* { dg-final { scan-assembler-times {\mvslo\M} 3 { target lp64 } } } */
+
+#include <altivec.h>
+
+unsigned long long
+testbl_var (vector bool long long vbl2, signed int si)
+{
+  return vec_extract (vbl2, si);
+}
+
+signed long long
+testsl_var (vector signed long long vsl2, signed int si)
+{
+  return vec_extract (vsl2, si);
+}
+
+unsigned long long
+testul_var (vector unsigned long long vul2, signed int si)
+{
+  return vec_extract (vul2, si);
+}
+
+unsigned long long
+testbl_cst (vector bool long long vbl2)
+{
+  return vec_extract (vbl2, 1);
+}
+
+signed long long
+testsl_cst (vector signed long long vsl2)
+{
+  return vec_extract (vsl2, 1);
+}
+
+unsigned long long
+testul_cst (vector unsigned long vul2)
+{
+  return vec_extract (vul2, 1);
+}
+

gcc/testsuite/gcc.target/powerpc/fold-vec-extract-longlong.p9.c

+/* Verify that overloaded built-ins for vec_extract() with long long
+   inputs produce the right code for a P9 (LE) target.  */
+
+/* { dg-do compile { target { powerpc*-*-linux* && le } } } */
+/* { dg-require-effective-target powerpc_p9vector_ok } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
+/* { dg-options "-mcpu=power9 -O2" } */
+
+// targeting P9 (LE), six tests.
+// p9 constants: mfvsrd
+// p9 vars:  xori, rldic, mtvsrdd, vslo, mfvsrd
+
+/* results. */
+/* { dg-final { scan-assembler-times {\mxori\M} 3 } } */
+/* { dg-final { scan-assembler-times {\mrldic\M} 3 } } */
+/* { dg-final { scan-assembler-times {\mmtvsrdd\M} 3 } } */
+/* { dg-final { scan-assembler-times {\mvslo\M} 3 } } */
+/* { dg-final { scan-assembler-times {\mmfvsrd\M} 6 } } */
+
+#include <altivec.h>
+
+unsigned long long
+testbl_var (vector bool long long vbl2, signed int si)
+{
+  return vec_extract (vbl2, si);
+}
+
+signed long long
+testsl_var (vector signed long long vsl2, signed int si)
+{
+  return vec_extract (vsl2, si);
+}
+
+unsigned long long
+testul_var (vector unsigned long long vul2, signed int si)
+{
+  return vec_extract (vul2, si);
+}
+
+unsigned long long
+testbl_cst (vector bool long long vbl2)
+{
+  return vec_extract (vbl2, 1);
+}
+
+signed long long
+testsl_cst (vector signed long long vsl2)
+{
+  return vec_extract (vsl2, 1);
+}
+
+unsigned long long
+testul_cst (vector unsigned long vul2)
+{
+  return vec_extract (vul2, 1);
+}
+

gcc/testsuite/gcc.target/powerpc/fold-vec-extract-short.p7.c

+/* Verify that overloaded built-ins for vec_extract() with short
+   inputs produce the right code for a P7 (BE) target.  */
+
+/* { dg-do compile { target { powerpc*-*-linux* } } } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power7" } } */
+/* { dg-options "-mcpu=power7 -O2" } */
+
+// six tests total. Targeting P7 BE.
+// p7 (be) vars:                 li, addi,              stxvw4x, rldic, addi, lhax/lhzx
+// P7 (be) constants:            li, addi,              stxvw4x, lha/lhz
+
+/* { dg-final { scan-assembler-times {\mli\M} 6 } } */
+/* { dg-final { scan-assembler-times {\maddi\M|\madd\M} 9 } } */
+/* { dg-final { scan-assembler-times {\mrldic\M|\mrlwinm\M} 3 } } */
+/* { dg-final { scan-assembler-times {\mstxvw4x\M|\mstvx\M} 6 } } */
+/* { dg-final { scan-assembler-times "lhz|lha|lhzx|lhax" 6 } } */
+
+#include <altivec.h>
+
+unsigned short
+testbi_cst (vector bool short vbs2)
+{
+  return vec_extract (vbs2, 12);
+}
+
+signed short
+testsi_cst (vector signed short vss2)
+{
+  return vec_extract (vss2, 12);
+}
+
+unsigned short
+testui_cst12 (vector unsigned short vus2)
+{
+  return vec_extract (vus2, 12);
+}
+
+unsigned short
+testbi_var (vector bool short vbs2, signed int si)
+{
+  return vec_extract (vbs2, si);
+}
+
+signed short
+testsi_var (vector signed short vss2, signed int si)
+{
+return vec_extract (vss2, si);
+}
+
+unsigned short
+testui_var (vector unsigned short vus2, signed int si)
+{
+return vec_extract (vus2, si);
+}
+

gcc/testsuite/gcc.target/powerpc/fold-vec-extract-short.p8.c

+/* Verify that overloaded built-ins for vec_extract() with short
+   inputs produce the right results with a P8 (LE or BE) target.  */
+
+/* { dg-do compile { target { powerpc*-*-linux* } } } */
+/* { dg-require-effective-target powerpc_p8vector_ok } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */
+/* { dg-options "-mcpu=power8 -O2" } */
+
+// six tests total. Targeting P8, both LE and BE.
+// p8 (le) variable offset: rldicl, subfic, sldi, mtvsrd, xxpermdi, vslo, mfvsrd, sradi, *extsh
+// p8 (le) const offset:                          mtvsrd,                                *extsh/rlwinm
+// p8 (be) var offset:                      sldi, mtvsrd, xxpermdi, vslo, mfvsrd, sradi, *extsh
+// p8 (be) const offset:    vsplth,               mfvsrd,                                *extsh/rlwinm
+
+// * - each of the above will have an extsh if the argument is signed.
+// * - bool and unsigned tests also have an rlwinm.
+
+/* { dg-final { scan-assembler-times "rldicl" 3 {target { lp64 && le } } } } */
+/* { dg-final { scan-assembler-times "subfic" 3 {target { lp64 && le } } } } */
+/* { dg-final { scan-assembler-times "vsplth" 3 { target { lp64 && be } } } } */
+/* { dg-final { scan-assembler-times "sldi" 3 { target lp64 } } } */
+/* { dg-final { scan-assembler-times "mtvsrd" 3 { target lp64 } } } */
+/* { dg-final { scan-assembler-times "xxpermdi" 3 { target lp64 } } } */
+/* { dg-final { scan-assembler-times "vslo" 3 { target lp64 } } } */
+/* { dg-final { scan-assembler-times "mfvsrd" 6 { target lp64 } } } */
+/* { dg-final { scan-assembler-times "sradi" 3 { target lp64 } } } */
+/* { dg-final { scan-assembler-times "extsh" 2 { target lp64 } } } */
+/* { dg-final { scan-assembler-times "rlwinm" 2 { target lp64 } } } */
+
+/* -m32 codegen tests. */
+/* { dg-final { scan-assembler-times {\mli\M} 6 { target ilp32 } } } */
+/* { dg-final { scan-assembler-times "stxvw4x" 6 { target ilp32 } } } */
+/* add and rlwinm instructions only on the variable tests. */
+/* { dg-final { scan-assembler-times {\madd\M} 3 { target ilp32 } } } */
+/* { dg-final { scan-assembler-times "rlwinm" 3 { target ilp32 } } } */
+/* { dg-final { scan-assembler-times {\maddi\M} 6 { target ilp32 } } } */
+/* { dg-final { scan-assembler-times {\mlha\M|\mlhz\M} 6 { target ilp32 } } } */
+
+
+#include <altivec.h>
+
+unsigned short
+testbi_cst (vector bool short vbs2)
+{
+  return vec_extract (vbs2, 12);
+}
+
+signed short
+testsi_cst (vector signed short vss2)
+{
+  return vec_extract (vss2, 12);
+}
+
+unsigned short
+testui_cst12 (vector unsigned short vus2)
+{
+  return vec_extract (vus2, 12);
+}
+
+unsigned short
+testbi_var (vector bool short vbs2, signed int si)
+{
+  return vec_extract (vbs2, si);
+}
+
+signed short
+testsi_var (vector signed short vss2, signed int si)
+{
+return vec_extract (vss2, si);
+}
+
+unsigned short
+testui_var (vector unsigned short vus2, signed int si)
+{
+return vec_extract (vus2, si);
+}
+

gcc/testsuite/gcc.target/powerpc/fold-vec-extract-short.p9.c

+/* Verify that overloaded built-ins for vec_extract() with short
+   inputs produce the right code for a P9 (LE) target.  */
+
+/* { dg-do compile { target { powerpc*-*-linux* && le } } } */
+/* { dg-require-effective-target powerpc_p9vector_ok } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
+/* { dg-options "-mcpu=power9 -O2" } */
+
+// six tests total. Targeting P9 LE.
+// p9 (le) variable offset: slwi, vextuhlx, extsh
+// p9 (le) const offset:  li, vextuhlx, extsh
+
+/* { dg-final { scan-assembler-times {\mslwi\M} 3 } } */
+/* { dg-final { scan-assembler-times {\mli\M} 3 } } */
+/* { dg-final { scan-assembler-times "vextuhrx" 6 } } */
+/* { dg-final { scan-assembler-times {\mextsh\M} 2 } } */
+
+#include <altivec.h>
+
+unsigned short
+testbi_cst (vector bool short vbs2)
+{
+  return vec_extract (vbs2, 12);
+}
+
+signed short
+testsi_cst (vector signed short vss2)
+{
+  return vec_extract (vss2, 12);
+}
+
+unsigned short
+testui_cst12 (vector unsigned short vus2)
+{
+  return vec_extract (vus2, 12);
+}
+
+unsigned short
+testbi_var (vector bool short vbs2, signed int si)
+{
+  return vec_extract (vbs2, si);
+}
+
+signed short
+testsi_var (vector signed short vss2, signed int si)
+{
+return vec_extract (vss2, si);
+}
+
+unsigned short
+testui_var (vector unsigned short vus2, signed int si)
+{
+return vec_extract (vus2, si);
+}
+