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riscv-gcc-1
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lvzhengyang
riscv-gcc-1
Commits
3b7f6cca
Commit
3b7f6cca
authored
Apr 18, 1995
by
Michael Meissner
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Do not generate mem->mem SF moves if -msoft-float
From-SVN: r9408
parent
eb0430f0
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gcc/config/rs6000/rs6000.md
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gcc/config/rs6000/rs6000.md
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3b7f6cca
...
...
@@ -3923,7 +3923,10 @@
&& REGNO (SUBREG_REG (operands
[
1
]
)) < FIRST_PSEUDO_REGISTER)
operands
[
1
]
= alter_subreg (operands
[
1
]
);
if (TARGET_HARD_FLOAT)
if (TARGET_SOFT_FLOAT && GET_CODE (operands
[
0
]
) == MEM)
operands
[
1
]
= force_reg (SFmode, operands
[
1
]
);
else if (TARGET_HARD_FLOAT)
{
if (GET_CODE (operands
[
1
]
) == REG && REGNO (operands
[
1
]
) < 32)
{
...
...
@@ -3956,7 +3959,7 @@
/* If operands[1] is a register, it may have double-precision data
in it, so truncate it to single precision. We need not do
this for POWERPC. */
if (! TARGET_POWERPC &&
TARGET_HARD_FLOAT &&
GET_CODE (operands[1]) == REG)
if (! TARGET_POWERPC && GET_CODE (operands[1]) == REG)
{
rtx newreg = reload_in_progress ? operands[1] : gen_reg_rtx (SFmode);
emit_insn (gen_truncdfsf2 (newreg,
...
...
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