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riscv-gcc-1
Commit 3b6d1699 by Vladimir Makarov Committed by Vladimir Makarov
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regmove.c: Remove. 

2013-10-30  Vladimir Makarov  <vmakarov@redhat.com>

	* regmove.c: Remove.
	* tree-pass.h (make_pass_regmove): Remove.
	* timevar.def (TV_REGMOVE): Remove.
	* passes.def (pass_regmove): Remove.
	* opts.c (default_options_table): Remove entry for regmove.
	* doc/passes.texi: Remove regmove pass description.
	* doc/invoke.texi (-foptimize-register-move, -fregmove): Remove
	options.
	(-fdump-rtl-regmove): Ditto.
	* common.opt (foptimize-register-move, fregmove): Ignore.
	* Makefile.in (OBJS): Remove regmove.o.
	* regmove.c: Remove.
	* ira-int.h (struct ira_allocno_pref, ira_pref_t): New structure
	and type.
	(struct ira_allocno) New member allocno_prefs.
	(ALLOCNO_PREFS): New macro.
	(ira_prefs, ira_prefs_num): New external vars.
	(ira_setup_alts, ira_get_dup_out_num, ira_debug_pref): New
	prototypes.
	(ira_debug_prefs, ira_debug_allocno_prefs, ira_create_pref):
	Ditto.
	(ira_add_allocno_pref, ira_remove_pref, ira_remove_allocno_prefs):
	Ditto.
	(ira_add_allocno_copy_to_list): Remove prototype.
	(ira_swap_allocno_copy_ends_if_necessary): Ditto.
	(ira_pref_iterator): New type.
	(ira_pref_iter_init, ira_pref_iter_cond): New functions.
	(FOR_EACH_PREF): New macro.
	* ira.c (commutative_constraint_p): Move from ira-conflicts.c.
	(ira_get_dup_out_num): Ditto. Rename from get_dup_num.  Modify the
	code.
	(ira_setup_alts): New function.
	(decrease_live_ranges_number): New function.
	(ira): Call the above function.
	* ira-build.c (ira_prefs, ira_prefs_num): New global vars.
	(ira_create_allocno): Initialize allocno prefs.
	(pref_pool, pref_vec): New static vars.
	(initiate_prefs, find_allocno_pref, ira_create_pref): New
	functions.
	(add_allocno_pref_to_list, ira_add_allocno_pref, print_pref): Ditto.
	(ira_debug_pref, print_prefs, ira_debug_prefs): Ditto.
	(print_allocno_prefs, ira_debug_allocno_prefs, finish_pref): Ditto.
	(ira_remove_pref, ira_remove_allocno_prefs, finish_prefs): Ditto.
	(ira_add_allocno_copy_to_list): Make static.  Rename to
	add_allocno_copy_to_list.
	(ira_swap_allocno_copy_ends_if_necessary): Make static.  Rename to
	swap_allocno_copy_ends_if_necessary.
	(remove_unnecessary_allocnos, remove_low_level_allocnos): Call
	ira_remove_allocno_prefs.
	(ira_flattening): Ditto.
	(ira_build): Call initiate_prefs, print_prefs.
	(ira_destroy): Call finish_prefs.
	* ira-color.c (struct update_cost_record): New.
	(struct allocno_color_data): Add new member update_cost_records.
	(update_cost_record_pool): New static var.
	(init_update_cost_records, get_update_cost_record): New functions.
	(free_update_cost_record_list, finish_update_cost_records): Ditto.
	(struct update_cost_queue_elem): Add member from.
	(initiate_cost_update): Call init_update_cost_records.
	(finish_cost_update): Call finish_update_cost_records.
	(queue_update_cost, get_next_update_cost): Add new param from.
	(Update_allocno_cost, update_costs_from_allocno): New functions.
	(update_costs_from_prefs): Ditto.
	(update_copy_costs): Rename to update_costs_from_copies.
	(restore_costs_from_copies): New function.
	(update_conflict_hard_regno_costs): Don't go back.
	(assign_hard_reg): Call restore_costs_from_copies.  Add printing
	more debug info.
	(pop_allocnos): Add priniting more debug info.
	(color_allocnos): Remove prefs for conflicting hard regs.
	Call update_costs_from_prefs.
	* ira-conflicts.c (commutative_constraint_p): Move to ira.c
	(get_dup_num): Rename, modify, and move to ira.c
	(process_regs_for_copy): Add prefs.
	(add_insn_allocno_copies): Put src as first arg of
	process_regs_for_copy.  Remove dead code.  Call ira_setup_alts.
	* ira-costs.c (record_reg_classes): Modify and move code into
	record_operands_costs.
	(find_costs_and_classes): Create prefs for the hard reg of small
	reg class.
	(process_bb_node_for_hard_reg_moves): Add prefs.

2013-10-30  Vladimir Makarov  <vmakarov@redhat.com>

	* gcc.target/i386/fma_double_3.c: Use pattern for
	scan-assembler-times instead of just one insn name.
	* gcc.target/i386/fma_double_5.c: Ditto.
	* gcc.target/i386/fma_float_3.c: Ditto.
	* gcc.target/i386/fma_float_5.c: Ditto.
	* gcc.target/i386/l_fma_double_1.c: Ditto.
	* gcc.target/i386/l_fma_double_2.c: Ditto.
	* gcc.target/i386/l_fma_double_3.c: Ditto.
	* gcc.target/i386/l_fma_double_4.c: Ditto.
	* gcc.target/i386/l_fma_double_5.c: Ditto.
	* gcc.target/i386/l_fma_double_6.c: Ditto.
	* gcc.target/i386/l_fma_float_1.c: Ditto.
	* gcc.target/i386/l_fma_float_2.c: Ditto.
	* gcc.target/i386/l_fma_float_3.c: Ditto.
	* gcc.target/i386/l_fma_float_4.c: Ditto.
	* gcc.target/i386/l_fma_float_5.c: Ditto.
	* gcc.target/i386/l_fma_float_6.c: Ditto.

From-SVN: r204212
parent 1bef9b23
Showing with 615 additions and 387 deletions
gcc/ChangeLog
2013-10-30 Vladimir Makarov <vmakarov@redhat.com>
* regmove.c: Remove.
* tree-pass.h (make_pass_regmove): Remove.
* timevar.def (TV_REGMOVE): Remove.
* passes.def (pass_regmove): Remove.
* opts.c (default_options_table): Remove entry for regmove.
* doc/passes.texi: Remove regmove pass description.
* doc/invoke.texi (-foptimize-register-move, -fregmove): Remove
options.
(-fdump-rtl-regmove): Ditto.
* common.opt (foptimize-register-move, fregmove): Ignore.
* Makefile.in (OBJS): Remove regmove.o.
* regmove.c: Remove.
* ira-int.h (struct ira_allocno_pref, ira_pref_t): New structure
and type.
(struct ira_allocno) New member allocno_prefs.
(ALLOCNO_PREFS): New macro.
(ira_prefs, ira_prefs_num): New external vars.
(ira_setup_alts, ira_get_dup_out_num, ira_debug_pref): New
prototypes.
(ira_debug_prefs, ira_debug_allocno_prefs, ira_create_pref):
Ditto.
(ira_add_allocno_pref, ira_remove_pref, ira_remove_allocno_prefs):
Ditto.
(ira_add_allocno_copy_to_list): Remove prototype.
(ira_swap_allocno_copy_ends_if_necessary): Ditto.
(ira_pref_iterator): New type.
(ira_pref_iter_init, ira_pref_iter_cond): New functions.
(FOR_EACH_PREF): New macro.
* ira.c (commutative_constraint_p): Move from ira-conflicts.c.
(ira_get_dup_out_num): Ditto. Rename from get_dup_num. Modify the
code.
(ira_setup_alts): New function.
(decrease_live_ranges_number): New function.
(ira): Call the above function.
* ira-build.c (ira_prefs, ira_prefs_num): New global vars.
(ira_create_allocno): Initialize allocno prefs.
(pref_pool, pref_vec): New static vars.
(initiate_prefs, find_allocno_pref, ira_create_pref): New
functions.
(add_allocno_pref_to_list, ira_add_allocno_pref, print_pref): Ditto.
(ira_debug_pref, print_prefs, ira_debug_prefs): Ditto.
(print_allocno_prefs, ira_debug_allocno_prefs, finish_pref): Ditto.
(ira_remove_pref, ira_remove_allocno_prefs, finish_prefs): Ditto.
(ira_add_allocno_copy_to_list): Make static. Rename to
add_allocno_copy_to_list.
(ira_swap_allocno_copy_ends_if_necessary): Make static. Rename to
swap_allocno_copy_ends_if_necessary.
(remove_unnecessary_allocnos, remove_low_level_allocnos): Call
ira_remove_allocno_prefs.
(ira_flattening): Ditto.
(ira_build): Call initiate_prefs, print_prefs.
(ira_destroy): Call finish_prefs.
* ira-color.c (struct update_cost_record): New.
(struct allocno_color_data): Add new member update_cost_records.
(update_cost_record_pool): New static var.
(init_update_cost_records, get_update_cost_record): New functions.
(free_update_cost_record_list, finish_update_cost_records): Ditto.
(struct update_cost_queue_elem): Add member from.
(initiate_cost_update): Call init_update_cost_records.
(finish_cost_update): Call finish_update_cost_records.
(queue_update_cost, get_next_update_cost): Add new param from.
(Update_allocno_cost, update_costs_from_allocno): New functions.
(update_costs_from_prefs): Ditto.
(update_copy_costs): Rename to update_costs_from_copies.
(restore_costs_from_copies): New function.
(update_conflict_hard_regno_costs): Don't go back.
(assign_hard_reg): Call restore_costs_from_copies. Add printing
more debug info.
(pop_allocnos): Add priniting more debug info.
(color_allocnos): Remove prefs for conflicting hard regs.
Call update_costs_from_prefs.
* ira-conflicts.c (commutative_constraint_p): Move to ira.c
(get_dup_num): Rename, modify, and move to ira.c
(process_regs_for_copy): Add prefs.
(add_insn_allocno_copies): Put src as first arg of
process_regs_for_copy. Remove dead code. Call ira_setup_alts.
* ira-costs.c (record_reg_classes): Modify and move code into
record_operands_costs.
(find_costs_and_classes): Create prefs for the hard reg of small
reg class.
(process_bb_node_for_hard_reg_moves): Add prefs.
2013-10-30 Richard Biener <rguenther@suse.de>
PR middle-end/57100
gcc/Makefile.in
......@@ -1328,7 +1328,6 @@ OBJS = \
reg-stack.o \
regcprop.o \
reginfo.o \
regmove.o \
regrename.o \
regstat.o \
reload.o \
......
gcc/common.opt
......@@ -1597,8 +1597,8 @@ Common Joined RejectNegative Var(common_deferred_options) Defer
-fopt-info[-<type>=filename] Dump compiler optimization details
foptimize-register-move
Common Report Var(flag_regmove) Optimization
Do the full register move optimization pass
Common Ignore
Does nothing. Preserved for backward compatibility.
foptimize-sibling-calls
Common Report Var(flag_optimize_sibling_calls) Optimization
......@@ -1735,8 +1735,8 @@ Common Report Var(flag_pcc_struct_return,0) Optimization
Return small aggregates in registers
fregmove
Common Report Var(flag_regmove) Optimization
Enables a register move optimization
Common Ignore
Does nothing. Preserved for backward compatibility.
frename-registers
Common Report Var(flag_rename_registers) Init(2) Optimization
......
gcc/doc/invoke.texi
......@@ -388,13 +388,13 @@ Objective-C and Objective-C++ Dialects}.
-fno-inline -fno-math-errno -fno-peephole -fno-peephole2 @gol
-fno-sched-interblock -fno-sched-spec -fno-signed-zeros @gol
-fno-toplevel-reorder -fno-trapping-math -fno-zero-initialized-in-bss @gol
-fomit-frame-pointer -foptimize-register-move -foptimize-sibling-calls @gol
-fomit-frame-pointer -foptimize-sibling-calls @gol
-fpartial-inlining -fpeel-loops -fpredictive-commoning @gol
-fprefetch-loop-arrays -fprofile-report @gol
-fprofile-correction -fprofile-dir=@var{path} -fprofile-generate @gol
-fprofile-generate=@var{path} @gol
-fprofile-use -fprofile-use=@var{path} -fprofile-values @gol
-freciprocal-math -free -fregmove -frename-registers -freorder-blocks @gol
-freciprocal-math -free -frename-registers -freorder-blocks @gol
-freorder-blocks-and-partition -freorder-functions @gol
-frerun-cse-after-loop -freschedule-modulo-scheduled-loops @gol
-frounding-math -fsched2-use-superblocks -fsched-pressure @gol
......@@ -5822,10 +5822,6 @@ Dump after post-reload optimizations.
@opindex fdump-rtl-pro_and_epilogue
Dump after generating the function prologues and epilogues.
@item -fdump-rtl-regmove
@opindex fdump-rtl-regmove
Dump after the register move pass.
@item -fdump-rtl-sched1
@itemx -fdump-rtl-sched2
@opindex fdump-rtl-sched1
......@@ -6738,7 +6734,6 @@ also turns on the following optimization flags:
-foptimize-sibling-calls @gol
-fpartial-inlining @gol
-fpeephole2 @gol
-fregmove @gol
-freorder-blocks -freorder-functions @gol
-frerun-cse-after-loop @gol
-fsched-interblock -fsched-spec @gol
......@@ -7262,20 +7257,6 @@ registers after writing to their lower 32-bit half.
Enabled for x86 at levels @option{-O2}, @option{-O3}.
@item -foptimize-register-move
@itemx -fregmove
@opindex foptimize-register-move
@opindex fregmove
Attempt to reassign register numbers in move instructions and as
operands of other simple instructions in order to maximize the amount of
register tying. This is especially helpful on machines with two-operand
instructions.
Note @option{-fregmove} and @option{-foptimize-register-move} are the same
optimization.
Enabled at levels @option{-O2}, @option{-O3}, @option{-Os}.
@item -fira-algorithm=@var{algorithm}
Use the specified coloring algorithm for the integrated register
allocator. The @var{algorithm} argument can be @samp{priority}, which
......
gcc/doc/passes.texi
......@@ -823,14 +823,6 @@ RTL expressions for the instructions by substitution, simplifies the
result using algebra, and then attempts to match the result against
the machine description. The code is located in @file{combine.c}.
@item Register movement
This pass looks for cases where matching constraints would force an
instruction to need a reload, and this reload would be a
register-to-register move. It then attempts to change the registers
used by the instruction to avoid the move instruction. The code is
located in @file{regmove.c}.
@item Mode switching optimization
This pass looks for instructions that require the processor to be in a
......@@ -869,11 +861,6 @@ them on the stack. This is done in several subpasses:
@itemize @bullet
@item
Register move optimizations. This pass makes some simple RTL code
transformations which improve the subsequent register allocation. The
source file is @file{regmove.c}.
@item
The integrated register allocator (@acronym{IRA}). It is called
integrated because coalescing, register live range splitting, and hard
register preferencing are done on-the-fly during coloring. It also
......
gcc/ira-build.c
......@@ -79,6 +79,13 @@ int ira_objects_num;
/* Map a conflict id to its conflict record. */
ira_object_t *ira_object_id_map;
/* Array of references to all allocno preferences. The order number
of the preference corresponds to the index in the array. */
ira_pref_t *ira_prefs;
/* Size of the previous array. */
int ira_prefs_num;
/* Array of references to all copies. The order number of the copy
corresponds to the index in the array. Removed copies have NULL
element value. */
......@@ -515,6 +522,7 @@ ira_create_allocno (int regno, bool cap_p,
ALLOCNO_BAD_SPILL_P (a) = false;
ALLOCNO_ASSIGNED_P (a) = false;
ALLOCNO_MODE (a) = (regno < 0 ? VOIDmode : PSEUDO_REGNO_MODE (regno));
ALLOCNO_PREFS (a) = NULL;
ALLOCNO_COPIES (a) = NULL;
ALLOCNO_HARD_REG_COSTS (a) = NULL;
ALLOCNO_CONFLICT_HARD_REG_COSTS (a) = NULL;
......@@ -1163,6 +1171,195 @@ finish_allocnos (void)
/* Pools for allocno preferences. */
static alloc_pool pref_pool;
/* Vec containing references to all created preferences. It is a
container of array ira_prefs. */
static vec<ira_pref_t> pref_vec;
/* The function initializes data concerning allocno prefs. */
static void
initiate_prefs (void)
{
pref_pool
= create_alloc_pool ("prefs", sizeof (struct ira_allocno_pref), 100);
pref_vec.create (get_max_uid ());
ira_prefs = NULL;
ira_prefs_num = 0;
}
/* Return pref for A and HARD_REGNO if any. */
static ira_pref_t
find_allocno_pref (ira_allocno_t a, int hard_regno)
{
ira_pref_t pref;
for (pref = ALLOCNO_PREFS (a); pref != NULL; pref = pref->next_pref)
if (pref->allocno == a && pref->hard_regno == hard_regno)
return pref;
return NULL;
}
/* Create and return pref with given attributes A, HARD_REGNO, and FREQ. */
ira_pref_t
ira_create_pref (ira_allocno_t a, int hard_regno, int freq)
{
ira_pref_t pref;
pref = (ira_pref_t) pool_alloc (pref_pool);
pref->num = ira_prefs_num;
pref->allocno = a;
pref->hard_regno = hard_regno;
pref->freq = freq;
pref_vec.safe_push (pref);
ira_prefs = pref_vec.address ();
ira_prefs_num = pref_vec.length ();
return pref;
}
/* Attach a pref PREF to the cooresponding allocno. */
static void
add_allocno_pref_to_list (ira_pref_t pref)
{
ira_allocno_t a = pref->allocno;
pref->next_pref = ALLOCNO_PREFS (a);
ALLOCNO_PREFS (a) = pref;
}
/* Create (or update frequency if the pref already exists) the pref of
allocnos A preferring HARD_REGNO with frequency FREQ. */
void
ira_add_allocno_pref (ira_allocno_t a, int hard_regno, int freq)
{
ira_pref_t pref;
if (freq <= 0)
return;
if ((pref = find_allocno_pref (a, hard_regno)) != NULL)
{
pref->freq += freq;
return;
}
pref = ira_create_pref (a, hard_regno, freq);
ira_assert (a != NULL);
add_allocno_pref_to_list (pref);
}
/* Print info about PREF into file F. */
static void
print_pref (FILE *f, ira_pref_t pref)
{
fprintf (f, " pref%d:a%d(r%d)<-hr%d@%d\n", pref->num,
ALLOCNO_NUM (pref->allocno), ALLOCNO_REGNO (pref->allocno),
pref->hard_regno, pref->freq);
}
/* Print info about PREF into stderr. */
void
ira_debug_pref (ira_pref_t pref)
{
print_pref (stderr, pref);
}
/* Print info about all prefs into file F. */
static void
print_prefs (FILE *f)
{
ira_pref_t pref;
ira_pref_iterator pi;
FOR_EACH_PREF (pref, pi)
print_pref (f, pref);
}
/* Print info about all prefs into stderr. */
void
ira_debug_prefs (void)
{
print_prefs (stderr);
}
/* Print info about prefs involving allocno A into file F. */
static void
print_allocno_prefs (FILE *f, ira_allocno_t a)
{
ira_pref_t pref;
fprintf (f, " a%d(r%d):", ALLOCNO_NUM (a), ALLOCNO_REGNO (a));
for (pref = ALLOCNO_PREFS (a); pref != NULL; pref = pref->next_pref)
fprintf (f, " pref%d:hr%d@%d", pref->num, pref->hard_regno, pref->freq);
fprintf (f, "\n");
}
/* Print info about prefs involving allocno A into stderr. */
void
ira_debug_allocno_prefs (ira_allocno_t a)
{
print_allocno_prefs (stderr, a);
}
/* The function frees memory allocated for PREF. */
static void
finish_pref (ira_pref_t pref)
{
ira_prefs[pref->num] = NULL;
pool_free (pref_pool, pref);
}
/* Remove PREF from the list of allocno prefs and free memory for
it. */
void
ira_remove_pref (ira_pref_t pref)
{
ira_pref_t cpref, prev;
if (internal_flag_ira_verbose > 1 && ira_dump_file != NULL)
fprintf (ira_dump_file, " Removing pref%d:hr%d@%d\n",
pref->num, pref->hard_regno, pref->freq);
for (prev = NULL, cpref = ALLOCNO_PREFS (pref->allocno);
cpref != NULL;
prev = cpref, cpref = cpref->next_pref)
if (cpref == pref)
break;
ira_assert (cpref != NULL);
if (prev == NULL)
ALLOCNO_PREFS (pref->allocno) = pref->next_pref;
else
prev->next_pref = pref->next_pref;
finish_pref (pref);
}
/* Remove all prefs of allocno A. */
void
ira_remove_allocno_prefs (ira_allocno_t a)
{
ira_pref_t pref, next_pref;
for (pref = ALLOCNO_PREFS (a); pref != NULL; pref = next_pref)
{
next_pref = pref->next_pref;
finish_pref (pref);
}
ALLOCNO_PREFS (a) = NULL;
}
/* Free memory allocated for all prefs. */
static void
finish_prefs (void)
{
ira_pref_t pref;
ira_pref_iterator pi;
FOR_EACH_PREF (pref, pi)
finish_pref (pref);
pref_vec.release ();
free_alloc_pool (pref_pool);
}
/* Pools for copies. */
static alloc_pool copy_pool;
......@@ -1235,8 +1432,8 @@ ira_create_copy (ira_allocno_t first, ira_allocno_t second, int freq,
}
/* Attach a copy CP to allocnos involved into the copy. */
void
ira_add_allocno_copy_to_list (ira_copy_t cp)
static void
add_allocno_copy_to_list (ira_copy_t cp)
{
ira_allocno_t first = cp->first, second = cp->second;
......@@ -1264,8 +1461,8 @@ ira_add_allocno_copy_to_list (ira_copy_t cp)
/* Make a copy CP a canonical copy where number of the
first allocno is less than the second one. */
void
ira_swap_allocno_copy_ends_if_necessary (ira_copy_t cp)
static void
swap_allocno_copy_ends_if_necessary (ira_copy_t cp)
{
ira_allocno_t temp;
ira_copy_t temp_cp;
......@@ -1305,8 +1502,8 @@ ira_add_allocno_copy (ira_allocno_t first, ira_allocno_t second, int freq,
cp = ira_create_copy (first, second, freq, constraint_p, insn,
loop_tree_node);
ira_assert (first != NULL && second != NULL);
ira_add_allocno_copy_to_list (cp);
ira_swap_allocno_copy_ends_if_necessary (cp);
add_allocno_copy_to_list (cp);
swap_allocno_copy_ends_if_necessary (cp);
return cp;
}
......@@ -2305,6 +2502,7 @@ remove_unnecessary_allocnos (void)
map to avoid info propagation of subsequent
allocno into this already removed allocno. */
a_node->regno_allocno_map[regno] = NULL;
ira_remove_allocno_prefs (a);
finish_allocno (a);
}
}
......@@ -2388,7 +2586,10 @@ remove_low_level_allocnos (void)
#endif
}
else
finish_allocno (a);
{
ira_remove_allocno_prefs (a);
finish_allocno (a);
}
}
if (merged_p)
ira_rebuild_start_finish_chains ();
......@@ -3105,6 +3306,7 @@ ira_flattening (int max_regno_before_emit, int ira_max_point_before_emit)
if (internal_flag_ira_verbose > 4 && ira_dump_file != NULL)
fprintf (ira_dump_file, " Remove a%dr%d\n",
ALLOCNO_NUM (a), REGNO (allocno_emit_reg (a)));
ira_remove_allocno_prefs (a);
finish_allocno (a);
continue;
}
......@@ -3131,8 +3333,8 @@ ira_flattening (int max_regno_before_emit, int ira_max_point_before_emit)
ira_assert
(ALLOCNO_LOOP_TREE_NODE (cp->first) == ira_loop_tree_root
&& ALLOCNO_LOOP_TREE_NODE (cp->second) == ira_loop_tree_root);
ira_add_allocno_copy_to_list (cp);
ira_swap_allocno_copy_ends_if_necessary (cp);
add_allocno_copy_to_list (cp);
swap_allocno_copy_ends_if_necessary (cp);
}
rebuild_regno_allocno_maps ();
if (ira_max_point != ira_max_point_before_emit)
......@@ -3220,6 +3422,7 @@ ira_build (void)
df_analyze ();
initiate_cost_vectors ();
initiate_allocnos ();
initiate_prefs ();
initiate_copies ();
create_loop_tree_nodes ();
form_loop_tree ();
......@@ -3265,6 +3468,8 @@ ira_build (void)
}
if (internal_flag_ira_verbose > 2 && ira_dump_file != NULL)
print_copies (ira_dump_file);
if (internal_flag_ira_verbose > 2 && ira_dump_file != NULL)
print_prefs (ira_dump_file);
if (internal_flag_ira_verbose > 0 && ira_dump_file != NULL)
{
int n, nr, nr_big;
......@@ -3304,6 +3509,7 @@ void
ira_destroy (void)
{
finish_loop_tree_nodes ();
finish_prefs ();
finish_copies ();
finish_allocnos ();
finish_cost_vectors ();
......
gcc/ira-conflicts.c
......@@ -208,149 +208,6 @@ allocnos_conflict_for_copy_p (ira_allocno_t a1, ira_allocno_t a2)
return OBJECTS_CONFLICT_P (obj1, obj2);
}
/* Return TRUE if the operand constraint STR is commutative. */
static bool
commutative_constraint_p (const char *str)
{
int curr_alt, c;
bool ignore_p;
for (ignore_p = false, curr_alt = 0;;)
{
c = *str;
if (c == '\0')
break;
str += CONSTRAINT_LEN (c, str);
if (c == '#' || !recog_data.alternative_enabled_p[curr_alt])
ignore_p = true;
else if (c == ',')
{
curr_alt++;
ignore_p = false;
}
else if (! ignore_p)
{
/* Usually `%' is the first constraint character but the
documentation does not require this. */
if (c == '%')
return true;
}
}
return false;
}
/* Return the number of the operand which should be the same in any
case as operand with number OP_NUM (or negative value if there is
no such operand). If USE_COMMUT_OP_P is TRUE, the function makes
temporarily commutative operand exchange before this. The function
takes only really possible alternatives into consideration. */
static int
get_dup_num (int op_num, bool use_commut_op_p)
{
int curr_alt, c, original, dup;
bool ignore_p, commut_op_used_p;
const char *str;
rtx op;
if (op_num < 0 || recog_data.n_alternatives == 0)
return -1;
op = recog_data.operand[op_num];
commut_op_used_p = true;
if (use_commut_op_p)
{
if (commutative_constraint_p (recog_data.constraints[op_num]))
op_num++;
else if (op_num > 0 && commutative_constraint_p (recog_data.constraints
[op_num - 1]))
op_num--;
else
commut_op_used_p = false;
}
str = recog_data.constraints[op_num];
for (ignore_p = false, original = -1, curr_alt = 0;;)
{
c = *str;
if (c == '\0')
break;
if (c == '#' || !recog_data.alternative_enabled_p[curr_alt])
ignore_p = true;
else if (c == ',')
{
curr_alt++;
ignore_p = false;
}
else if (! ignore_p)
switch (c)
{
case 'X':
return -1;
case 'm':
case 'o':
/* Accept a register which might be placed in memory. */
return -1;
break;
case 'V':
case '<':
case '>':
break;
case 'p':
if (address_operand (op, VOIDmode))
return -1;
break;
case 'g':
return -1;
case 'r':
case 'a': case 'b': case 'c': case 'd': case 'e': case 'f':
case 'h': case 'j': case 'k': case 'l':
case 'q': case 't': case 'u':
case 'v': case 'w': case 'x': case 'y': case 'z':
case 'A': case 'B': case 'C': case 'D':
case 'Q': case 'R': case 'S': case 'T': case 'U':
case 'W': case 'Y': case 'Z':
{
enum reg_class cl;
cl = (c == 'r'
? GENERAL_REGS : REG_CLASS_FROM_CONSTRAINT (c, str));
if (cl != NO_REGS)
return -1;
#ifdef EXTRA_CONSTRAINT_STR
else if (EXTRA_CONSTRAINT_STR (op, c, str))
return -1;
#endif
break;
}
case '0': case '1': case '2': case '3': case '4':
case '5': case '6': case '7': case '8': case '9':
if (original != -1 && original != c)
return -1;
original = c;
break;
}
str += CONSTRAINT_LEN (c, str);
}
if (original == -1)
return -1;
dup = original - '0';
if (use_commut_op_p)
{
if (commutative_constraint_p (recog_data.constraints[dup]))
dup++;
else if (dup > 0
&& commutative_constraint_p (recog_data.constraints[dup -1]))
dup--;
else if (! commut_op_used_p)
return -1;
}
return dup;
}
/* Check that X is REG or SUBREG of REG. */
#define REG_SUBREG_P(x) \
(REG_P (x) || (GET_CODE (x) == SUBREG && REG_P (SUBREG_REG (x))))
......@@ -461,6 +318,7 @@ process_regs_for_copy (rtx reg1, rtx reg2, bool constraint_p,
ALLOCNO_CONFLICT_HARD_REG_COSTS (a)[index] -= cost;
if (ALLOCNO_HARD_REG_COSTS (a)[index] < ALLOCNO_CLASS_COST (a))
ALLOCNO_CLASS_COST (a) = ALLOCNO_HARD_REG_COSTS (a)[index];
ira_add_allocno_pref (a, allocno_preferenced_hard_regno, freq);
a = ira_parent_or_cap_allocno (a);
}
while (a != NULL);
......@@ -498,9 +356,9 @@ static void
add_insn_allocno_copies (rtx insn)
{
rtx set, operand, dup;
const char *str;
bool commut_p, bound_p[MAX_RECOG_OPERANDS];
int i, j, n, freq;
bool bound_p[MAX_RECOG_OPERANDS];
int i, n, freq;
HARD_REG_SET alts;
freq = REG_FREQ_FROM_BB (BLOCK_FOR_INSN (insn));
if (freq == 0)
......@@ -513,7 +371,7 @@ add_insn_allocno_copies (rtx insn)
? SET_SRC (set)
: SUBREG_REG (SET_SRC (set))) != NULL_RTX)
{
process_regs_for_copy (SET_DEST (set), SET_SRC (set),
process_regs_for_copy (SET_SRC (set), SET_DEST (set),
false, insn, freq);
return;
}
......@@ -521,7 +379,7 @@ add_insn_allocno_copies (rtx insn)
there are no dead registers, there will be no such copies. */
if (! find_reg_note (insn, REG_DEAD, NULL_RTX))
return;
extract_insn (insn);
ira_setup_alts (insn, alts);
for (i = 0; i < recog_data.n_operands; i++)
bound_p[i] = false;
for (i = 0; i < recog_data.n_operands; i++)
......@@ -529,21 +387,18 @@ add_insn_allocno_copies (rtx insn)
operand = recog_data.operand[i];
if (! REG_SUBREG_P (operand))
continue;
str = recog_data.constraints[i];
while (*str == ' ' || *str == '\t')
str++;
for (j = 0, commut_p = false; j < 2; j++, commut_p = true)
if ((n = get_dup_num (i, commut_p)) >= 0)
{
bound_p[n] = true;
dup = recog_data.operand[n];
if (REG_SUBREG_P (dup)
&& find_reg_note (insn, REG_DEAD,
REG_P (operand)
? operand
: SUBREG_REG (operand)) != NULL_RTX)
process_regs_for_copy (operand, dup, true, NULL_RTX, freq);
}
if ((n = ira_get_dup_out_num (i, alts)) >= 0)
{
bound_p[n] = true;
dup = recog_data.operand[n];
if (REG_SUBREG_P (dup)
&& find_reg_note (insn, REG_DEAD,
REG_P (operand)
? operand
: SUBREG_REG (operand)) != NULL_RTX)
process_regs_for_copy (operand, dup, true, NULL_RTX,
freq);
}
}
for (i = 0; i < recog_data.n_operands; i++)
{
......
gcc/ira-int.h
......@@ -57,6 +57,7 @@ extern FILE *ira_dump_file;
allocnos. */
typedef struct live_range *live_range_t;
typedef struct ira_allocno *ira_allocno_t;
typedef struct ira_allocno_pref *ira_pref_t;
typedef struct ira_allocno_copy *ira_copy_t;
typedef struct ira_object *ira_object_t;
......@@ -346,6 +347,8 @@ struct ira_allocno
register class living at the point than number of hard-registers
of the class available for the allocation. */
int excess_pressure_points_num;
/* Allocno hard reg preferences. */
ira_pref_t allocno_prefs;
/* Copies to other non-conflicting allocnos. The copies can
represent move insn or potential move insn usually because of two
operand insn constraints. */
......@@ -426,6 +429,7 @@ struct ira_allocno
#define ALLOCNO_BAD_SPILL_P(A) ((A)->bad_spill_p)
#define ALLOCNO_ASSIGNED_P(A) ((A)->assigned_p)
#define ALLOCNO_MODE(A) ((A)->mode)
#define ALLOCNO_PREFS(A) ((A)->allocno_prefs)
#define ALLOCNO_COPIES(A) ((A)->allocno_copies)
#define ALLOCNO_HARD_REG_COSTS(A) ((A)->hard_reg_costs)
#define ALLOCNO_UPDATED_HARD_REG_COSTS(A) ((A)->updated_hard_reg_costs)
......@@ -516,6 +520,33 @@ extern ira_object_t *ira_object_id_map;
/* The size of the previous array. */
extern int ira_objects_num;
/* The following structure represents a hard register prefererence of
allocno. The preference represent move insns or potential move
insns usually because of two operand insn constraints. One move
operand is a hard register. */
struct ira_allocno_pref
{
/* The unique order number of the preference node starting with 0. */
int num;
/* Preferred hard register. */
int hard_regno;
/* Accumulated execution frequency of insns from which the
preference created. */
int freq;
/* Given allocno. */
ira_allocno_t allocno;
/* All prefernces with the same allocno are linked by the following
member. */
ira_pref_t next_pref;
};
/* Array of references to all allocno preferences. The order number
of the preference corresponds to the index in the array. */
extern ira_pref_t *ira_prefs;
/* Size of the previous array. */
extern int ira_prefs_num;
/* The following structure represents a copy of two allocnos. The
copies represent move insns or potential move insns usually because
of two operand insn constraints. To remove register shuffle, we
......@@ -925,6 +956,8 @@ extern void ira_print_disposition (FILE *);
extern void ira_debug_disposition (void);
extern void ira_debug_allocno_classes (void);
extern void ira_init_register_move_cost (enum machine_mode);
extern void ira_setup_alts (rtx insn, HARD_REG_SET &alts);
extern int ira_get_dup_out_num (int op_num, HARD_REG_SET &alts);
/* ira-build.c */
......@@ -932,6 +965,10 @@ extern void ira_init_register_move_cost (enum machine_mode);
extern ira_loop_tree_node_t ira_curr_loop_tree_node;
extern ira_allocno_t *ira_curr_regno_allocno_map;
extern void ira_debug_pref (ira_pref_t);
extern void ira_debug_prefs (void);
extern void ira_debug_allocno_prefs (ira_allocno_t);
extern void ira_debug_copy (ira_copy_t);
extern void debug (ira_allocno_copy &ref);
extern void debug (ira_allocno_copy *ptr);
......@@ -963,10 +1000,12 @@ extern bool ira_live_ranges_intersect_p (live_range_t, live_range_t);
extern void ira_finish_live_range (live_range_t);
extern void ira_finish_live_range_list (live_range_t);
extern void ira_free_allocno_updated_costs (ira_allocno_t);
extern ira_pref_t ira_create_pref (ira_allocno_t, int, int);
extern void ira_add_allocno_pref (ira_allocno_t, int, int);
extern void ira_remove_pref (ira_pref_t);
extern void ira_remove_allocno_prefs (ira_allocno_t);
extern ira_copy_t ira_create_copy (ira_allocno_t, ira_allocno_t,
int, bool, rtx, ira_loop_tree_node_t);
extern void ira_add_allocno_copy_to_list (ira_copy_t);
extern void ira_swap_allocno_copy_ends_if_necessary (ira_copy_t);
extern ira_copy_t ira_add_allocno_copy (ira_allocno_t, ira_allocno_t, int,
bool, rtx, ira_loop_tree_node_t);
......@@ -1151,6 +1190,44 @@ ira_allocno_object_iter_cond (ira_allocno_object_iterator *i, ira_allocno_t a,
ira_allocno_object_iter_cond (&(ITER), (A), &(O));)
/* The iterator for prefs. */
typedef struct {
/* The number of the current element in IRA_PREFS. */
int n;
} ira_pref_iterator;
/* Initialize the iterator I. */
static inline void
ira_pref_iter_init (ira_pref_iterator *i)
{
i->n = 0;
}
/* Return TRUE if we have more prefs to visit, in which case *PREF is
set to the pref to be visited. Otherwise, return FALSE. */
static inline bool
ira_pref_iter_cond (ira_pref_iterator *i, ira_pref_t *pref)
{
int n;
for (n = i->n; n < ira_prefs_num; n++)
if (ira_prefs[n] != NULL)
{
*pref = ira_prefs[n];
i->n = n + 1;
return true;
}
return false;
}
/* Loop over all prefs. In each iteration, P is set to the next
pref. ITER is an instance of ira_pref_iterator used to iterate
the prefs. */
#define FOR_EACH_PREF(P, ITER) \
for (ira_pref_iter_init (&(ITER)); \
ira_pref_iter_cond (&(ITER), &(P));)
/* The iterator for copies. */
typedef struct {
/* The number of the current element in IRA_COPIES. */
......
gcc/opts.c
......@@ -473,7 +473,6 @@ static const struct default_options default_options_table[] =
{ OPT_LEVELS_2_PLUS_SPEED_ONLY, OPT_fschedule_insns, NULL, 1 },
{ OPT_LEVELS_2_PLUS, OPT_fschedule_insns2, NULL, 1 },
#endif
{ OPT_LEVELS_2_PLUS, OPT_fregmove, NULL, 1 },
{ OPT_LEVELS_2_PLUS, OPT_fstrict_aliasing, NULL, 1 },
{ OPT_LEVELS_2_PLUS, OPT_fstrict_overflow, NULL, 1 },
{ OPT_LEVELS_2_PLUS, OPT_freorder_blocks, NULL, 1 },
......
gcc/passes.def
......@@ -350,7 +350,6 @@ along with GCC; see the file COPYING3. If not see
NEXT_PASS (pass_combine);
NEXT_PASS (pass_if_after_combine);
NEXT_PASS (pass_partition_blocks);
NEXT_PASS (pass_regmove);
NEXT_PASS (pass_outof_cfg_layout_mode);
NEXT_PASS (pass_split_all_insns);
NEXT_PASS (pass_lower_subreg2);
......
gcc/testsuite/ChangeLog
2013-10-30 Vladimir Makarov <vmakarov@redhat.com>
* gcc.target/i386/fma_double_3.c: Use pattern for
scan-assembler-times instead of just one insn name.
* gcc.target/i386/fma_double_5.c: Ditto.
* gcc.target/i386/fma_float_3.c: Ditto.
* gcc.target/i386/fma_float_5.c: Ditto.
* gcc.target/i386/l_fma_double_1.c: Ditto.
* gcc.target/i386/l_fma_double_2.c: Ditto.
* gcc.target/i386/l_fma_double_3.c: Ditto.
* gcc.target/i386/l_fma_double_4.c: Ditto.
* gcc.target/i386/l_fma_double_5.c: Ditto.
* gcc.target/i386/l_fma_double_6.c: Ditto.
* gcc.target/i386/l_fma_float_1.c: Ditto.
* gcc.target/i386/l_fma_float_2.c: Ditto.
* gcc.target/i386/l_fma_float_3.c: Ditto.
* gcc.target/i386/l_fma_float_4.c: Ditto.
* gcc.target/i386/l_fma_float_5.c: Ditto.
* gcc.target/i386/l_fma_float_6.c: Ditto.
2013-10-30 Christian Bruel <christian.bruel@st.com>
* gcc.c-torture/execute/builtins/strncmp-2.c: Enable for SH.
......
gcc/testsuite/gcc.target/i386/fma_double_3.c
......@@ -8,11 +8,7 @@
#include "fma_3.h"
/* { dg-final { scan-assembler-times "vfmadd132sd" 4 } } */
/* { dg-final { scan-assembler-times "vfmadd231sd" 4 } } */
/* { dg-final { scan-assembler-times "vfmsub132sd" 4 } } */
/* { dg-final { scan-assembler-times "vfmsub231sd" 4 } } */
/* { dg-final { scan-assembler-times "vfnmadd132sd" 4 } } */
/* { dg-final { scan-assembler-times "vfnmadd231sd" 4 } } */
/* { dg-final { scan-assembler-times "vfnmsub132sd" 4 } } */
/* { dg-final { scan-assembler-times "vfnmsub231sd" 4 } } */
/* { dg-final { scan-assembler-times "vfmadd\[123\]+sd" 8 } } */
/* { dg-final { scan-assembler-times "vfmsub\[132\]+sd" 8 } } */
/* { dg-final { scan-assembler-times "vfnmadd\[132\]+sd" 8 } } */
/* { dg-final { scan-assembler-times "vfnmsub\[132\]+sd" 8 } } */
gcc/testsuite/gcc.target/i386/fma_double_5.c
......@@ -8,7 +8,7 @@
#include "fma_5.h"
/* { dg-final { scan-assembler-times "vfmadd132sd" 8 } } */
/* { dg-final { scan-assembler-times "vfmsub132sd" 8 } } */
/* { dg-final { scan-assembler-times "vfnmadd132sd" 8 } } */
/* { dg-final { scan-assembler-times "vfnmsub132sd" 8 } } */
/* { dg-final { scan-assembler-times "vfmadd\[132\]+sd" 8 } } */
/* { dg-final { scan-assembler-times "vfmsub\[132\]+sd" 8 } } */
/* { dg-final { scan-assembler-times "vfnmadd\[132\]+sd" 8 } } */
/* { dg-final { scan-assembler-times "vfnmsub\[132\]+sd" 8 } } */
gcc/testsuite/gcc.target/i386/fma_float_3.c
......@@ -8,11 +8,7 @@
#include "fma_3.h"
/* { dg-final { scan-assembler-times "vfmadd132ss" 4 } } */
/* { dg-final { scan-assembler-times "vfmadd231ss" 4 } } */
/* { dg-final { scan-assembler-times "vfmsub132ss" 4 } } */
/* { dg-final { scan-assembler-times "vfmsub231ss" 4 } } */
/* { dg-final { scan-assembler-times "vfnmadd132ss" 4 } } */
/* { dg-final { scan-assembler-times "vfnmadd231ss" 4 } } */
/* { dg-final { scan-assembler-times "vfnmsub132ss" 4 } } */
/* { dg-final { scan-assembler-times "vfnmsub231ss" 4 } } */
/* { dg-final { scan-assembler-times "vfmadd\[132\]+ss" 8 } } */
/* { dg-final { scan-assembler-times "vfmsub\[132\]+ss" 8 } } */
/* { dg-final { scan-assembler-times "vfnmadd\[132\]+ss" 8 } } */
/* { dg-final { scan-assembler-times "vfnmsub\[132\]+ss" 8 } } */
gcc/testsuite/gcc.target/i386/fma_float_5.c
......@@ -8,7 +8,7 @@
#include "fma_5.h"
/* { dg-final { scan-assembler-times "vfmadd132ss" 8 } } */
/* { dg-final { scan-assembler-times "vfmsub132ss" 8 } } */
/* { dg-final { scan-assembler-times "vfnmadd132ss" 8 } } */
/* { dg-final { scan-assembler-times "vfnmsub132ss" 8 } } */
/* { dg-final { scan-assembler-times "vfmadd\[132\]+ss" 8 } } */
/* { dg-final { scan-assembler-times "vfmsub\[132\]+ss" 8 } } */
/* { dg-final { scan-assembler-times "vfnmadd\[132\]+ss" 8 } } */
/* { dg-final { scan-assembler-times "vfnmsub\[132\]+ss" 8 } } */
gcc/testsuite/gcc.target/i386/l_fma_double_1.c
......@@ -17,11 +17,7 @@ typedef double adouble __attribute__((aligned(sizeof (double))));
/* { dg-final { scan-assembler-times "vfnmadd231pd" 4 } } */
/* { dg-final { scan-assembler-times "vfnmsub132pd" 4 } } */
/* { dg-final { scan-assembler-times "vfnmsub231pd" 4 } } */
/* { dg-final { scan-assembler-times "vfmadd132sd" 28 } } */
/* { dg-final { scan-assembler-times "vfmadd213sd" 28 } } */
/* { dg-final { scan-assembler-times "vfmsub132sd" 28 } } */
/* { dg-final { scan-assembler-times "vfmsub213sd" 28 } } */
/* { dg-final { scan-assembler-times "vfnmadd132sd" 28 } } */
/* { dg-final { scan-assembler-times "vfnmadd213sd" 28 } } */
/* { dg-final { scan-assembler-times "vfnmsub132sd" 28 } } */
/* { dg-final { scan-assembler-times "vfnmsub213sd" 28 } } */
/* { dg-final { scan-assembler-times "vfmadd\[123\]+sd" 56 } } */
/* { dg-final { scan-assembler-times "vfmsub\[123\]+sd" 56 } } */
/* { dg-final { scan-assembler-times "vfnmadd\[123\]+sd" 56 } } */
/* { dg-final { scan-assembler-times "vfnmsub\[123\]+sd" 56 } } */
gcc/testsuite/gcc.target/i386/l_fma_double_2.c
......@@ -13,7 +13,7 @@ typedef double adouble __attribute__((aligned(sizeof (double))));
/* { dg-final { scan-assembler-times "vfmsub132pd" 8 } } */
/* { dg-final { scan-assembler-times "vfnmadd132pd" 8 } } */
/* { dg-final { scan-assembler-times "vfnmsub132pd" 8 } } */
/* { dg-final { scan-assembler-times "vfmadd132sd" 56 } } */
/* { dg-final { scan-assembler-times "vfmsub132sd" 56 } } */
/* { dg-final { scan-assembler-times "vfnmadd132sd" 56 } } */
/* { dg-final { scan-assembler-times "vfnmsub132sd" 56 } } */
/* { dg-final { scan-assembler-times "vfmadd\[123\]+sd" 56 } } */
/* { dg-final { scan-assembler-times "vfmsub\[123\]+sd" 56 } } */
/* { dg-final { scan-assembler-times "vfnmadd\[123\]+sd" 56 } } */
/* { dg-final { scan-assembler-times "vfnmsub\[123\]+sd" 56 } } */
gcc/testsuite/gcc.target/i386/l_fma_double_3.c
......@@ -17,11 +17,7 @@ typedef double adouble __attribute__((aligned(sizeof (double))));
/* { dg-final { scan-assembler-times "vfnmadd231pd" 4 } } */
/* { dg-final { scan-assembler-times "vfnmsub132pd" 4 } } */
/* { dg-final { scan-assembler-times "vfnmsub231pd" 4 } } */
/* { dg-final { scan-assembler-times "vfmadd132sd" 28 } } */
/* { dg-final { scan-assembler-times "vfmadd213sd" 28 } } */
/* { dg-final { scan-assembler-times "vfmsub132sd" 28 } } */
/* { dg-final { scan-assembler-times "vfmsub213sd" 28 } } */
/* { dg-final { scan-assembler-times "vfnmadd132sd" 28 } } */
/* { dg-final { scan-assembler-times "vfnmadd213sd" 28 } } */
/* { dg-final { scan-assembler-times "vfnmsub132sd" 28 } } */
/* { dg-final { scan-assembler-times "vfnmsub213sd" 28 } } */
/* { dg-final { scan-assembler-times "vfmadd\[123\]+sd" 56 } } */
/* { dg-final { scan-assembler-times "vfmsub\[123\]+sd" 56 } } */
/* { dg-final { scan-assembler-times "vfnmadd\[123\]+sd" 56 } } */
/* { dg-final { scan-assembler-times "vfnmsub\[123\]+sd" 56 } } */
gcc/testsuite/gcc.target/i386/l_fma_double_4.c
......@@ -13,7 +13,7 @@ typedef double adouble __attribute__((aligned(sizeof (double))));
/* { dg-final { scan-assembler-times "vfmsub132pd" 8 } } */
/* { dg-final { scan-assembler-times "vfnmadd132pd" 8 } } */
/* { dg-final { scan-assembler-times "vfnmsub132pd" 8 } } */
/* { dg-final { scan-assembler-times "vfmadd132sd" 56 } } */
/* { dg-final { scan-assembler-times "vfmsub132sd" 56 } } */
/* { dg-final { scan-assembler-times "vfnmadd132sd" 56 } } */
/* { dg-final { scan-assembler-times "vfnmsub132sd" 56 } } */
/* { dg-final { scan-assembler-times "vfmadd\[123\]+sd" 56 } } */
/* { dg-final { scan-assembler-times "vfmsub\[123\]+sd" 56 } } */
/* { dg-final { scan-assembler-times "vfnmadd\[123\]+sd" 56 } } */
/* { dg-final { scan-assembler-times "vfnmsub\[123\]+sd" 56 } } */
gcc/testsuite/gcc.target/i386/l_fma_double_5.c
......@@ -13,7 +13,7 @@ typedef double adouble __attribute__((aligned(sizeof (double))));
/* { dg-final { scan-assembler-times "vfmsub132pd" 8 } } */
/* { dg-final { scan-assembler-times "vfnmadd132pd" 8 } } */
/* { dg-final { scan-assembler-times "vfnmsub132pd" 8 } } */
/* { dg-final { scan-assembler-times "vfmadd132sd" 56 } } */
/* { dg-final { scan-assembler-times "vfmsub132sd" 56 } } */
/* { dg-final { scan-assembler-times "vfnmadd132sd" 56 } } */
/* { dg-final { scan-assembler-times "vfnmsub132sd" 56 } } */
/* { dg-final { scan-assembler-times "vfmadd\[123\]+sd" 56 } } */
/* { dg-final { scan-assembler-times "vfmsub\[123\]+sd" 56 } } */
/* { dg-final { scan-assembler-times "vfnmadd\[123\]+sd" 56 } } */
/* { dg-final { scan-assembler-times "vfnmsub\[123\]+sd" 56 } } */
gcc/testsuite/gcc.target/i386/l_fma_double_6.c
......@@ -13,7 +13,7 @@ typedef double adouble __attribute__((aligned(sizeof (double))));
/* { dg-final { scan-assembler-times "vfmsub132pd" 8 } } */
/* { dg-final { scan-assembler-times "vfnmadd132pd" 8 } } */
/* { dg-final { scan-assembler-times "vfnmsub132pd" 8 } } */
/* { dg-final { scan-assembler-times "vfmadd132sd" 56 } } */
/* { dg-final { scan-assembler-times "vfmsub132sd" 56 } } */
/* { dg-final { scan-assembler-times "vfnmadd132sd" 56 } } */
/* { dg-final { scan-assembler-times "vfnmsub132sd" 56 } } */
/* { dg-final { scan-assembler-times "vfmadd\[123\]+sd" 56 } } */
/* { dg-final { scan-assembler-times "vfmsub\[123\]+sd" 56 } } */
/* { dg-final { scan-assembler-times "vfnmadd\[123\]+sd" 56 } } */
/* { dg-final { scan-assembler-times "vfnmsub\[123\]+sd" 56 } } */
gcc/testsuite/gcc.target/i386/l_fma_float_1.c
......@@ -16,11 +16,7 @@
/* { dg-final { scan-assembler-times "vfnmadd231ps" 4 } } */
/* { dg-final { scan-assembler-times "vfnmsub132ps" 4 } } */
/* { dg-final { scan-assembler-times "vfnmsub231ps" 4 } } */
/* { dg-final { scan-assembler-times "vfmadd132ss" 60 } } */
/* { dg-final { scan-assembler-times "vfmadd213ss" 60 } } */
/* { dg-final { scan-assembler-times "vfmsub132ss" 60 } } */
/* { dg-final { scan-assembler-times "vfmsub213ss" 60 } } */
/* { dg-final { scan-assembler-times "vfnmadd132ss" 60 } } */
/* { dg-final { scan-assembler-times "vfnmadd213ss" 60 } } */
/* { dg-final { scan-assembler-times "vfnmsub132ss" 60 } } */
/* { dg-final { scan-assembler-times "vfnmsub213ss" 60 } } */
/* { dg-final { scan-assembler-times "vfmadd\[123\]+ss" 120 } } */
/* { dg-final { scan-assembler-times "vfmsub\[123\]+ss" 120 } } */
/* { dg-final { scan-assembler-times "vfnmadd\[123\]+ss" 120 } } */
/* { dg-final { scan-assembler-times "vfnmsub\[123\]+ss" 120 } } */
gcc/testsuite/gcc.target/i386/l_fma_float_2.c
......@@ -12,7 +12,7 @@
/* { dg-final { scan-assembler-times "vfmsub132ps" 8 } } */
/* { dg-final { scan-assembler-times "vfnmadd132ps" 8 } } */
/* { dg-final { scan-assembler-times "vfnmsub132ps" 8 } } */
/* { dg-final { scan-assembler-times "vfmadd132ss" 120 } } */
/* { dg-final { scan-assembler-times "vfmsub132ss" 120 } } */
/* { dg-final { scan-assembler-times "vfnmadd132ss" 120 } } */
/* { dg-final { scan-assembler-times "vfnmsub132ss" 120 } } */
/* { dg-final { scan-assembler-times "vfmadd\[123\]+ss" 120 } } */
/* { dg-final { scan-assembler-times "vfmsub\[123\]+ss" 120 } } */
/* { dg-final { scan-assembler-times "vfnmadd\[123\]+ss" 120 } } */
/* { dg-final { scan-assembler-times "vfnmsub\[123\]+ss" 120 } } */
gcc/testsuite/gcc.target/i386/l_fma_float_3.c
......@@ -16,11 +16,7 @@
/* { dg-final { scan-assembler-times "vfnmadd231ps" 4 } } */
/* { dg-final { scan-assembler-times "vfnmsub132ps" 4 } } */
/* { dg-final { scan-assembler-times "vfnmsub231ps" 4 } } */
/* { dg-final { scan-assembler-times "vfmadd132ss" 60 } } */
/* { dg-final { scan-assembler-times "vfmadd213ss" 60 } } */
/* { dg-final { scan-assembler-times "vfmsub132ss" 60 } } */
/* { dg-final { scan-assembler-times "vfmsub213ss" 60 } } */
/* { dg-final { scan-assembler-times "vfnmadd132ss" 60 } } */
/* { dg-final { scan-assembler-times "vfnmadd213ss" 60 } } */
/* { dg-final { scan-assembler-times "vfnmsub132ss" 60 } } */
/* { dg-final { scan-assembler-times "vfnmsub213ss" 60 } } */
/* { dg-final { scan-assembler-times "vfmadd\[123\]+ss" 120 } } */
/* { dg-final { scan-assembler-times "vfmsub\[123\]+ss" 120 } } */
/* { dg-final { scan-assembler-times "vfnmadd\[123\]+ss" 120 } } */
/* { dg-final { scan-assembler-times "vfnmsub\[123\]+ss" 120 } } */
gcc/testsuite/gcc.target/i386/l_fma_float_4.c
......@@ -12,7 +12,7 @@
/* { dg-final { scan-assembler-times "vfmsub132ps" 8 } } */
/* { dg-final { scan-assembler-times "vfnmadd132ps" 8 } } */
/* { dg-final { scan-assembler-times "vfnmsub132ps" 8 } } */
/* { dg-final { scan-assembler-times "vfmadd132ss" 120 } } */
/* { dg-final { scan-assembler-times "vfmsub132ss" 120 } } */
/* { dg-final { scan-assembler-times "vfnmadd132ss" 120 } } */
/* { dg-final { scan-assembler-times "vfnmsub132ss" 120 } } */
/* { dg-final { scan-assembler-times "vfmadd\[123\]+ss" 120 } } */
/* { dg-final { scan-assembler-times "vfmsub\[123\]+ss" 120 } } */
/* { dg-final { scan-assembler-times "vfnmadd\[123\]+ss" 120 } } */
/* { dg-final { scan-assembler-times "vfnmsub\[123\]+ss" 120 } } */
gcc/testsuite/gcc.target/i386/l_fma_float_5.c
......@@ -12,7 +12,7 @@
/* { dg-final { scan-assembler-times "vfmsub132ps" 8 } } */
/* { dg-final { scan-assembler-times "vfnmadd132ps" 8 } } */
/* { dg-final { scan-assembler-times "vfnmsub132ps" 8 } } */
/* { dg-final { scan-assembler-times "vfmadd132ss" 120 } } */
/* { dg-final { scan-assembler-times "vfmsub132ss" 120 } } */
/* { dg-final { scan-assembler-times "vfnmadd132ss" 120 } } */
/* { dg-final { scan-assembler-times "vfnmsub132ss" 120 } } */
/* { dg-final { scan-assembler-times "vfmadd\[123\]+ss" 120 } } */
/* { dg-final { scan-assembler-times "vfmsub\[123\]+ss" 120 } } */
/* { dg-final { scan-assembler-times "vfnmadd\[123\]+ss" 120 } } */
/* { dg-final { scan-assembler-times "vfnmsub\[123\]+ss" 120 } } */
gcc/testsuite/gcc.target/i386/l_fma_float_6.c
......@@ -12,7 +12,7 @@
/* { dg-final { scan-assembler-times "vfmsub132ps" 8 } } */
/* { dg-final { scan-assembler-times "vfnmadd132ps" 8 } } */
/* { dg-final { scan-assembler-times "vfnmsub132ps" 8 } } */
/* { dg-final { scan-assembler-times "vfmadd132ss" 120 } } */
/* { dg-final { scan-assembler-times "vfmsub132ss" 120 } } */
/* { dg-final { scan-assembler-times "vfnmadd132ss" 120 } } */
/* { dg-final { scan-assembler-times "vfnmsub132ss" 120 } } */
/* { dg-final { scan-assembler-times "vfmadd\[123\]+ss" 120 } } */
/* { dg-final { scan-assembler-times "vfmsub\[123\]+ss" 120 } } */
/* { dg-final { scan-assembler-times "vfnmadd\[123\]+ss" 120 } } */
/* { dg-final { scan-assembler-times "vfnmsub\[123\]+ss" 120 } } */
gcc/timevar.def
......@@ -221,7 +221,6 @@ DEFTIMEVAR (TV_CSE2 , "CSE 2")
DEFTIMEVAR (TV_BRANCH_PROB , "branch prediction")
DEFTIMEVAR (TV_COMBINE , "combiner")
DEFTIMEVAR (TV_IFCVT , "if-conversion")
DEFTIMEVAR (TV_REGMOVE , "regmove")
DEFTIMEVAR (TV_MODE_SWITCH , "mode switching")
DEFTIMEVAR (TV_SMS , "sms modulo scheduling")
DEFTIMEVAR (TV_SCHED , "scheduling")
......
gcc/tree-pass.h
......@@ -524,7 +524,6 @@ extern rtl_opt_pass *make_pass_if_after_combine (gcc::context *ctxt);
extern rtl_opt_pass *make_pass_ree (gcc::context *ctxt);
extern rtl_opt_pass *make_pass_partition_blocks (gcc::context *ctxt);
extern rtl_opt_pass *make_pass_match_asm_constraints (gcc::context *ctxt);
extern rtl_opt_pass *make_pass_regmove (gcc::context *ctxt);
extern rtl_opt_pass *make_pass_split_all_insns (gcc::context *ctxt);
extern rtl_opt_pass *make_pass_fast_rtl_byte_dce (gcc::context *ctxt);
extern rtl_opt_pass *make_pass_lower_subreg2 (gcc::context *ctxt);
......
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