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riscv-gcc-1
Commit 3b684012 by Richard Earnshaw Committed by Richard Earnshaw
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* arm.c (fpa_rhs_operand, fpa_add_operand, const_double_rtx_ok_for_fpa) 

(neg_const_double_ok_for_fpa, output_mov_long_double_fpa_from_arm)
(output_mov_long_double_arm_from_fpa, output_mov_double_fpa_from_arm)
(output_mov_double_arm_from_fpa): Renamed to use fpa instead of fpu.
All callers changed.
* arm.md, arm.h, arm-protos.h: Updated.

* arm.h (enum reg_class FPA_REGS): Renamed from FPU_REGS.
(CLASS_MAX_NREGS, REGISTER_MOVE_COST, REG_CLASS_FROM_LETTER): Updated.
* arm.c (arm_regno_class, f_register_operand): Updated.

From-SVN: r63996
parent fa5848c7
Showing with 71 additions and 58 deletions
gcc/ChangeLog
2003-03-08 Richard Earnshaw <rearnsha@arm.com>
* arm.c (fpa_rhs_operand, fpa_add_operand, const_double_rtx_ok_for_fpa)
(neg_const_double_ok_for_fpa, output_mov_long_double_fpa_from_arm)
(output_mov_long_double_arm_from_fpa, output_mov_double_fpa_from_arm)
(output_mov_double_arm_from_fpa): Renamed to use fpa instead of fpu.
All callers changed.
* arm.md, arm.h, arm-protos.h: Updated.
* arm.h (enum reg_class FPA_REGS): Renamed from FPU_REGS.
(CLASS_MAX_NREGS, REGISTER_MOVE_COST, REG_CLASS_FROM_LETTER): Updated.
* arm.c (arm_regno_class, f_register_operand): Updated.
2003-03-08 Hans-Peter Nilsson <hp@bitrange.com>
* config/cris/cris.h: Remove EGCS references.
......
gcc/config/arm/arm-protos.h
......@@ -58,8 +58,8 @@ extern int thumb_legitimate_address_p PARAMS ((enum machine_mode, rtx,
extern int thumb_legitimate_offset_p PARAMS ((enum machine_mode,
HOST_WIDE_INT));
extern rtx arm_legitimize_address PARAMS ((rtx, rtx, enum machine_mode));
extern int const_double_rtx_ok_for_fpu PARAMS ((rtx));
extern int neg_const_double_rtx_ok_for_fpu PARAMS ((rtx));
extern int const_double_rtx_ok_for_fpa PARAMS ((rtx));
extern int neg_const_double_rtx_ok_for_fpa PARAMS ((rtx));
/* Predicates. */
extern int s_register_operand PARAMS ((rtx, enum machine_mode));
......@@ -74,8 +74,8 @@ extern int arm_not_operand PARAMS ((rtx, enum machine_mode));
extern int offsettable_memory_operand PARAMS ((rtx, enum machine_mode));
extern int alignable_memory_operand PARAMS ((rtx, enum machine_mode));
extern int bad_signed_byte_operand PARAMS ((rtx, enum machine_mode));
extern int fpu_rhs_operand PARAMS ((rtx, enum machine_mode));
extern int fpu_add_operand PARAMS ((rtx, enum machine_mode));
extern int fpa_rhs_operand PARAMS ((rtx, enum machine_mode));
extern int fpa_add_operand PARAMS ((rtx, enum machine_mode));
extern int power_of_two_operand PARAMS ((rtx, enum machine_mode));
extern int nonimmediate_di_operand PARAMS ((rtx, enum machine_mode));
extern int di_operand PARAMS ((rtx, enum machine_mode));
......@@ -125,11 +125,11 @@ extern void arm_reorg PARAMS ((rtx));
extern const char * fp_immediate_constant PARAMS ((rtx));
extern const char * output_call PARAMS ((rtx *));
extern const char * output_call_mem PARAMS ((rtx *));
extern const char * output_mov_long_double_fpu_from_arm PARAMS ((rtx *));
extern const char * output_mov_long_double_arm_from_fpu PARAMS ((rtx *));
extern const char * output_mov_long_double_fpa_from_arm PARAMS ((rtx *));
extern const char * output_mov_long_double_arm_from_fpa PARAMS ((rtx *));
extern const char * output_mov_long_double_arm_from_arm PARAMS ((rtx *));
extern const char * output_mov_double_fpu_from_arm PARAMS ((rtx *));
extern const char * output_mov_double_arm_from_fpu PARAMS ((rtx *));
extern const char * output_mov_double_fpa_from_arm PARAMS ((rtx *));
extern const char * output_mov_double_arm_from_fpa PARAMS ((rtx *));
extern const char * output_move_double PARAMS ((rtx *));
extern const char * output_mov_immediate PARAMS ((rtx *));
extern const char * output_add_immediate PARAMS ((rtx *));
......
gcc/config/arm/arm.c
......@@ -387,7 +387,7 @@ static const struct processors all_cores[] =
{"arm710c", FL_MODE26 | FL_MODE32 },
{"arm7100", FL_MODE26 | FL_MODE32 },
{"arm7500", FL_MODE26 | FL_MODE32 },
/* Doesn't have an external co-proc, but does have embedded fpu. */
/* Doesn't have an external co-proc, but does have embedded fpa. */
{"arm7500fe", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
{"arm7tdmi", FL_CO_PROC | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB },
{"arm8", FL_MODE26 | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED },
......@@ -1008,7 +1008,7 @@ use_return_insn (iscond)
if (saved_int_regs && !(saved_int_regs & (1 << LR_REGNUM)))
return 0;
/* Can't be done if any of the FPU regs are pushed,
/* Can't be done if any of the FPA regs are pushed,
since this also requires an insn. */
if (TARGET_HARD_FLOAT)
for (regno = FIRST_ARM_FP_REGNUM; regno <= LAST_ARM_FP_REGNUM; regno++)
......@@ -3216,11 +3216,11 @@ arm_rtx_costs_1 (x, code, outer)
if (GET_MODE_CLASS (mode) == MODE_FLOAT)
return (2 + ((REG_OR_SUBREG_REG (XEXP (x, 1))
|| (GET_CODE (XEXP (x, 1)) == CONST_DOUBLE
&& const_double_rtx_ok_for_fpu (XEXP (x, 1))))
&& const_double_rtx_ok_for_fpa (XEXP (x, 1))))
? 0 : 8)
+ ((REG_OR_SUBREG_REG (XEXP (x, 0))
|| (GET_CODE (XEXP (x, 0)) == CONST_DOUBLE
&& const_double_rtx_ok_for_fpu (XEXP (x, 0))))
&& const_double_rtx_ok_for_fpa (XEXP (x, 0))))
? 0 : 8));
if (((GET_CODE (XEXP (x, 0)) == CONST_INT
......@@ -3245,7 +3245,7 @@ arm_rtx_costs_1 (x, code, outer)
return (2 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 8)
+ ((REG_OR_SUBREG_REG (XEXP (x, 1))
|| (GET_CODE (XEXP (x, 1)) == CONST_DOUBLE
&& const_double_rtx_ok_for_fpu (XEXP (x, 1))))
&& const_double_rtx_ok_for_fpa (XEXP (x, 1))))
? 0 : 8));
/* Fall through */
......@@ -3405,10 +3405,10 @@ arm_rtx_costs_1 (x, code, outer)
return 6;
case CONST_DOUBLE:
if (const_double_rtx_ok_for_fpu (x))
if (const_double_rtx_ok_for_fpa (x))
return outer == SET ? 2 : -1;
else if ((outer == COMPARE || outer == PLUS)
&& neg_const_double_rtx_ok_for_fpu (x))
&& neg_const_double_rtx_ok_for_fpa (x))
return -1;
return 7;
......@@ -3569,10 +3569,10 @@ init_fpa_table ()
fpa_consts_inited = 1;
}
/* Return TRUE if rtx X is a valid immediate FPU constant. */
/* Return TRUE if rtx X is a valid immediate FPA constant. */
int
const_double_rtx_ok_for_fpu (x)
const_double_rtx_ok_for_fpa (x)
rtx x;
{
REAL_VALUE_TYPE r;
......@@ -3592,10 +3592,10 @@ const_double_rtx_ok_for_fpu (x)
return 0;
}
/* Return TRUE if rtx X is a valid immediate FPU constant. */
/* Return TRUE if rtx X is a valid immediate FPA constant. */
int
neg_const_double_rtx_ok_for_fpu (x)
neg_const_double_rtx_ok_for_fpa (x)
rtx x;
{
REAL_VALUE_TYPE r;
......@@ -3851,13 +3851,13 @@ f_register_operand (op, mode)
to be a register operand. */
return (GET_CODE (op) == REG
&& (REGNO (op) >= FIRST_PSEUDO_REGISTER
|| REGNO_REG_CLASS (REGNO (op)) == FPU_REGS));
|| REGNO_REG_CLASS (REGNO (op)) == FPA_REGS));
}
/* Return TRUE for valid operands for the rhs of an FPU instruction. */
/* Return TRUE for valid operands for the rhs of an FPA instruction. */
int
fpu_rhs_operand (op, mode)
fpa_rhs_operand (op, mode)
rtx op;
enum machine_mode mode;
{
......@@ -3868,13 +3868,13 @@ fpu_rhs_operand (op, mode)
return FALSE;
if (GET_CODE (op) == CONST_DOUBLE)
return const_double_rtx_ok_for_fpu (op);
return const_double_rtx_ok_for_fpa (op);
return FALSE;
}
int
fpu_add_operand (op, mode)
fpa_add_operand (op, mode)
rtx op;
enum machine_mode mode;
{
......@@ -3885,8 +3885,8 @@ fpu_add_operand (op, mode)
return FALSE;
if (GET_CODE (op) == CONST_DOUBLE)
return (const_double_rtx_ok_for_fpu (op)
|| neg_const_double_rtx_ok_for_fpu (op));
return (const_double_rtx_ok_for_fpa (op)
|| neg_const_double_rtx_ok_for_fpa (op));
return FALSE;
}
......@@ -7292,12 +7292,12 @@ output_call_mem (operands)
}
/* Output a move from arm registers to an fpu registers.
OPERANDS[0] is an fpu register.
/* Output a move from arm registers to an fpa registers.
OPERANDS[0] is an fpa register.
OPERANDS[1] is the first registers of an arm register pair. */
const char *
output_mov_long_double_fpu_from_arm (operands)
output_mov_long_double_fpa_from_arm (operands)
rtx * operands;
{
int arm_reg0 = REGNO (operands[1]);
......@@ -7316,12 +7316,12 @@ output_mov_long_double_fpu_from_arm (operands)
return "";
}
/* Output a move from an fpu register to arm registers.
/* Output a move from an fpa register to arm registers.
OPERANDS[0] is the first registers of an arm register pair.
OPERANDS[1] is an fpu register. */
OPERANDS[1] is an fpa register. */
const char *
output_mov_long_double_arm_from_fpu (operands)
output_mov_long_double_arm_from_fpa (operands)
rtx * operands;
{
int arm_reg0 = REGNO (operands[0]);
......@@ -7376,12 +7376,12 @@ output_mov_long_double_arm_from_arm (operands)
}
/* Output a move from arm registers to an fpu registers.
OPERANDS[0] is an fpu register.
/* Output a move from arm registers to an fpa registers.
OPERANDS[0] is an fpa register.
OPERANDS[1] is the first registers of an arm register pair. */
const char *
output_mov_double_fpu_from_arm (operands)
output_mov_double_fpa_from_arm (operands)
rtx * operands;
{
int arm_reg0 = REGNO (operands[1]);
......@@ -7397,12 +7397,12 @@ output_mov_double_fpu_from_arm (operands)
return "";
}
/* Output a move from an fpu register to arm registers.
/* Output a move from an fpa register to arm registers.
OPERANDS[0] is the first registers of an arm register pair.
OPERANDS[1] is an fpu register. */
OPERANDS[1] is an fpa register. */
const char *
output_mov_double_arm_from_fpu (operands)
output_mov_double_arm_from_fpa (operands)
rtx * operands;
{
int arm_reg0 = REGNO (operands[0]);
......@@ -10243,7 +10243,7 @@ arm_hard_regno_mode_ok (regno, mode)
/* We only allow integers in the fake hard registers. */
return GET_MODE_CLASS (mode) == MODE_INT;
/* The only registers left are the FPU registers
/* The only registers left are the FPA registers
which we only allow to hold FP values. */
return GET_MODE_CLASS (mode) == MODE_FLOAT
&& regno >= FIRST_ARM_FP_REGNUM
......@@ -10276,7 +10276,7 @@ arm_regno_class (regno)
if (IS_CIRRUS_REGNUM (regno))
return CIRRUS_REGS;
return FPU_REGS;
return FPA_REGS;
}
/* Handle a special case when computing the offset
......
gcc/config/arm/arm.h
......@@ -1002,7 +1002,7 @@ extern const char * structure_size_string;
#define IS_CIRRUS_REGNUM(REGNUM) \
(((REGNUM) >= FIRST_CIRRUS_FP_REGNUM) && ((REGNUM) <= LAST_CIRRUS_FP_REGNUM))
/* The number of hard registers is 16 ARM + 8 FPU + 1 CC + 1 SFP. */
/* The number of hard registers is 16 ARM + 8 FPA + 1 CC + 1 SFP. */
/* Cirrus registers take us up to 43... */
#define FIRST_PSEUDO_REGISTER 43
......@@ -1021,7 +1021,7 @@ extern const char * structure_size_string;
This is ordinarily the length in words of a value of mode MODE
but can be less for certain modes in special long registers.
On the ARM regs are UNITS_PER_WORD bits wide; FPU regs can hold any FP
On the ARM regs are UNITS_PER_WORD bits wide; FPA regs can hold any FP
mode. */
#define HARD_REGNO_NREGS(REGNO, MODE) \
((TARGET_ARM \
......@@ -1066,12 +1066,12 @@ extern const char * structure_size_string;
/* Register and constant classes. */
/* Register classes: used to be simple, just all ARM regs or all FPU regs
/* Register classes: used to be simple, just all ARM regs or all FPA regs
Now that the Thumb is involved it has become more complicated. */
enum reg_class
{
NO_REGS,
FPU_REGS,
FPA_REGS,
CIRRUS_REGS,
LO_REGS,
STACK_REG,
......@@ -1089,7 +1089,7 @@ enum reg_class
#define REG_CLASS_NAMES \
{ \
"NO_REGS", \
"FPU_REGS", \
"FPA_REGS", \
"CIRRUS_REGS", \
"LO_REGS", \
"STACK_REG", \
......@@ -1106,7 +1106,7 @@ enum reg_class
#define REG_CLASS_CONTENTS \
{ \
{ 0x00000000, 0x0 }, /* NO_REGS */ \
{ 0x00FF0000, 0x0 }, /* FPU_REGS */ \
{ 0x00FF0000, 0x0 }, /* FPA_REGS */ \
{ 0xF8000000, 0x000007FF }, /* CIRRUS_REGS */ \
{ 0x000000FF, 0x0 }, /* LO_REGS */ \
{ 0x00002000, 0x0 }, /* STACK_REG */ \
......@@ -1143,10 +1143,10 @@ enum reg_class
#define SMALL_REGISTER_CLASSES TARGET_THUMB
/* Get reg_class from a letter such as appears in the machine description.
We only need constraint `f' for FPU_REGS (`r' == GENERAL_REGS) for the
We only need constraint `f' for FPA_REGS (`r' == GENERAL_REGS) for the
ARM, but several more letters for the Thumb. */
#define REG_CLASS_FROM_LETTER(C) \
( (C) == 'f' ? FPU_REGS \
( (C) == 'f' ? FPA_REGS \
: (C) == 'v' ? CIRRUS_REGS \
: (C) == 'l' ? (TARGET_ARM ? GENERAL_REGS : LO_REGS) \
: TARGET_ARM ? NO_REGS \
......@@ -1190,11 +1190,11 @@ enum reg_class
(TARGET_ARM ? \
CONST_OK_FOR_ARM_LETTER (VALUE, C) : CONST_OK_FOR_THUMB_LETTER (VALUE, C))
/* Constant letter 'G' for the FPU immediate constants.
/* Constant letter 'G' for the FPA immediate constants.
'H' means the same constant negated. */
#define CONST_DOUBLE_OK_FOR_ARM_LETTER(X, C) \
((C) == 'G' ? const_double_rtx_ok_for_fpu (X) : \
(C) == 'H' ? neg_const_double_rtx_ok_for_fpu (X) : 0)
((C) == 'G' ? const_double_rtx_ok_for_fpa (X) : \
(C) == 'H' ? neg_const_double_rtx_ok_for_fpa (X) : 0)
#define CONST_DOUBLE_OK_FOR_LETTER_P(X, C) \
(TARGET_ARM ? \
......@@ -1364,18 +1364,18 @@ enum reg_class
/* Return the maximum number of consecutive registers
needed to represent mode MODE in a register of class CLASS.
ARM regs are UNITS_PER_WORD bits while FPU regs can hold any FP mode */
ARM regs are UNITS_PER_WORD bits while FPA regs can hold any FP mode */
#define CLASS_MAX_NREGS(CLASS, MODE) \
(((CLASS) == FPU_REGS || (CLASS) == CIRRUS_REGS) ? 1 : ARM_NUM_REGS (MODE))
(((CLASS) == FPA_REGS || (CLASS) == CIRRUS_REGS) ? 1 : ARM_NUM_REGS (MODE))
/* If defined, gives a class of registers that cannot be used as the
operand of a SUBREG that changes the mode of the object illegally. */
/* Moves between FPU_REGS and GENERAL_REGS are two memory insns. */
/* Moves between FPA_REGS and GENERAL_REGS are two memory insns. */
#define REGISTER_MOVE_COST(MODE, FROM, TO) \
(TARGET_ARM ? \
((FROM) == FPU_REGS && (TO) != FPU_REGS ? 20 : \
(FROM) != FPU_REGS && (TO) == FPU_REGS ? 20 : \
((FROM) == FPA_REGS && (TO) != FPA_REGS ? 20 : \
(FROM) != FPA_REGS && (TO) == FPA_REGS ? 20 : \
(FROM) == CIRRUS_REGS && (TO) != CIRRUS_REGS ? 20 : \
(FROM) != CIRRUS_REGS && (TO) == CIRRUS_REGS ? 20 : \
2) \
......@@ -2508,8 +2508,8 @@ extern int making_const_table;
{"arm_hard_register_operand", {REG}}, \
{"f_register_operand", {SUBREG, REG}}, \
{"arm_add_operand", {SUBREG, REG, CONST_INT}}, \
{"fpu_add_operand", {SUBREG, REG, CONST_DOUBLE}}, \
{"fpu_rhs_operand", {SUBREG, REG, CONST_DOUBLE}}, \
{"fpa_add_operand", {SUBREG, REG, CONST_DOUBLE}}, \
{"fpa_rhs_operand", {SUBREG, REG, CONST_DOUBLE}}, \
{"arm_rhs_operand", {SUBREG, REG, CONST_INT}}, \
{"arm_not_operand", {SUBREG, REG, CONST_INT}}, \
{"reg_or_int_operand", {SUBREG, REG, CONST_INT}}, \
......
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