[AARCH64] Enable support for TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES.

gcc/

	* config/aarch64/aarch64.c
	(aarch64_autovectorize_vector_sizes): New.
	(TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES): Define.

gcc/testsuite/

	* lib/target-supports.exp
	(check_effective_target_vect_multiple_sizes): Enable for AArch64.


Co-Authored-By: Tejas Belagod <tejas.belagod@arm.com>

From-SVN: r194552

gcc/ChangeLog

+2012-12-17  James Greenhalgh  <james.greenhalgh@arm.com>
+	    Tejas Belagod  <tejas.belagod@arm.com>
+
+	* config/aarch64/aarch64.c
+	(aarch64_autovectorize_vector_sizes): New.
+	(TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES): Define.
+
 2012-12-16  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 
 	PR middle-end/55709

gcc/config/aarch64/aarch64.c

@@ -5865,6 +5865,14 @@ aarch64_preferred_simd_mode (enum machine_mode mode)
   return word_mode;
 }
 
+/* Return the bitmask of possible vector sizes for the vectorizer
+   to iterate over.  */
+static unsigned int
+aarch64_autovectorize_vector_sizes (void)
+{
+  return (16 | 8);
+}
+
 /* A table to help perform AArch64-specific name mangling for AdvSIMD
    vector types in order to conform to the AAPCS64 (see "Procedure
    Call Standard for the ARM 64-bit Architecture", Appendix A).  To
@@ -7519,6 +7527,10 @@ aarch64_vectorize_vec_perm_const_ok (enum machine_mode vmode,
 #define TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION \
   aarch64_builtin_vectorized_function
 
+#undef TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES
+#define TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES \
+  aarch64_autovectorize_vector_sizes
+
 /* Section anchor support.  */
 
 #undef TARGET_MIN_ANCHOR_OFFSET

gcc/testsuite/ChangeLog

+2012-12-17  James Greenhalgh  <james.greenhalgh@arm.com>
+	    Tejas Belagod  <tejas.belagod@arm.com>
+
+	* lib/target-supports.exp
+	(check_effective_target_vect_multiple_sizes): Enable for AArch64.
+
 2012-12-16  Tobias Burnus  <burnus@net-b.de>
 
 	PR fortran/55197

gcc/testsuite/lib/target-supports.exp

@@ -3891,7 +3891,8 @@ proc check_effective_target_vect_multiple_sizes { } {
     global et_vect_multiple_sizes_saved
 
     set et_vect_multiple_sizes_saved 0
-    if { ([istarget arm*-*-*] && [check_effective_target_arm_neon_ok]) } {
+    if { ([istarget aarch64*-*-*]
+	  || ([istarget arm*-*-*] && [check_effective_target_arm_neon_ok])) } {
        set et_vect_multiple_sizes_saved 1
     }
     if { ([istarget x86_64-*-*] || [istarget i?86-*-*]) } {