init_1.c: Remove options -O2 -fno-schedule-insns and instead pass -O.

2019-06-08  Prathamesh Kulkarni  <prathamesh.kulkarni@linaro.org>

	* gcc.target/aarch64/sve/init_1.c: Remove options
	-O2 -fno-schedule-insns and instead pass -O.
	Update assembly in comments. 
	* gcc.target/aarch64/sve/init_2.c: Likewise.
	* gcc.target/aarch64/sve/init_3.c: Likewise.
	* gcc.target/aarch64/sve/init_4.c: Likewise.
	* gcc.target/aarch64/sve/init_5.c: Likewise and additionally
	adjust dg-scan.
	* gcc.target/aarch64/sve/init_6.c: Likewise.
	* gcc.target/aarch64/sve/init_7.c: Likewise.
	* gcc.target/aarch64/sve/init_8.c: Likewise.
	* gcc.target/aarch64/sve/init_9.c: Likewise.
	* gcc.target/aarch64/sve/init_10.c: Likewise.
	* gcc.target/aarch64/sve/init_11.c: Likewise.
	* gcc.target/aarch64/sve/init_12.c: Likewise.

From-SVN: r272073

gcc/testsuite/ChangeLog

+2019-06-08  Prathamesh Kulkarni  <prathamesh.kulkarni@linaro.org>
+
+	* gcc.target/aarch64/sve/init_1.c: Remove options
+	-O2 -fno-schedule-insns and instead pass -O.
+	Update assembly in comments. 
+	* gcc.target/aarch64/sve/init_2.c: Likewise.
+	* gcc.target/aarch64/sve/init_3.c: Likewise.
+	* gcc.target/aarch64/sve/init_4.c: Likewise.
+	* gcc.target/aarch64/sve/init_5.c: Likewise and additionally
+	adjust dg-scan.
+	* gcc.target/aarch64/sve/init_6.c: Likewise.
+	* gcc.target/aarch64/sve/init_7.c: Likewise.
+	* gcc.target/aarch64/sve/init_8.c: Likewise.
+	* gcc.target/aarch64/sve/init_9.c: Likewise.
+	* gcc.target/aarch64/sve/init_10.c: Likewise.
+	* gcc.target/aarch64/sve/init_11.c: Likewise.
+	* gcc.target/aarch64/sve/init_12.c: Likewise.
+
 2019-06-07  Marek Polacek  <polacek@redhat.com>
 
 	PR c++/77747

gcc/testsuite/gcc.target/aarch64/sve/init_1.c

 /* { dg-do assemble { target aarch64_asm_sve_ok } } */
-/* { dg-options "-O2 -fno-schedule-insns -msve-vector-bits=256 --save-temps" } */
+/* { dg-options "-O -msve-vector-bits=256 --save-temps" } */
 
 /* Case 1.1: Trailing constants with stepped sequence.  */
 
@@ -17,7 +17,6 @@ vnx4si foo(int a, int b)
 foo:
 .LFB0:
         .cfi_startproc
-        ptrue   p0.s, vl8
         index   z0.s, #1, #1
         insr    z0.s, w1
         insr    z0.s, w0

gcc/testsuite/gcc.target/aarch64/sve/init_10.c

 /* { dg-do assemble { target aarch64_asm_sve_ok } } */
-/* { dg-options "-O2 -fno-schedule-insns -msve-vector-bits=256 --save-temps" } */
+/* { dg-options "-O -msve-vector-bits=256 --save-temps" } */
 
 /* Case 5.4: Interleaved repeating elements and non-repeating elements.  */
 
@@ -17,13 +17,12 @@ vnx4si foo(int a, int b, int c, int f)
 foo:
 .LFB0:
         .cfi_startproc
-        mov     z0.s, w2
         mov     z1.s, w3
+        mov     z0.s, w2
         insr    z0.s, w1
-        ptrue   p0.s, vl8
         insr    z0.s, w0
         zip1    z0.s, z0.s, z1.s
         ret
 */
 
-/* { dg-final { scan-assembler {\tmov\t(z[0-9]+\.s), w3\n\tmov\t(z[0-9]+\.s), w2\n.*\n\tinsr\t\2, w1\n\tinsr\t\2, w0\n\tzip1\t\2, \2, \1} } } */
+/* { dg-final { scan-assembler {\tmov\t(z[0-9]+\.s), w3\n\tmov\t(z[0-9]+\.s), w2\n\tinsr\t\2, w1\n\tinsr\t\2, w0\n\tzip1\t\2, \2, \1} } } */

gcc/testsuite/gcc.target/aarch64/sve/init_11.c

 /* { dg-do assemble { target aarch64_asm_sve_ok } } */
-/* { dg-options "-O2 -fno-schedule-insns -msve-vector-bits=256 --save-temps" } */
+/* { dg-options "-O -msve-vector-bits=256 --save-temps" } */
 
 /* Case 5.5: Interleaved repeating elements and trailing same elements.  */
 
@@ -18,11 +18,10 @@ foo:
 .LFB0:
         .cfi_startproc
         mov     z0.s, w1
-        mov     z1.s, w2
         insr    z0.s, w0
-        ptrue   p0.s, vl8
+        mov     z1.s, w2
         zip1    z0.s, z0.s, z1.s
         ret
 */
 
-/* { dg-final { scan-assembler {\tmov\t(z[0-9]+\.s), w1\n\tmov\t(z[0-9]+\.s), w2\n\tinsr\t\1, w0\n.*\tzip1\t\1, \1, \2} } } */
+/* { dg-final { scan-assembler {\tmov\t(z[0-9]+\.s), w1\n\tinsr\t\1, w0\n\tmov\t(z[0-9]+\.s), w2\n\tzip1\t\1, \1, \2} } } */

gcc/testsuite/gcc.target/aarch64/sve/init_12.c

 /* { dg-do assemble { target aarch64_asm_sve_ok } } */
-/* { dg-options "-O2 -fno-schedule-insns -msve-vector-bits=256 --save-temps" } */
+/* { dg-options "-O -msve-vector-bits=256 --save-temps" } */
 
 /* Case 5.5: Interleaved repeating elements and trailing same elements.  */
 
@@ -17,14 +17,13 @@ vnx4si foo(int a, int b, int f)
 foo:
 .LFB0:
         .cfi_startproc
-        mov     z0.s, w0
         mov     z1.s, w2
+        mov     z0.s, w0
         insr    z0.s, w1
-        ptrue   p0.s, vl8
         insr    z0.s, w1
         insr    z0.s, w1
         zip1    z0.s, z0.s, z1.s
         ret
 */
 
-/* { dg-final { scan-assembler {\tmov\t(z[0-9]+\.s), w2\n\tmov\t(z[0-9]+\.s), w0\n.*\n\tinsr\t\2, w1\n\tinsr\t\2, w1\n\tinsr\t\2, w1\n\tzip1\t\2, \2, \1} } } */
+/* { dg-final { scan-assembler {\tmov\t(z[0-9]+\.s), w2\n\tmov\t(z[0-9]+\.s), w0\n\tinsr\t\2, w1\n\tinsr\t\2, w1\n\tinsr\t\2, w1\n\tzip1\t\2, \2, \1} } } */

gcc/testsuite/gcc.target/aarch64/sve/init_2.c

 /* { dg-do assemble { target aarch64_asm_sve_ok } } */
-/* { dg-options "-O2 -fno-schedule-insns -msve-vector-bits=256 --save-temps" } */
+/* { dg-options "-O -msve-vector-bits=256 --save-temps" } */
 
 /* Case 1.2: Trailing constants with repeating sequence.  */
 

gcc/testsuite/gcc.target/aarch64/sve/init_3.c

 /* { dg-do assemble { target aarch64_asm_sve_ok } } */
-/* { dg-options "-O2 -fno-schedule-insns -msve-vector-bits=256 --save-temps" } */
+/* { dg-options "-O -msve-vector-bits=256 --save-temps" } */
 
 /* Case 2.1: Leading constants with stepped sequence.  */
 
@@ -17,7 +17,6 @@ vnx4si foo(int a, int b)
 foo:
 .LFB0:
         .cfi_startproc
-        ptrue   p0.s, vl8
         index   z0.s, #6, #-1
         insr    z0.s, w0
         insr    z0.s, w1

gcc/testsuite/gcc.target/aarch64/sve/init_4.c

 /* { dg-do assemble { target aarch64_asm_sve_ok } } */
-/* { dg-options "-O2 -fno-schedule-insns -msve-vector-bits=256 --save-temps" } */
+/* { dg-options "-O -msve-vector-bits=256 --save-temps" } */
 
 /* Case 2.2: Leading constants with stepped sequence.  */
 

gcc/testsuite/gcc.target/aarch64/sve/init_5.c

 /* { dg-do assemble { target aarch64_asm_sve_ok } } */
-/* { dg-options "-O2 -fno-schedule-insns -msve-vector-bits=256 --save-temps" } */
+/* { dg-options "-O -msve-vector-bits=256 --save-temps" } */
 
 /* Case 3: Trailing same element.  */ 
 
@@ -18,10 +18,9 @@ foo:
 .LFB0:
         .cfi_startproc
         mov     z0.s, w2
-        ptrue   p0.s, vl8
         insr    z0.s, w1
         insr    z0.s, w0
         ret
 */
 
-/* { dg-final { scan-assembler {\tmov\t(z[0-9]+\.s), w2\n.*\tinsr\t\1, w1\n\tinsr\t\1, w0} } } */
+/* { dg-final { scan-assembler {\tmov\t(z[0-9]+\.s), w2\n\tinsr\t\1, w1\n\tinsr\t\1, w0} } } */

gcc/testsuite/gcc.target/aarch64/sve/init_6.c

 /* { dg-do assemble { target aarch64_asm_sve_ok } } */
-/* { dg-options "-O2 -fno-schedule-insns -msve-vector-bits=256 --save-temps" } */
+/* { dg-options "-O -msve-vector-bits=256 --save-temps" } */
 
 /* Case 3: Trailing same element.  */ 
 
@@ -18,11 +18,10 @@ foo:
 .LFB0:
         .cfi_startproc
         mov     z0.s, w2
-        ptrue   p0.s, vl8
         insr    z0.s, w1
         insr    z0.s, w0
         rev     z0.s, z0.s
         ret
 */
 
-/* { dg-final { scan-assembler {\tmov\t(z[0-9]+\.s), w2\n.*\tinsr\t\1, w1\n\tinsr\t\1, w0\n\trev\t\1, \1} } } */
+/* { dg-final { scan-assembler {\tmov\t(z[0-9]+\.s), w2\n\tinsr\t\1, w1\n\tinsr\t\1, w0\n\trev\t\1, \1} } } */

gcc/testsuite/gcc.target/aarch64/sve/init_7.c

 /* { dg-do assemble { target aarch64_asm_sve_ok } } */
-/* { dg-options "-O2 -fno-schedule-insns -msve-vector-bits=256 --save-temps" } */
+/* { dg-options "-O -msve-vector-bits=256 --save-temps" } */
 
 /* Case 5.1: All elements.  */ 
 
@@ -18,7 +18,6 @@ foo:
 .LFB0:
         .cfi_startproc
         mov     z0.s, w7
-        ptrue   p0.s, vl8
         insr    z0.s, w6
         insr    z0.s, w5
         insr    z0.s, w4
@@ -29,4 +28,4 @@ foo:
         ret
 */
 
-/* { dg-final { scan-assembler {\tmov\t(z[0-9]+\.s), w7\n.*\tinsr\t\1, w6\n\tinsr\t\1, w5\n\tinsr\t\1, w4\n\tinsr\t\1, w3\n\tinsr\t\1, w2\n\tinsr\t\1, w1\n\tinsr\t\1, w0} } } */
+/* { dg-final { scan-assembler {\tmov\t(z[0-9]+\.s), w7\n\tinsr\t\1, w6\n\tinsr\t\1, w5\n\tinsr\t\1, w4\n\tinsr\t\1, w3\n\tinsr\t\1, w2\n\tinsr\t\1, w1\n\tinsr\t\1, w0} } } */

gcc/testsuite/gcc.target/aarch64/sve/init_8.c

 /* { dg-do assemble { target aarch64_asm_sve_ok } } */
-/* { dg-options "-O2 -fno-schedule-insns -msve-vector-bits=256 --save-temps" } */
+/* { dg-options "-O -msve-vector-bits=256 --save-temps" } */
 
 /* Case 5.2: Interleaved elements and constants.  */ 
 
@@ -18,15 +18,15 @@ foo:
 .LFB0:
         .cfi_startproc
         ptrue   p0.s, vl8
+        adrp    x4, .LANCHOR0
+        add     x4, x4, :lo12:.LANCHOR0
+        ld1w    z1.s, p0/z, [x4]
         mov     z0.s, w3
-        adrp    x3, .LANCHOR0
         insr    z0.s, w2
-        add     x3, x3, :lo12:.LANCHOR0
         insr    z0.s, w1
-        ld1w    z1.s, p0/z, [x3]
         insr    z0.s, w0
         zip1    z0.s, z0.s, z1.s
         ret
 */
 
-/* { dg-final { scan-assembler {\tmov\t(z[0-9]+\.s), w3\n\tadrp\t(x[0-9]+), \.LANCHOR0\n\tinsr\t\1, w2\n\tadd\t\2, \2, :lo12:\.LANCHOR0\n\tinsr\t\1, w1\n\tld1w\t(z[0-9]+\.s), p[0-9]+/z, \[\2\]\n\tinsr\t\1, w0\n\tzip1\t\1, \1, \3} } } */
+/* { dg-final { scan-assembler {\tld1w\t(z[0-9]+\.s), p[0-9]+/z, \[x[0-9]+\]\n\tmov\t(z[0-9]+\.s), w3\n\tinsr\t\2, w2\n\tinsr\t\2, w1\n\tinsr\t\2, w0\n\tzip1\t\2, \2, \1} } } */

gcc/testsuite/gcc.target/aarch64/sve/init_9.c

 /* { dg-do assemble { target aarch64_asm_sve_ok } } */
-/* { dg-options "-O2 -fno-schedule-insns -msve-vector-bits=256 --save-temps" } */
+/* { dg-options "-O -msve-vector-bits=256 --save-temps" } */
 
 /* Case 5.3: Repeated elements.  */ 
 
@@ -19,9 +19,8 @@ foo:
         .cfi_startproc
         mov     z0.s, w0
         mov     z1.s, w1
-        ptrue   p0.s, vl8
         zip1    z0.s, z0.s, z1.s
         ret
 */
 
-/* { dg-final { scan-assembler {\tmov\t(z[0-9]+\.s), w0\n\tmov\t(z[0-9]+\.s), w1\n.*\tzip1\t\1, \1, \2} } } */
+/* { dg-final { scan-assembler {\tmov\t(z[0-9]+\.s), w0\n\tmov\t(z[0-9]+\.s), w1\n\tzip1\t\1, \1, \2} } } */