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riscv-gcc-1
Commit 3a81b570 by Aldy Hernandez Committed by Aldy Hernandez
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* gimple.h (enum gf_mask): Change the ordering of GF_OMP_* bits. 

From-SVN: r204894
parent c4d1d6be
Showing with 8 additions and 4 deletions
gcc/ChangeLog
2013-11-15 Aldy Hernandez <aldyh@redhat.com>
* gimple.h (enum gf_mask): Change the ordering of GF_OMP_* bits.
2013-11-15 Kaz Kojima <kkojima@gcc.gnu.org> 2013-11-15 Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/sh.c (barrier_align): Return 0 when barrier_or_label * config/sh/sh.c (barrier_align): Return 0 when barrier_or_label
gcc/gimple.h
...@@ -102,13 +102,13 @@ enum gf_mask { ...@@ -102,13 +102,13 @@ enum gf_mask {
GF_CALL_ALLOCA_FOR_VAR = 1 << 5, GF_CALL_ALLOCA_FOR_VAR = 1 << 5,
GF_CALL_INTERNAL = 1 << 6, GF_CALL_INTERNAL = 1 << 6,
GF_OMP_PARALLEL_COMBINED = 1 << 0, GF_OMP_PARALLEL_COMBINED = 1 << 0,
GF_OMP_FOR_KIND_MASK = 7, GF_OMP_FOR_KIND_MASK = 3 << 0,
GF_OMP_FOR_KIND_FOR = 0 << 0, GF_OMP_FOR_KIND_FOR = 0 << 0,
GF_OMP_FOR_KIND_DISTRIBUTE = 1 << 0,
GF_OMP_FOR_KIND_SIMD = 2 << 0, GF_OMP_FOR_KIND_SIMD = 2 << 0,
GF_OMP_FOR_KIND_CILKSIMD = 3 << 0, GF_OMP_FOR_KIND_CILKSIMD = 3 << 0,
GF_OMP_FOR_KIND_DISTRIBUTE = 1 << 2, GF_OMP_FOR_COMBINED = 1 << 2,
GF_OMP_FOR_COMBINED = 1 << 3, GF_OMP_FOR_COMBINED_INTO = 1 << 3,
GF_OMP_FOR_COMBINED_INTO = 1 << 4,
GF_OMP_TARGET_KIND_MASK = 3 << 0, GF_OMP_TARGET_KIND_MASK = 3 << 0,
GF_OMP_TARGET_KIND_REGION = 0 << 0, GF_OMP_TARGET_KIND_REGION = 0 << 0,
GF_OMP_TARGET_KIND_DATA = 1 << 0, GF_OMP_TARGET_KIND_DATA = 1 << 0,
......
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