Skip to content

R
riscv-gcc-1
Commit 3a42aebe by Richard Earnshaw Committed by Richard Earnshaw
Options

re PR target/18973 (-mcpu=arm926ejs should set FL_LDSCHED) 

PR target/18973
arm-cores.def (arm926ej-s, arm1026ej-s, arm1136j-s, arm1136-jfs)
(arm1176jz-s, arm1176jzf-s, mpcorenovfp, mpcore): Add load-scheduling
property to flags.

From-SVN: r92135
parent 370d199d
Showing with 15 additions and 8 deletions
gcc/ChangeLog
2004-12-14 Richard Earnshaw <rearnsha@arm.com>
PR target/18973
arm-cores.def (arm926ej-s, arm1026ej-s, arm1136j-s, arm1136-jfs)
(arm1176jz-s, arm1176jzf-s, mpcorenovfp, mpcore): Add load-scheduling
property to flags.
2004-12-14 Diego Novillo <dnovillo@redhat.com>
* tree-gimple.c (get_base_address): Update documentation.
......
gcc/config/arm/arm-cores.def
......@@ -105,13 +105,13 @@ ARM_CORE("xscale", xscale, 5TE, FL_LDSCHED | FL_
ARM_CORE("iwmmxt", iwmmxt, 5TE, FL_LDSCHED | FL_STRONG | FL_XSCALE | FL_IWMMXT, xscale)
/* V5TEJ Architecture Processors */
ARM_CORE("arm926ej-s", arm926ejs, 5TEJ, 0, 9e)
ARM_CORE("arm1026ej-s", arm1026ejs, 5TEJ, 0, 9e)
ARM_CORE("arm926ej-s", arm926ejs, 5TEJ, FL_LDSCHED, 9e)
ARM_CORE("arm1026ej-s", arm1026ejs, 5TEJ, FL_LDSCHED, 9e)
/* V6 Architecture Processors */
ARM_CORE("arm1136j-s", arm1136js, 6J, 0, 9e)
ARM_CORE("arm1136jf-s", arm1136jfs, 6J, FL_VFPV2, 9e)
ARM_CORE("arm1176jz-s", arm1176jzs, 6ZK, 0, 9e)
ARM_CORE("arm1176jzf-s", arm1176jzfs, 6ZK, FL_VFPV2, 9e)
ARM_CORE("mpcorenovfp", mpcorenovfp, 6K, 0, 9e)
ARM_CORE("mpcore", mpcore, 6K, FL_VFPV2, 9e)
ARM_CORE("arm1136j-s", arm1136js, 6J, FL_LDSCHED, 9e)
ARM_CORE("arm1136jf-s", arm1136jfs, 6J, FL_LDSCHED | FL_VFPV2, 9e)
ARM_CORE("arm1176jz-s", arm1176jzs, 6ZK, FL_LDSCHED, 9e)
ARM_CORE("arm1176jzf-s", arm1176jzfs, 6ZK, FL_LDSCHED | FL_VFPV2, 9e)
ARM_CORE("mpcorenovfp", mpcorenovfp, 6K, FL_LDSCHED, 9e)
ARM_CORE("mpcore", mpcore, 6K, FL_LDSCHED | FL_VFPV2, 9e)
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment