config.gcc: Add options for arch and tune on SPU.

2007-07-13  Sa Liu  <saliu@de.ibm.com>

	* config.gcc: Add options for arch and tune on SPU.
	* config/spu/predicates.md: Add constant operands 0 and 1.
	* config/spu/spu-builtins.def: Add builtins for double precision 
	floating point comparison: si_dfceq, si_dfcmeq,	si_dfcgt, si_dfcmgt, 
	si_dftsv, spu_cmpeq_13, spu_cmpabseq_1, spu_cmpgt_13, spu_cmpabsgt_1,
	spu_testsv.
	* config/spu/spu-c.c: Define __SPU_EDP__ when builtins invoked with 
	a CELLEDP target.
	* config/spu/spu-protos.h: Add new function prototypes. 
	* config/spu/spu.c (spu_override_options): Check options -march and
	-mtune.
	(spu_comp_icode): Add comparison code for DFmode and vector mode.
	(spu_emit_branch_or_set): Use the new code for DFmode and vector 
	mode comparison.
	(spu_const_from_int): New.  Create a vector constant from 4 ints.
	(get_vec_cmp_insn): New.  Get insn index of vector compare instruction.
	(spu_emit_vector_compare): New.  Emit vector compare.
	(spu_emit_vector_cond_expr): New.  Emit vector conditional expression.
	* config/spu/spu.h: Add options -march and -mtune.  Define processor
	types PROCESSOR_CELL and PROCESSOR_CELLEDP.  Define macro
	CANONICALIZE_COMPARISON.
	* config/spu/spu.md: Add new insns for double precision compare
	and double precision vector compare.  Add vcond and smax/smin patterns
	to enable DFmode vector conditional expression.
	* config/spu/spu.opt: Add options -march and -mtune.
	* config/spu/spu_internals.h: Add builtins for CELLEDP target:
	si_dfceq, si_dfcmeq, si_dfcgt, si_dfcmgt, si_dftsv.  Add builtin for
	both CELL and CELLEDP targets: spu_testsv.
	* config/spu/spu_intrinsics.h: Add flag mnemonics for test special 
	values.

testsuite/
	* gcc.dg/vect/fast-math-vect-reduc-7.c: Switch on test
	for V2DFmode vector conditional expression.
	* gcc.target/spu/dfcmeq.c: New.  Test combination of abs
	and dfceq patterns.
	* gcc.target/spu/dfcmgt.c: New.  Test combination of abs
	and dfcgt patterns.
	* gcc.target/spu/intrinsics-2.c: New.  Test intrinsics for
	V2DFmode comparison and test special values.
	* lib/target-supports.exp: Switch on test for V2DFmode 
	vector conditional expression.

From-SVN: r126626

gcc/ChangeLog

+2007-07-13  Sa Liu  <saliu@de.ibm.com>
+
+	* config.gcc: Add options for arch and tune on SPU.
+	* config/spu/predicates.md: Add constant operands 0 and 1.
+	* config/spu/spu-builtins.def: Add builtins for double precision 
+	floating point comparison: si_dfceq, si_dfcmeq,	si_dfcgt, si_dfcmgt, 
+	si_dftsv, spu_cmpeq_13, spu_cmpabseq_1, spu_cmpgt_13, spu_cmpabsgt_1,
+	spu_testsv.
+	* config/spu/spu-c.c: Define __SPU_EDP__ when builtins invoked with 
+	a CELLEDP target.
+	* config/spu/spu-protos.h: Add new function prototypes. 
+	* config/spu/spu.c (spu_override_options): Check options -march and
+	-mtune.
+	(spu_comp_icode): Add comparison code for DFmode and vector mode.
+	(spu_emit_branch_or_set): Use the new code for DFmode and vector 
+	mode comparison.
+	(spu_const_from_int): New.  Create a vector constant from 4 ints.
+	(get_vec_cmp_insn): New.  Get insn index of vector compare instruction.
+	(spu_emit_vector_compare): New.  Emit vector compare.
+	(spu_emit_vector_cond_expr): New.  Emit vector conditional expression.
+	* config/spu/spu.h: Add options -march and -mtune.  Define processor
+	types PROCESSOR_CELL and PROCESSOR_CELLEDP.  Define macro
+	CANONICALIZE_COMPARISON.
+	* config/spu/spu.md: Add new insns for double precision compare
+	and double precision vector compare.  Add vcond and smax/smin patterns
+	to enable DFmode vector conditional expression.
+	* config/spu/spu.opt: Add options -march and -mtune.
+	* config/spu/spu_internals.h: Add builtins for CELLEDP target:
+	si_dfceq, si_dfcmeq, si_dfcgt, si_dfcmgt, si_dftsv.  Add builtin for
+	both CELL and CELLEDP targets: spu_testsv.
+	* config/spu/spu_intrinsics.h: Add flag mnemonics for test special 
+	values.
+
 2007-07-13  Richard Guenther  <rguenther@suse.de>
 
 	PR tree-optimization/32721

gcc/config.gcc

@@ -3142,6 +3142,23 @@ case "${target}" in
 		esac
 		;;
 
+	spu-*-*)
+		supported_defaults="arch tune"
+
+		for which in arch tune; do
+			eval "val=\$with_$which"
+			case ${val} in
+			"" | cell | celledp)
+				# OK
+				;;
+			*)
+				echo "Unknown cpu used in --with-$which=$val." 1>&2
+				exit 1
+				;;
+			esac
+		done
+		;;
+
 	v850*-*-*)
 		supported_defaults=cpu
 		case ${with_cpu} in

gcc/config/spu/predicates.md

@@ -16,6 +16,15 @@
 ;; Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
 ;; 02110-1301, USA.
 
+;; Return 1 if operand is constant zero of its mode
+(define_predicate "const_zero_operand"
+  (and (match_code "const_int,const,const_double,const_vector")
+       (match_test "op == CONST0_RTX (mode)")))
+
+(define_predicate "const_one_operand"
+  (and (match_code "const_int,const,const_double,const_vector")
+       (match_test "op == CONST1_RTX (mode)")))
+
 (define_predicate "spu_reg_operand"
   (and (match_operand 0 "register_operand")
        (ior (not (match_code "subreg"))

gcc/config/spu/spu-builtins.def

@@ -189,9 +189,14 @@ DEF_BUILTIN (SI_CFLTU,       CODE_FOR_spu_cfltu,     "si_cfltu",       B_INSN,
 DEF_BUILTIN (SI_FRDS,        CODE_FOR_spu_frds,      "si_frds",        B_INSN,   _A2(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
 DEF_BUILTIN (SI_FESD,        CODE_FOR_spu_fesd,      "si_fesd",        B_INSN,   _A2(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
 DEF_BUILTIN (SI_FCEQ,        CODE_FOR_ceq_v4sf,      "si_fceq",        B_INSN,   _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
+DEF_BUILTIN (SI_DFCEQ,       CODE_FOR_ceq_v2df,      "si_dfceq",       B_INSN,   _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
 DEF_BUILTIN (SI_FCMEQ,       CODE_FOR_cmeq_v4sf,     "si_fcmeq",       B_INSN,   _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
+DEF_BUILTIN (SI_DFCMEQ,      CODE_FOR_cmeq_v2df,     "si_dfcmeq",      B_INSN,   _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
 DEF_BUILTIN (SI_FCGT,        CODE_FOR_cgt_v4sf,      "si_fcgt",        B_INSN,   _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
+DEF_BUILTIN (SI_DFCGT,       CODE_FOR_cgt_v2df,      "si_dfcgt",       B_INSN,   _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
 DEF_BUILTIN (SI_FCMGT,       CODE_FOR_cmgt_v4sf,     "si_fcmgt",       B_INSN,   _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
+DEF_BUILTIN (SI_DFCMGT,      CODE_FOR_cmgt_v2df,     "si_dfcmgt",      B_INSN,   _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
+DEF_BUILTIN (SI_DFTSV,       CODE_FOR_dftsv,         "si_dftsv",       B_INSN,   _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_U7))
 DEF_BUILTIN (SI_STOP,        CODE_FOR_spu_stop,      "si_stop",        B_INSN,   _A2(SPU_BTI_VOID,     SPU_BTI_U14))
 DEF_BUILTIN (SI_STOPD,       CODE_FOR_spu_stopd,     "si_stopd",       B_INSN,   _A4(SPU_BTI_VOID,     SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
 DEF_BUILTIN (SI_LNOP,        CODE_FOR_lnop,          "si_lnop",        B_INSN,   _A1(SPU_BTI_VOID))
@@ -245,11 +250,10 @@ DEF_BUILTIN (SPU_SUMB,       CODE_FOR_spu_sumb,       "spu_sumb",       B_INSN,
 DEF_BUILTIN (SPU_BISLED,     CODE_FOR_spu_bisled,     "spu_bisled",     B_BISLED,   _A3(SPU_BTI_VOID,    SPU_BTI_PTR,   SPU_BTI_PTR))
 DEF_BUILTIN (SPU_BISLED_D,   CODE_FOR_spu_bisledd,    "spu_bisled_d",   B_BISLED,   _A3(SPU_BTI_VOID,    SPU_BTI_PTR,   SPU_BTI_PTR))
 DEF_BUILTIN (SPU_BISLED_E,   CODE_FOR_spu_bislede,    "spu_bisled_e",   B_BISLED,   _A3(SPU_BTI_VOID,    SPU_BTI_PTR,   SPU_BTI_PTR))
-DEF_BUILTIN (SPU_CMPABSEQ,   CODE_FOR_cmeq_v4sf,      "spu_cmpabseq",   B_INSN,     _A3(SPU_BTI_UV4SI,    SPU_BTI_V4SF,   SPU_BTI_V4SF))
-DEF_BUILTIN (SPU_CMPABSGT,   CODE_FOR_cmgt_v4sf,      "spu_cmpabsgt",   B_INSN,     _A3(SPU_BTI_UV4SI,    SPU_BTI_V4SF,   SPU_BTI_V4SF))
 DEF_BUILTIN (SPU_IDISABLE,   CODE_FOR_spu_idisable,   "spu_idisable",   B_INSN,     _A1(SPU_BTI_VOID))
 DEF_BUILTIN (SPU_IENABLE,    CODE_FOR_spu_ienable,    "spu_ienable",    B_INSN,     _A1(SPU_BTI_VOID))
 DEF_BUILTIN (SPU_MASK_FOR_LOAD,    CODE_FOR_spu_lvsr, "spu_lvsr",       B_INSN,     _A2(SPU_BTI_V16QI, SPU_BTI_PTR))
+DEF_BUILTIN (SPU_TESTSV,     CODE_FOR_dftsv,          "spu_testsv",     B_INSN,     _A3(SPU_BTI_UV2DI, SPU_BTI_V2DF, SPU_BTI_U7))
 
 /* definitions to support overloaded generic builtin functions:  */
 
@@ -339,6 +343,10 @@ DEF_BUILTIN (SPU_CMPEQ_9,          CODE_FOR_ceq_v8hi,      "spu_cmpeq_9",
 DEF_BUILTIN (SPU_CMPEQ_10,         CODE_FOR_ceq_v8hi,      "spu_cmpeq_10",         B_INTERNAL, _A3(SPU_BTI_UV8HI,  SPU_BTI_V8HI,   SPU_BTI_INTHI))
 DEF_BUILTIN (SPU_CMPEQ_11,         CODE_FOR_ceq_v4si,      "spu_cmpeq_11",         B_INTERNAL, _A3(SPU_BTI_UV4SI,  SPU_BTI_UV4SI,  SPU_BTI_UINTSI))
 DEF_BUILTIN (SPU_CMPEQ_12,         CODE_FOR_ceq_v4si,      "spu_cmpeq_12",         B_INTERNAL, _A3(SPU_BTI_UV4SI,  SPU_BTI_V4SI,   SPU_BTI_INTSI))
+DEF_BUILTIN (SPU_CMPEQ_13,         CODE_FOR_ceq_v2df,      "spu_cmpeq_13",         B_INTERNAL, _A3(SPU_BTI_UV2DI,  SPU_BTI_V2DF,   SPU_BTI_V2DF))
+DEF_BUILTIN (SPU_CMPABSEQ,         CODE_FOR_nothing,       "spu_cmpabseq",         B_OVERLOAD, _A1(SPU_BTI_VOID))
+DEF_BUILTIN (SPU_CMPABSEQ_0,       CODE_FOR_cmeq_v4sf,     "spu_cmpabseq_0",       B_INTERNAL, _A3(SPU_BTI_UV4SI, SPU_BTI_V4SF, SPU_BTI_V4SF))
+DEF_BUILTIN (SPU_CMPABSEQ_1,       CODE_FOR_cmeq_v2df,     "spu_cmpabseq_1",       B_INTERNAL, _A3(SPU_BTI_UV2DI, SPU_BTI_V2DF, SPU_BTI_V2DF))
 DEF_BUILTIN (SPU_CMPGT,            CODE_FOR_nothing,       "spu_cmpgt",            B_OVERLOAD, _A1(SPU_BTI_VOID))
 DEF_BUILTIN (SPU_CMPGT_0,          CODE_FOR_clgt_v16qi,    "spu_cmpgt_0",          B_INTERNAL, _A3(SPU_BTI_UV16QI, SPU_BTI_UV16QI, SPU_BTI_UV16QI))
 DEF_BUILTIN (SPU_CMPGT_1,          CODE_FOR_cgt_v16qi,     "spu_cmpgt_1",          B_INTERNAL, _A3(SPU_BTI_UV16QI, SPU_BTI_V16QI,  SPU_BTI_V16QI))
@@ -353,6 +361,10 @@ DEF_BUILTIN (SPU_CMPGT_9,          CODE_FOR_clgt_v8hi,     "spu_cmpgt_9",
 DEF_BUILTIN (SPU_CMPGT_10,         CODE_FOR_cgt_v8hi,      "spu_cmpgt_10",         B_INTERNAL, _A3(SPU_BTI_UV8HI,  SPU_BTI_V8HI,   SPU_BTI_INTHI))
 DEF_BUILTIN (SPU_CMPGT_11,         CODE_FOR_cgt_v4si,      "spu_cmpgt_11",         B_INTERNAL, _A3(SPU_BTI_UV4SI,  SPU_BTI_V4SI,   SPU_BTI_INTSI))
 DEF_BUILTIN (SPU_CMPGT_12,         CODE_FOR_clgt_v4si,     "spu_cmpgt_12",         B_INTERNAL, _A3(SPU_BTI_UV4SI,  SPU_BTI_UV4SI,  SPU_BTI_UINTSI))
+DEF_BUILTIN (SPU_CMPGT_13,         CODE_FOR_cgt_v2df,      "spu_cmpgt_13",         B_INTERNAL, _A3(SPU_BTI_UV2DI,  SPU_BTI_V2DF,   SPU_BTI_V2DF))
+DEF_BUILTIN (SPU_CMPABSGT,         CODE_FOR_nothing,       "spu_cmpabsgt",         B_OVERLOAD, _A1(SPU_BTI_VOID))
+DEF_BUILTIN (SPU_CMPABSGT_0,       CODE_FOR_cmgt_v4sf,     "spu_cmpabsgt_0",       B_INTERNAL, _A3(SPU_BTI_UV4SI, SPU_BTI_V4SF, SPU_BTI_V4SF))
+DEF_BUILTIN (SPU_CMPABSGT_1,       CODE_FOR_cmgt_v2df,     "spu_cmpabsgt_1",       B_INTERNAL, _A3(SPU_BTI_UV2DI, SPU_BTI_V2DF, SPU_BTI_V2DF))
 DEF_BUILTIN (SPU_HCMPEQ,           CODE_FOR_nothing,       "spu_hcmpeq",           B_OVERLOAD, _A1(SPU_BTI_VOID))
 DEF_BUILTIN (SPU_HCMPEQ_0,         CODE_FOR_spu_heq,       "spu_hcmpeq_0",         B_INTERNAL, _A3(SPU_BTI_VOID,  SPU_BTI_INTSI,  SPU_BTI_INTSI))
 DEF_BUILTIN (SPU_HCMPEQ_1,         CODE_FOR_spu_heq,       "spu_hcmpeq_1",         B_INTERNAL, _A3(SPU_BTI_VOID,  SPU_BTI_UINTSI, SPU_BTI_UINTSI))

gcc/config/spu/spu-c.c

@@ -138,6 +138,8 @@ spu_cpu_cpp_builtins (struct cpp_reader *pfile)
   builtin_define_std ("__SPU__");
   cpp_assert (pfile, "cpu=spu");
   cpp_assert (pfile, "machine=spu");
+  if (spu_arch == PROCESSOR_CELLEDP)
+    builtin_define_std ("__SPU_EDP__");
   builtin_define_std ("__vector=__attribute__((__spu_vector__))");
 }
 

gcc/config/spu/spu-protos.h

@@ -32,6 +32,7 @@ extern void spu_expand_insv (rtx * ops);
 extern int spu_expand_block_move (rtx * ops);
 extern void spu_emit_branch_or_set (int is_set, enum rtx_code code,
 				    rtx * operands);
+extern int spu_emit_vector_cond_expr (rtx, rtx, rtx, rtx, rtx, rtx);
 extern HOST_WIDE_INT const_double_to_hwint (rtx x);
 extern rtx hwint_to_const_double (enum machine_mode mode, HOST_WIDE_INT v);
 extern void print_operand_address (FILE * file, register rtx addr);
@@ -43,6 +44,8 @@ extern void spu_expand_prologue (void);
 extern void spu_expand_epilogue (unsigned char sibcall_p);
 extern rtx spu_return_addr (int count, rtx frame);
 extern rtx spu_const (enum machine_mode mode, HOST_WIDE_INT val);
+extern rtx spu_const_from_ints (enum machine_mode mode, 
+			        int a, int b, int c, int d);
 extern struct rtx_def *spu_float_const (const char *string,
 					enum machine_mode mode);
 extern int immediate_load_p (rtx op, enum machine_mode mode);

gcc/config/spu/spu.h

@@ -32,6 +32,23 @@
 extern int target_flags;
 extern const char *spu_fixed_range_string;
 
+/* Which processor to generate code or schedule for.  */
+enum processor_type
+{
+  PROCESSOR_CELL,
+  PROCESSOR_CELLEDP
+};
+
+extern GTY(()) int spu_arch;
+extern GTY(()) int spu_tune;
+
+/* Support for a compile-time default architecture and tuning.  The rules are:
+   --with-arch is ignored if -march is specified.
+   --with-tune is ignored if -mtune is specified.  */
+#define OPTION_DEFAULT_SPECS \
+  {"arch", "%{!march=*:-march=%(VALUE)}" }, \
+  {"tune", "%{!mtune=*:-mtune=%(VALUE)}" }
+
 /* Default target_flags if no switches specified.  */
 #ifndef TARGET_DEFAULT
 #define TARGET_DEFAULT (MASK_ERROR_RELOC | MASK_SAFE_DMA | MASK_BRANCH_HINTS)
@@ -605,7 +622,18 @@ targetm.resolve_overloaded_builtin = spu_resolve_overloaded_builtin;	\
 #define NO_IMPLICIT_EXTERN_C 1
 
 #define HANDLE_PRAGMA_PACK_PUSH_POP 1
-
+
+/* Canonicalize a comparison from one we don't have to one we do have.  */
+#define CANONICALIZE_COMPARISON(CODE,OP0,OP1) \
+  do {                                                                    \
+    if (((CODE) == LE || (CODE) == LT || (CODE) == LEU || (CODE) == LTU)) \
+      {                                                                   \
+        rtx tem = (OP0);                                                  \
+        (OP0) = (OP1);                                                    \
+        (OP1) = tem;                                                      \
+        (CODE) = swap_condition (CODE);                                   \
+      }                                                                   \
+  } while (0)
 
 /* These are set by the cmp patterns and used while expanding
    conditional branches. */

gcc/config/spu/spu.opt

@@ -55,3 +55,11 @@ Generate code for 32 bit addressing
 mfixed-range=
 Target RejectNegative Joined Var(spu_fixed_range_string)
 Specify range of registers to make fixed
+
+march=
+Target RejectNegative Joined Var(spu_arch_string)
+Generate code for given CPU
+
+mtune=
+Target RejectNegative Joined Var(spu_tune_string)
+Schedule code for given CPU

gcc/config/spu/spu_internals.h

@@ -233,6 +233,15 @@
 #define si_rchcnt(imm)       __builtin_si_rchcnt(imm)
 #define si_wrch(imm,ra)      __builtin_si_wrch(imm,ra)
 
+/* celledp only instructions  */
+#ifdef __SPU_EDP__
+#define si_dfceq(ra,rb)      __builtin_si_dfceq(ra,rb)
+#define si_dfcmeq(ra,rb)     __builtin_si_dfcmeq(ra,rb)
+#define si_dfcgt(ra,rb)      __builtin_si_dfcgt(ra,rb)
+#define si_dfcmgt(ra,rb)     __builtin_si_dfcmgt(ra,rb)
+#define si_dftsv(ra,imm)     __builtin_si_dftsv(ra,imm)
+#endif /* __SPU_EDP__  */
+
 #define si_from_char(scalar)    __builtin_si_from_char(scalar)
 #define si_from_uchar(scalar)   __builtin_si_from_uchar(scalar)
 #define si_from_short(scalar)   __builtin_si_from_short(scalar)
@@ -295,6 +304,7 @@
 #define spu_cmpabsgt(ra,rb)       __builtin_spu_cmpabsgt(ra,rb) 
 #define spu_cmpeq(ra,rb)          __builtin_spu_cmpeq(ra,rb) 
 #define spu_cmpgt(ra,rb)          __builtin_spu_cmpgt(ra,rb) 
+#define spu_testsv(ra,imm)        __builtin_spu_testsv(ra,imm) 
 #define spu_hcmpeq(ra,rb)         __builtin_spu_hcmpeq(ra,rb) 
 #define spu_hcmpgt(ra,rb)         __builtin_spu_hcmpgt(ra,rb) 
 #define spu_cntb(ra)              __builtin_spu_cntb(ra) 

gcc/config/spu/spu_intrinsics.h

@@ -70,6 +70,16 @@
 #define MFC_WrListStallAck	26 
 #define MFC_RdAtomicStat	27 
 
+/* Bit flag mnemonics for test special value.
+ */
+#define SPU_SV_NEG_DENORM       0x01    /* negative denormalized number  */
+#define SPU_SV_POS_DENORM       0x02    /* positive denormalized number  */
+#define SPU_SV_NEG_ZERO         0x04    /* negative zero                 */
+#define SPU_SV_POS_ZERO         0x08    /* positive zero                 */
+#define SPU_SV_NEG_INFINITY     0x10    /* negative infinity             */
+#define SPU_SV_POS_INFINITY     0x20    /* positive infinity             */
+#define SPU_SV_NAN              0x40    /* not a number                  */
+
 #include <spu_internals.h>
 
 #endif /* _SPU_INTRINSICS_H */

gcc/testsuite/ChangeLog

+2007-07-13  Sa Liu  <saliu@de.ibm.com>
+
+	* gcc.dg/vect/fast-math-vect-reduc-7.c: Switch on test
+	for V2DFmode vector conditional expression.
+	* gcc.target/spu/dfcmeq.c: New.  Test combination of abs
+	and dfceq patterns.
+	* gcc.target/spu/dfcmgt.c: New.  Test combination of abs
+	and dfcgt patterns.
+	* gcc.target/spu/intrinsics-2.c: New.  Test intrinsics for
+	V2DFmode comparison and test special values.
+	* lib/target-supports.exp: Switch on test for V2DFmode 
+	vector conditional expression.
+
 2007-07-13  Richard Guenther  <rguenther@suse.de>
 
 	PR tree-optimization/32721

gcc/testsuite/gcc.dg/vect/fast-math-vect-reduc-7.c

@@ -50,6 +50,5 @@ int main (void)
   return 0;
 }
 
-/* { dg-final { scan-tree-dump-times "vectorized 3 loops" 1 "vect" { xfail vect_no_compare_double } } } */
-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target vect_no_compare_double } } } */
+/* { dg-final { scan-tree-dump-times "vectorized 3 loops" 1 "vect" } } */
 /* { dg-final { cleanup-tree-dump "vect" } } */

gcc/testsuite/lib/target-supports.exp

@@ -1659,7 +1659,7 @@ proc check_effective_target_vect_double { } {
     return $et_vect_double_saved
 }
 
-# Return 0 if the target supports hardware comparison of vectors of double, 0 otherwise.
+# Return 1 if the target supports hardware comparison of vectors of double, 0 otherwise.
 #
 # This won't change for different subtargets so cache the result.
 
@@ -1670,9 +1670,6 @@ proc check_effective_target_vect_no_compare_double { } {
         verbose "check_effective_target_vect_no_compare_double: using cached result" 2
     } else {
         set et_vect_no_compare_double_saved 0
-        if { [istarget spu-*-*] } {
-           set et_vect_no_compare_double_saved 1
-        }
     }
 
     verbose "check_effective_target_vect_no_compare_double: returning $et_vect_no_compare_double_saved" 2
@@ -2025,6 +2022,7 @@ proc check_effective_target_vect_condition { } {
 	if { [istarget powerpc*-*-*]
 	     || [istarget ia64-*-*]
 	     || [istarget i?86-*-*]
+	     || [istarget spu-*-*]
 	     || [istarget x86_64-*-*] } {
 	   set et_vect_cond_saved 1
 	}