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riscv-gcc-1
Commit 37f74dcf by Richard Earnshaw Committed by Richard Earnshaw
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* arm.md (addsf3, adddf3, subsf3, subdf3, mulsf3, muldf3, negsf2) 

(negdf2, abssi2, abssf2, absdf2, floatsisf2, floatsidf2)
(fix_truncsfsi2, fix_truncdfsi2, truncdfsf2): Moved back into main
machine description file from ...
* cirrus.md: ... here.

From-SVN: r63940
parent 3bf74da2
Showing with 177 additions and 171 deletions
gcc/ChangeLog
2003-03-07 Richard Earnshaw <rearnsha@arm.com>
* arm.md (addsf3, adddf3, subsf3, subdf3, mulsf3, muldf3, negsf2)
(negdf2, abssi2, abssf2, absdf2, floatsisf2, floatsidf2)
(fix_truncsfsi2, fix_truncdfsi2, truncdfsf2): Moved back into main
machine description file from ...
* cirrus.md: ... here.
2003-03-06 Kazu Hirata <kazu@cs.umass.edu> 2003-03-06 Kazu Hirata <kazu@cs.umass.edu>
* config/h8300/h8300.md (a peephole2): Don't use * config/h8300/h8300.md (a peephole2): Don't use
......
gcc/config/arm/arm.md
...@@ -806,6 +806,17 @@ ...@@ -806,6 +806,17 @@
(set_attr "length" "4,8")] (set_attr "length" "4,8")]
) )
(define_expand "addsf3"
[(set (match_operand:SF 0 "s_register_operand" "")
(plus:SF (match_operand:SF 1 "s_register_operand" "")
(match_operand:SF 2 "fpu_add_operand" "")))]
"TARGET_ARM && TARGET_ANY_HARD_FLOAT"
"
if (TARGET_CIRRUS
&& !cirrus_fp_register (operands[2], SFmode))
operands[2] = force_reg (SFmode, operands[2]);
")
(define_insn "*arm_addsf3" (define_insn "*arm_addsf3"
[(set (match_operand:SF 0 "s_register_operand" "=f,f") [(set (match_operand:SF 0 "s_register_operand" "=f,f")
(plus:SF (match_operand:SF 1 "s_register_operand" "%f,f") (plus:SF (match_operand:SF 1 "s_register_operand" "%f,f")
...@@ -818,6 +829,17 @@ ...@@ -818,6 +829,17 @@
(set_attr "predicable" "yes")] (set_attr "predicable" "yes")]
) )
(define_expand "adddf3"
[(set (match_operand:DF 0 "s_register_operand" "")
(plus:DF (match_operand:DF 1 "s_register_operand" "")
(match_operand:DF 2 "fpu_add_operand" "")))]
"TARGET_ARM && TARGET_ANY_HARD_FLOAT"
"
if (TARGET_CIRRUS
&& !cirrus_fp_register (operands[2], DFmode))
operands[2] = force_reg (DFmode, operands[2]);
")
(define_insn "*arm_adddf3" (define_insn "*arm_adddf3"
[(set (match_operand:DF 0 "s_register_operand" "=f,f") [(set (match_operand:DF 0 "s_register_operand" "=f,f")
(plus:DF (match_operand:DF 1 "s_register_operand" "%f,f") (plus:DF (match_operand:DF 1 "s_register_operand" "%f,f")
...@@ -1068,6 +1090,21 @@ ...@@ -1068,6 +1090,21 @@
(set_attr "length" "*,8")] (set_attr "length" "*,8")]
) )
(define_expand "subsf3"
[(set (match_operand:SF 0 "s_register_operand" "")
(minus:SF (match_operand:SF 1 "fpu_rhs_operand" "")
(match_operand:SF 2 "fpu_rhs_operand" "")))]
"TARGET_ARM && TARGET_ANY_HARD_FLOAT"
"
if (TARGET_CIRRUS)
{
if (!cirrus_fp_register (operands[1], SFmode))
operands[1] = force_reg (SFmode, operands[1]);
if (!cirrus_fp_register (operands[2], SFmode))
operands[2] = force_reg (SFmode, operands[2]);
}
")
(define_insn "*arm_subsf3" (define_insn "*arm_subsf3"
[(set (match_operand:SF 0 "s_register_operand" "=f,f") [(set (match_operand:SF 0 "s_register_operand" "=f,f")
(minus:SF (match_operand:SF 1 "fpu_rhs_operand" "f,G") (minus:SF (match_operand:SF 1 "fpu_rhs_operand" "f,G")
...@@ -1079,6 +1116,21 @@ ...@@ -1079,6 +1116,21 @@
[(set_attr "type" "farith")] [(set_attr "type" "farith")]
) )
(define_expand "subdf3"
[(set (match_operand:DF 0 "s_register_operand" "")
(minus:DF (match_operand:DF 1 "fpu_rhs_operand" "")
(match_operand:DF 2 "fpu_rhs_operand" "")))]
"TARGET_ARM && TARGET_ANY_HARD_FLOAT"
"
if (TARGET_CIRRUS)
{
if (!cirrus_fp_register (operands[1], DFmode))
operands[1] = force_reg (DFmode, operands[1]);
if (!cirrus_fp_register (operands[2], DFmode))
operands[2] = force_reg (DFmode, operands[2]);
}
")
(define_insn "*arm_subdf3" (define_insn "*arm_subdf3"
[(set (match_operand:DF 0 "s_register_operand" "=f,f") [(set (match_operand:DF 0 "s_register_operand" "=f,f")
(minus:DF (match_operand:DF 1 "fpu_rhs_operand" "f,G") (minus:DF (match_operand:DF 1 "fpu_rhs_operand" "f,G")
...@@ -1401,6 +1453,17 @@ ...@@ -1401,6 +1453,17 @@
[(set_attr "type" "mult") [(set_attr "type" "mult")
(set_attr "predicable" "yes")]) (set_attr "predicable" "yes")])
(define_expand "mulsf3"
[(set (match_operand:SF 0 "s_register_operand" "")
(mult:SF (match_operand:SF 1 "s_register_operand" "")
(match_operand:SF 2 "fpu_rhs_operand" "")))]
"TARGET_ARM && TARGET_ANY_HARD_FLOAT"
"
if (TARGET_CIRRUS
&& !cirrus_fp_register (operands[2], SFmode))
operands[2] = force_reg (SFmode, operands[2]);
")
(define_insn "*arm_mulsf3" (define_insn "*arm_mulsf3"
[(set (match_operand:SF 0 "s_register_operand" "=f") [(set (match_operand:SF 0 "s_register_operand" "=f")
(mult:SF (match_operand:SF 1 "s_register_operand" "f") (mult:SF (match_operand:SF 1 "s_register_operand" "f")
...@@ -1411,6 +1474,17 @@ ...@@ -1411,6 +1474,17 @@
(set_attr "predicable" "yes")] (set_attr "predicable" "yes")]
) )
(define_expand "muldf3"
[(set (match_operand:DF 0 "s_register_operand" "")
(mult:DF (match_operand:DF 1 "s_register_operand" "")
(match_operand:DF 2 "fpu_rhs_operand" "")))]
"TARGET_ARM && TARGET_ANY_HARD_FLOAT"
"
if (TARGET_CIRRUS
&& !cirrus_fp_register (operands[2], DFmode))
operands[2] = force_reg (DFmode, operands[2]);
")
(define_insn "*arm_muldf3" (define_insn "*arm_muldf3"
[(set (match_operand:DF 0 "s_register_operand" "=f") [(set (match_operand:DF 0 "s_register_operand" "=f")
(mult:DF (match_operand:DF 1 "s_register_operand" "f") (mult:DF (match_operand:DF 1 "s_register_operand" "f")
...@@ -2784,6 +2858,19 @@ ...@@ -2784,6 +2858,19 @@
[(set_attr "length" "2")] [(set_attr "length" "2")]
) )
(define_expand "negsf2"
[(set (match_operand:SF 0 "s_register_operand" "")
(neg:SF (match_operand:SF 1 "s_register_operand" "")))]
"TARGET_ARM && TARGET_ANY_HARD_FLOAT"
""
)
(define_expand "negdf2"
[(set (match_operand:DF 0 "s_register_operand" "")
(neg:DF (match_operand:DF 1 "s_register_operand" "")))]
"TARGET_ARM && TARGET_ANY_HARD_FLOAT"
"")
(define_insn "*arm_negsf2" (define_insn "*arm_negsf2"
[(set (match_operand:SF 0 "s_register_operand" "=f") [(set (match_operand:SF 0 "s_register_operand" "=f")
(neg:SF (match_operand:SF 1 "s_register_operand" "f")))] (neg:SF (match_operand:SF 1 "s_register_operand" "f")))]
...@@ -2817,6 +2904,14 @@ ...@@ -2817,6 +2904,14 @@
;; it does, but tell the final scan operator the truth. Similarly for ;; it does, but tell the final scan operator the truth. Similarly for
;; (neg (abs...)) ;; (neg (abs...))
(define_expand "abssi2"
[(parallel
[(set (match_operand:SI 0 "s_register_operand" "")
(abs:SI (match_operand:SI 1 "s_register_operand" "")))
(clobber (reg:CC CC_REGNUM))])]
"TARGET_ARM"
"")
(define_insn "*arm_abssi2" (define_insn "*arm_abssi2"
[(set (match_operand:SI 0 "s_register_operand" "=r,&r") [(set (match_operand:SI 0 "s_register_operand" "=r,&r")
(abs:SI (match_operand:SI 1 "s_register_operand" "0,r"))) (abs:SI (match_operand:SI 1 "s_register_operand" "0,r")))
...@@ -2845,6 +2940,12 @@ ...@@ -2845,6 +2940,12 @@
(set_attr "length" "8")] (set_attr "length" "8")]
) )
(define_expand "abssf2"
[(set (match_operand:SF 0 "s_register_operand" "")
(abs:SF (match_operand:SF 1 "s_register_operand" "")))]
"TARGET_ARM && TARGET_ANY_HARD_FLOAT"
"")
(define_insn "*arm_abssf2" (define_insn "*arm_abssf2"
[(set (match_operand:SF 0 "s_register_operand" "=f") [(set (match_operand:SF 0 "s_register_operand" "=f")
(abs:SF (match_operand:SF 1 "s_register_operand" "f")))] (abs:SF (match_operand:SF 1 "s_register_operand" "f")))]
...@@ -2854,6 +2955,12 @@ ...@@ -2854,6 +2955,12 @@
(set_attr "predicable" "yes")] (set_attr "predicable" "yes")]
) )
(define_expand "absdf2"
[(set (match_operand:DF 0 "s_register_operand" "")
(abs:DF (match_operand:DF 1 "s_register_operand" "")))]
"TARGET_ARM && TARGET_ANY_HARD_FLOAT"
"")
(define_insn "*arm_absdf2" (define_insn "*arm_absdf2"
[(set (match_operand:DF 0 "s_register_operand" "=f") [(set (match_operand:DF 0 "s_register_operand" "=f")
(abs:DF (match_operand:DF 1 "s_register_operand" "f")))] (abs:DF (match_operand:DF 1 "s_register_operand" "f")))]
...@@ -2966,6 +3073,18 @@ ...@@ -2966,6 +3073,18 @@
;; Fixed <--> Floating conversion insns ;; Fixed <--> Floating conversion insns
(define_expand "floatsisf2"
[(set (match_operand:SF 0 "s_register_operand" "")
(float:SF (match_operand:SI 1 "s_register_operand" "")))]
"TARGET_ARM && TARGET_ANY_HARD_FLOAT"
"
if (TARGET_CIRRUS)
{
emit_insn (gen_cirrus_floatsisf2 (operands[0], operands[1]));
DONE;
}
")
(define_insn "*arm_floatsisf2" (define_insn "*arm_floatsisf2"
[(set (match_operand:SF 0 "s_register_operand" "=f") [(set (match_operand:SF 0 "s_register_operand" "=f")
(float:SF (match_operand:SI 1 "s_register_operand" "r")))] (float:SF (match_operand:SI 1 "s_register_operand" "r")))]
...@@ -2975,6 +3094,18 @@ ...@@ -2975,6 +3094,18 @@
(set_attr "predicable" "yes")] (set_attr "predicable" "yes")]
) )
(define_expand "floatsidf2"
[(set (match_operand:DF 0 "s_register_operand" "")
(float:DF (match_operand:SI 1 "s_register_operand" "")))]
"TARGET_ARM && TARGET_ANY_HARD_FLOAT"
"
if (TARGET_CIRRUS)
{
emit_insn (gen_cirrus_floatsidf2 (operands[0], operands[1]));
DONE;
}
")
(define_insn "*arm_floatsidf2" (define_insn "*arm_floatsidf2"
[(set (match_operand:DF 0 "s_register_operand" "=f") [(set (match_operand:DF 0 "s_register_operand" "=f")
(float:DF (match_operand:SI 1 "s_register_operand" "r")))] (float:DF (match_operand:SI 1 "s_register_operand" "r")))]
...@@ -2984,6 +3115,22 @@ ...@@ -2984,6 +3115,22 @@
(set_attr "predicable" "yes")] (set_attr "predicable" "yes")]
) )
(define_expand "fix_truncsfsi2"
[(set (match_operand:SI 0 "s_register_operand" "")
(fix:SI (match_operand:SF 1 "s_register_operand" "")))]
"TARGET_ARM && TARGET_ANY_HARD_FLOAT"
"
if (TARGET_CIRRUS)
{
if (!cirrus_fp_register (operands[0], SImode))
operands[0] = force_reg (SImode, operands[0]);
if (!cirrus_fp_register (operands[1], SFmode))
operands[1] = force_reg (SFmode, operands[0]);
emit_insn (gen_cirrus_truncsfsi2 (operands[0], operands[1]));
DONE;
}
")
(define_insn "*arm_fix_truncsfsi2" (define_insn "*arm_fix_truncsfsi2"
[(set (match_operand:SI 0 "s_register_operand" "=r") [(set (match_operand:SI 0 "s_register_operand" "=r")
(fix:SI (match_operand:SF 1 "s_register_operand" "f")))] (fix:SI (match_operand:SF 1 "s_register_operand" "f")))]
...@@ -2993,6 +3140,20 @@ ...@@ -2993,6 +3140,20 @@
(set_attr "predicable" "yes")] (set_attr "predicable" "yes")]
) )
(define_expand "fix_truncdfsi2"
[(set (match_operand:SI 0 "s_register_operand" "")
(fix:SI (match_operand:DF 1 "s_register_operand" "")))]
"TARGET_ARM && TARGET_ANY_HARD_FLOAT"
"
if (TARGET_CIRRUS)
{
if (!cirrus_fp_register (operands[1], DFmode))
operands[1] = force_reg (DFmode, operands[0]);
emit_insn (gen_cirrus_truncdfsi2 (operands[0], operands[1]));
DONE;
}
")
(define_insn "*arm_fix_truncdfsi2" (define_insn "*arm_fix_truncdfsi2"
[(set (match_operand:SI 0 "s_register_operand" "=r") [(set (match_operand:SI 0 "s_register_operand" "=r")
(fix:SI (match_operand:DF 1 "s_register_operand" "f")))] (fix:SI (match_operand:DF 1 "s_register_operand" "f")))]
...@@ -3004,6 +3165,14 @@ ...@@ -3004,6 +3165,14 @@
;; Truncation insns ;; Truncation insns
(define_expand "truncdfsf2"
[(set (match_operand:SF 0 "s_register_operand" "")
(float_truncate:SF
(match_operand:DF 1 "s_register_operand" "")))]
"TARGET_ARM && TARGET_ANY_HARD_FLOAT"
""
)
(define_insn "*arm_truncdfsf2" (define_insn "*arm_truncdfsf2"
[(set (match_operand:SF 0 "s_register_operand" "=f") [(set (match_operand:SF 0 "s_register_operand" "=f")
(float_truncate:SF (float_truncate:SF
......
gcc/config/arm/cirrus.md
...@@ -50,18 +50,6 @@ ...@@ -50,18 +50,6 @@
(set_attr "cirrus" "normal")] (set_attr "cirrus" "normal")]
) )
;; define_insn replaced by define_expand and define_insn
(define_expand "addsf3"
[(set (match_operand:SF 0 "s_register_operand" "")
(plus:SF (match_operand:SF 1 "s_register_operand" "")
(match_operand:SF 2 "fpu_add_operand" "")))]
"TARGET_ARM && TARGET_ANY_HARD_FLOAT"
"
if (TARGET_CIRRUS
&& !cirrus_fp_register (operands[2], SFmode))
operands[2] = force_reg (SFmode, operands[2]);
")
(define_insn "*cirrus_addsf3" (define_insn "*cirrus_addsf3"
[(set (match_operand:SF 0 "cirrus_fp_register" "=v") [(set (match_operand:SF 0 "cirrus_fp_register" "=v")
(plus:SF (match_operand:SF 1 "cirrus_fp_register" "v") (plus:SF (match_operand:SF 1 "cirrus_fp_register" "v")
...@@ -72,18 +60,6 @@ ...@@ -72,18 +60,6 @@
(set_attr "cirrus" "normal")] (set_attr "cirrus" "normal")]
) )
;; define_insn replaced by define_expand and define_insn
(define_expand "adddf3"
[(set (match_operand:DF 0 "s_register_operand" "")
(plus:DF (match_operand:DF 1 "s_register_operand" "")
(match_operand:DF 2 "fpu_add_operand" "")))]
"TARGET_ARM && TARGET_ANY_HARD_FLOAT"
"
if (TARGET_CIRRUS
&& !cirrus_fp_register (operands[2], DFmode))
operands[2] = force_reg (DFmode, operands[2]);
")
(define_insn "*cirrus_adddf3" (define_insn "*cirrus_adddf3"
[(set (match_operand:DF 0 "cirrus_fp_register" "=v") [(set (match_operand:DF 0 "cirrus_fp_register" "=v")
(plus:DF (match_operand:DF 1 "cirrus_fp_register" "v") (plus:DF (match_operand:DF 1 "cirrus_fp_register" "v")
...@@ -114,21 +90,6 @@ ...@@ -114,21 +90,6 @@
(set_attr "cirrus" "normal")] (set_attr "cirrus" "normal")]
) )
(define_expand "subsf3"
[(set (match_operand:SF 0 "s_register_operand" "")
(minus:SF (match_operand:SF 1 "fpu_rhs_operand" "")
(match_operand:SF 2 "fpu_rhs_operand" "")))]
"TARGET_ARM && TARGET_ANY_HARD_FLOAT"
"
if (TARGET_CIRRUS)
{
if (!cirrus_fp_register (operands[1], SFmode))
operands[1] = force_reg (SFmode, operands[1]);
if (!cirrus_fp_register (operands[2], SFmode))
operands[2] = force_reg (SFmode, operands[2]);
}
")
(define_insn "*cirrus_subsf3" (define_insn "*cirrus_subsf3"
[(set (match_operand:SF 0 "cirrus_fp_register" "=v") [(set (match_operand:SF 0 "cirrus_fp_register" "=v")
(minus:SF (match_operand:SF 1 "cirrus_fp_register" "v") (minus:SF (match_operand:SF 1 "cirrus_fp_register" "v")
...@@ -139,21 +100,6 @@ ...@@ -139,21 +100,6 @@
(set_attr "cirrus" "normal")] (set_attr "cirrus" "normal")]
) )
(define_expand "subdf3"
[(set (match_operand:DF 0 "s_register_operand" "")
(minus:DF (match_operand:DF 1 "fpu_rhs_operand" "")
(match_operand:DF 2 "fpu_rhs_operand" "")))]
"TARGET_ARM && TARGET_ANY_HARD_FLOAT"
"
if (TARGET_CIRRUS)
{
if (!cirrus_fp_register (operands[1], DFmode))
operands[1] = force_reg (DFmode, operands[1]);
if (!cirrus_fp_register (operands[2], DFmode))
operands[2] = force_reg (DFmode, operands[2]);
}
")
(define_insn "*cirrus_subdf3" (define_insn "*cirrus_subdf3"
[(set (match_operand:DF 0 "cirrus_fp_register" "=v") [(set (match_operand:DF 0 "cirrus_fp_register" "=v")
(minus:DF (match_operand:DF 1 "cirrus_fp_register" "v") (minus:DF (match_operand:DF 1 "cirrus_fp_register" "v")
...@@ -209,17 +155,6 @@ ...@@ -209,17 +155,6 @@
(set_attr "cirrus" "normal")] (set_attr "cirrus" "normal")]
) )
(define_expand "mulsf3"
[(set (match_operand:SF 0 "s_register_operand" "")
(mult:SF (match_operand:SF 1 "s_register_operand" "")
(match_operand:SF 2 "fpu_rhs_operand" "")))]
"TARGET_ARM && TARGET_ANY_HARD_FLOAT"
"
if (TARGET_CIRRUS
&& !cirrus_fp_register (operands[2], SFmode))
operands[2] = force_reg (SFmode, operands[2]);
")
(define_insn "*cirrus_mulsf3" (define_insn "*cirrus_mulsf3"
[(set (match_operand:SF 0 "cirrus_fp_register" "=v") [(set (match_operand:SF 0 "cirrus_fp_register" "=v")
(mult:SF (match_operand:SF 1 "cirrus_fp_register" "v") (mult:SF (match_operand:SF 1 "cirrus_fp_register" "v")
...@@ -230,17 +165,6 @@ ...@@ -230,17 +165,6 @@
(set_attr "cirrus" "normal")] (set_attr "cirrus" "normal")]
) )
(define_expand "muldf3"
[(set (match_operand:DF 0 "s_register_operand" "")
(mult:DF (match_operand:DF 1 "s_register_operand" "")
(match_operand:DF 2 "fpu_rhs_operand" "")))]
"TARGET_ARM && TARGET_ANY_HARD_FLOAT"
"
if (TARGET_CIRRUS
&& !cirrus_fp_register (operands[2], DFmode))
operands[2] = force_reg (DFmode, operands[2]);
")
(define_insn "*cirrus_muldf3" (define_insn "*cirrus_muldf3"
[(set (match_operand:DF 0 "cirrus_fp_register" "=v") [(set (match_operand:DF 0 "cirrus_fp_register" "=v")
(mult:DF (match_operand:DF 1 "cirrus_fp_register" "v") (mult:DF (match_operand:DF 1 "cirrus_fp_register" "v")
...@@ -331,13 +255,6 @@ ...@@ -331,13 +255,6 @@
[(set_attr "cirrus" "normal")] [(set_attr "cirrus" "normal")]
) )
(define_expand "negsf2"
[(set (match_operand:SF 0 "s_register_operand" "")
(neg:SF (match_operand:SF 1 "s_register_operand" "")))]
"TARGET_ARM && TARGET_ANY_HARD_FLOAT"
""
)
(define_insn "*cirrus_negsf2" (define_insn "*cirrus_negsf2"
[(set (match_operand:SF 0 "cirrus_fp_register" "=v") [(set (match_operand:SF 0 "cirrus_fp_register" "=v")
(neg:SF (match_operand:SF 1 "cirrus_fp_register" "v")))] (neg:SF (match_operand:SF 1 "cirrus_fp_register" "v")))]
...@@ -346,12 +263,6 @@ ...@@ -346,12 +263,6 @@
[(set_attr "cirrus" "normal")] [(set_attr "cirrus" "normal")]
) )
(define_expand "negdf2"
[(set (match_operand:DF 0 "s_register_operand" "")
(neg:DF (match_operand:DF 1 "s_register_operand" "")))]
"TARGET_ARM && TARGET_ANY_HARD_FLOAT"
"")
(define_insn "*cirrus_negdf2" (define_insn "*cirrus_negdf2"
[(set (match_operand:DF 0 "cirrus_fp_register" "=v") [(set (match_operand:DF 0 "cirrus_fp_register" "=v")
(neg:DF (match_operand:DF 1 "cirrus_fp_register" "v")))] (neg:DF (match_operand:DF 1 "cirrus_fp_register" "v")))]
...@@ -360,14 +271,6 @@ ...@@ -360,14 +271,6 @@
[(set_attr "cirrus" "normal")] [(set_attr "cirrus" "normal")]
) )
(define_expand "abssi2"
[(parallel
[(set (match_operand:SI 0 "s_register_operand" "")
(abs:SI (match_operand:SI 1 "s_register_operand" "")))
(clobber (reg:CC CC_REGNUM))])]
"TARGET_ARM"
"")
;; This doesn't really clobber the condition codes either. ;; This doesn't really clobber the condition codes either.
(define_insn "*cirrus_abssi2" (define_insn "*cirrus_abssi2"
[(set (match_operand:SI 0 "cirrus_fp_register" "=v") [(set (match_operand:SI 0 "cirrus_fp_register" "=v")
...@@ -378,12 +281,6 @@ ...@@ -378,12 +281,6 @@
[(set_attr "cirrus" "normal")] [(set_attr "cirrus" "normal")]
) )
(define_expand "abssf2"
[(set (match_operand:SF 0 "s_register_operand" "")
(abs:SF (match_operand:SF 1 "s_register_operand" "")))]
"TARGET_ARM && TARGET_ANY_HARD_FLOAT"
"")
(define_insn "*cirrus_abssf2" (define_insn "*cirrus_abssf2"
[(set (match_operand:SF 0 "cirrus_fp_register" "=v") [(set (match_operand:SF 0 "cirrus_fp_register" "=v")
(abs:SF (match_operand:SF 1 "cirrus_fp_register" "v")))] (abs:SF (match_operand:SF 1 "cirrus_fp_register" "v")))]
...@@ -392,12 +289,6 @@ ...@@ -392,12 +289,6 @@
[(set_attr "cirrus" "normal")] [(set_attr "cirrus" "normal")]
) )
(define_expand "absdf2"
[(set (match_operand:DF 0 "s_register_operand" "")
(abs:DF (match_operand:DF 1 "s_register_operand" "")))]
"TARGET_ARM && TARGET_ANY_HARD_FLOAT"
"")
(define_insn "*cirrus_absdf2" (define_insn "*cirrus_absdf2"
[(set (match_operand:DF 0 "cirrus_fp_register" "=v") [(set (match_operand:DF 0 "cirrus_fp_register" "=v")
(abs:DF (match_operand:DF 1 "cirrus_fp_register" "v")))] (abs:DF (match_operand:DF 1 "cirrus_fp_register" "v")))]
...@@ -406,18 +297,6 @@ ...@@ -406,18 +297,6 @@
[(set_attr "cirrus" "normal")] [(set_attr "cirrus" "normal")]
) )
(define_expand "floatsisf2"
[(set (match_operand:SF 0 "s_register_operand" "")
(float:SF (match_operand:SI 1 "s_register_operand" "")))]
"TARGET_ARM && TARGET_ANY_HARD_FLOAT"
"
if (TARGET_CIRRUS)
{
emit_insn (gen_cirrus_floatsisf2 (operands[0], operands[1]));
DONE;
}
")
;; Convert Cirrus-SI to Cirrus-SF ;; Convert Cirrus-SI to Cirrus-SF
(define_insn "cirrus_floatsisf2" (define_insn "cirrus_floatsisf2"
[(set (match_operand:SF 0 "cirrus_fp_register" "=v") [(set (match_operand:SF 0 "cirrus_fp_register" "=v")
...@@ -429,18 +308,6 @@ ...@@ -429,18 +308,6 @@
(set_attr "cirrus" "move")] (set_attr "cirrus" "move")]
) )
(define_expand "floatsidf2"
[(set (match_operand:DF 0 "s_register_operand" "")
(float:DF (match_operand:SI 1 "s_register_operand" "")))]
"TARGET_ARM && TARGET_ANY_HARD_FLOAT"
"
if (TARGET_CIRRUS)
{
emit_insn (gen_cirrus_floatsidf2 (operands[0], operands[1]));
DONE;
}
")
(define_insn "cirrus_floatsidf2" (define_insn "cirrus_floatsidf2"
[(set (match_operand:DF 0 "cirrus_fp_register" "=v") [(set (match_operand:DF 0 "cirrus_fp_register" "=v")
(float:DF (match_operand:SI 1 "s_register_operand" "r"))) (float:DF (match_operand:SI 1 "s_register_operand" "r")))
...@@ -465,22 +332,6 @@ ...@@ -465,22 +332,6 @@
"cfcvt64d%?\\t%V0, %V1" "cfcvt64d%?\\t%V0, %V1"
[(set_attr "cirrus" "normal")]) [(set_attr "cirrus" "normal")])
(define_expand "fix_truncsfsi2"
[(set (match_operand:SI 0 "s_register_operand" "")
(fix:SI (match_operand:SF 1 "s_register_operand" "")))]
"TARGET_ARM && TARGET_ANY_HARD_FLOAT"
"
if (TARGET_CIRRUS)
{
if (!cirrus_fp_register (operands[0], SImode))
operands[0] = force_reg (SImode, operands[0]);
if (!cirrus_fp_register (operands[1], SFmode))
operands[1] = force_reg (SFmode, operands[0]);
emit_insn (gen_cirrus_truncsfsi2 (operands[0], operands[1]));
DONE;
}
")
(define_insn "cirrus_truncsfsi2" (define_insn "cirrus_truncsfsi2"
[(set (match_operand:SI 0 "s_register_operand" "=r") [(set (match_operand:SI 0 "s_register_operand" "=r")
(fix:SI (match_operand:SF 1 "cirrus_fp_register" "v"))) (fix:SI (match_operand:SF 1 "cirrus_fp_register" "v")))
...@@ -491,20 +342,6 @@ ...@@ -491,20 +342,6 @@
(set_attr "cirrus" "normal")] (set_attr "cirrus" "normal")]
) )
(define_expand "fix_truncdfsi2"
[(set (match_operand:SI 0 "s_register_operand" "")
(fix:SI (match_operand:DF 1 "s_register_operand" "")))]
"TARGET_ARM && TARGET_ANY_HARD_FLOAT"
"
if (TARGET_CIRRUS)
{
if (!cirrus_fp_register (operands[1], DFmode))
operands[1] = force_reg (DFmode, operands[0]);
emit_insn (gen_cirrus_truncdfsi2 (operands[0], operands[1]));
DONE;
}
")
(define_insn "cirrus_truncdfsi2" (define_insn "cirrus_truncdfsi2"
[(set (match_operand:SI 0 "s_register_operand" "=r") [(set (match_operand:SI 0 "s_register_operand" "=r")
(fix:SI (match_operand:DF 1 "cirrus_fp_register" "v"))) (fix:SI (match_operand:DF 1 "cirrus_fp_register" "v")))
...@@ -514,14 +351,6 @@ ...@@ -514,14 +351,6 @@
[(set_attr "length" "8")] [(set_attr "length" "8")]
) )
(define_expand "truncdfsf2"
[(set (match_operand:SF 0 "s_register_operand" "")
(float_truncate:SF
(match_operand:DF 1 "s_register_operand" "")))]
"TARGET_ARM && TARGET_ANY_HARD_FLOAT"
""
)
(define_insn "*cirrus_truncdfsf2" (define_insn "*cirrus_truncdfsf2"
[(set (match_operand:SF 0 "cirrus_fp_register" "=v") [(set (match_operand:SF 0 "cirrus_fp_register" "=v")
(float_truncate:SF (float_truncate:SF
......
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