Commit 37e33ecb by Richard Earnshaw Committed by Richard Earnshaw

arm.opt (cirrus-fix-invalid-insns): Delete option.

	* arm.opt (cirrus-fix-invalid-insns): Delete option.
	* invoke.texi (cirrus-fix-invalid-insns): Remove documentation.

From-SVN: r194137
parent 5c972fb6
2012-12-04 Richard Earnshaw <rearnsha@arm.com>
* arm.opt (cirrus-fix-invalid-insns): Delete option.
* invoke.texi (cirrus-fix-invalid-insns): Remove documentation.
2012-12-04 Jakub Jelinek <jakub@redhat.com> 2012-12-04 Jakub Jelinek <jakub@redhat.com>
* tsan.c (instrument_expr): If expr_ptr isn't a gimple val, first * tsan.c (instrument_expr): If expr_ptr isn't a gimple val, first
...@@ -101,10 +101,6 @@ mcaller-super-interworking ...@@ -101,10 +101,6 @@ mcaller-super-interworking
Target Report Mask(CALLER_INTERWORKING) Target Report Mask(CALLER_INTERWORKING)
Thumb: Assume function pointers may go to non-Thumb aware code Thumb: Assume function pointers may go to non-Thumb aware code
mcirrus-fix-invalid-insns
Target Report Mask(CIRRUS_FIX_INVALID_INSNS)
Cirrus: Place NOPs to avoid invalid instruction combinations
mcpu= mcpu=
Target RejectNegative Joined Enum(processor_type) Var(arm_cpu_option) Init(arm_none) Target RejectNegative Joined Enum(processor_type) Var(arm_cpu_option) Init(arm_none)
Specify the name of the target CPU Specify the name of the target CPU
......
...@@ -506,7 +506,6 @@ Objective-C and Objective-C++ Dialects}. ...@@ -506,7 +506,6 @@ Objective-C and Objective-C++ Dialects}.
-msingle-pic-base -mno-single-pic-base @gol -msingle-pic-base -mno-single-pic-base @gol
-mpic-register=@var{reg} @gol -mpic-register=@var{reg} @gol
-mnop-fun-dllimport @gol -mnop-fun-dllimport @gol
-mcirrus-fix-invalid-insns -mno-cirrus-fix-invalid-insns @gol
-mpoke-function-name @gol -mpoke-function-name @gol
-mthumb -marm @gol -mthumb -marm @gol
-mtpcs-frame -mtpcs-leaf-frame @gol -mtpcs-frame -mtpcs-leaf-frame @gol
...@@ -11394,18 +11393,6 @@ before execution begins. ...@@ -11394,18 +11393,6 @@ before execution begins.
Specify the register to be used for PIC addressing. The default is R10 Specify the register to be used for PIC addressing. The default is R10
unless stack-checking is enabled, when R9 is used. unless stack-checking is enabled, when R9 is used.
@item -mcirrus-fix-invalid-insns
@opindex mcirrus-fix-invalid-insns
@opindex mno-cirrus-fix-invalid-insns
Insert NOPs into the instruction stream to in order to work around
problems with invalid Maverick instruction combinations. This option
is only valid if the @option{-mcpu=ep9312} option has been used to
enable generation of instructions for the Cirrus Maverick floating-point
co-processor. This option is not enabled by default, since the
problem is only present in older Maverick implementations. The default
can be re-enabled by use of the @option{-mno-cirrus-fix-invalid-insns}
switch.
@item -mpoke-function-name @item -mpoke-function-name
@opindex mpoke-function-name @opindex mpoke-function-name
Write the name of each function into the text section, directly Write the name of each function into the text section, directly
......
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