Provide more constraints for future use.

gcc/
	* config/nds32/constraints.md: Provide more constraints.
	* config/nds32/nds32.h (enum reg_class, REG_CLASS_NAMES,
	REG_CLASS_CONTENTS): Define R5_REG, R8_REG, and FRAME_POINTER_REG to
	support constraints usage.

Co-Authored-By: Kito Cheng <kito.cheng@gmail.com>

From-SVN: r254800

gcc/ChangeLog

 2017-11-16  Chung-Ju Wu  <jasonwucj@gmail.com>
+	    Kito Cheng  <kito.cheng@gmail.com>
+
+	* config/nds32/constraints.md: Provide more constraints.
+	* config/nds32/nds32.h (enum reg_class, REG_CLASS_NAMES,
+	REG_CLASS_CONTENTS): Define R5_REG, R8_REG, and FRAME_POINTER_REG to
+	support constraints usage.
+
+2017-11-16  Chung-Ju Wu  <jasonwucj@gmail.com>
 
 	* config/nds32/constants.md (UNSPEC_VOLATILE_FUNC_RETURN): Remove.
 

gcc/config/nds32/constraints.md

@@ -41,9 +41,52 @@
 (define_register_constraint "t" "R15_TA_REG"
   "Temporary Assist register $ta (i.e. $r15)")
 
+(define_register_constraint "e" "R8_REG"
+  "Function Entry register $r8)")
+
 (define_register_constraint "k" "STACK_REG"
   "Stack register $sp")
 
+(define_register_constraint "v" "R5_REG"
+  "Register $r5")
+
+(define_register_constraint "x" "FRAME_POINTER_REG"
+  "Frame pointer register $fp")
+
+(define_constraint "Iv00"
+  "Constant value 0"
+  (and (match_code "const_int")
+       (match_test "ival == 0")))
+
+(define_constraint "Iv01"
+  "Constant value 1"
+  (and (match_code "const_int")
+       (match_test "ival == 1")))
+
+(define_constraint "Iv02"
+  "Constant value 2"
+  (and (match_code "const_int")
+       (match_test "ival == 2")))
+
+(define_constraint "Iv04"
+  "Constant value 4"
+  (and (match_code "const_int")
+       (match_test "ival == 4")))
+
+(define_constraint "Iv08"
+  "Constant value 8"
+  (and (match_code "const_int")
+       (match_test "ival == 8")))
+
+(define_constraint "Iu01"
+  "Unsigned immediate 1-bit value"
+  (and (match_code "const_int")
+       (match_test "ival == 1 || ival == 0")))
+
+(define_constraint "Iu02"
+  "Unsigned immediate 2-bit value"
+  (and (match_code "const_int")
+       (match_test "ival < (1 << 2) && ival >= 0")))
 
 (define_constraint "Iu03"
   "Unsigned immediate 3-bit value"
@@ -103,6 +146,11 @@
        (match_test "ival < (1 << 9) && ival >= 0")))
 
 
+(define_constraint "Is08"
+  "Signed immediate 8-bit value"
+  (and (match_code "const_int")
+       (match_test "ival < (1 << 7) && ival >= -(1 << 7)")))
+
 (define_constraint "Is10"
   "Signed immediate 10-bit value"
   (and (match_code "const_int")
@@ -113,6 +161,10 @@
   (and (match_code "const_int")
        (match_test "ival < (1 << 10) && ival >= -(1 << 10)")))
 
+(define_constraint "Is14"
+  "Signed immediate 14-bit value"
+  (and (match_code "const_int")
+       (match_test "ival < (1 << 13) && ival >= -(1 << 13)")))
 
 (define_constraint "Is15"
   "Signed immediate 15-bit value"

gcc/config/nds32/nds32.h

@@ -613,8 +613,11 @@ enum nds32_builtins
 enum reg_class
 {
   NO_REGS,
+  R5_REG,
+  R8_REG,
   R15_TA_REG,
   STACK_REG,
+  FRAME_POINTER_REG,
   LOW_REGS,
   MIDDLE_REGS,
   HIGH_REGS,
@@ -629,8 +632,11 @@ enum reg_class
 #define REG_CLASS_NAMES \
 {                       \
   "NO_REGS",            \
+  "R5_REG",             \
+  "R8_REG",             \
   "R15_TA_REG",         \
   "STACK_REG",          \
+  "FRAME_POINTER_REG",  \
   "LOW_REGS",           \
   "MIDDLE_REGS",        \
   "HIGH_REGS",          \
@@ -641,9 +647,12 @@ enum reg_class
 
 #define REG_CLASS_CONTENTS \
 {                                                            \
-  {0x00000000, 0x00000000}, /* NO_REGS     :              */ \
-  {0x00008000, 0x00000000}, /* R15_TA_REG  : 15           */ \
-  {0x80000000, 0x00000000}, /* STACK_REG   : 31           */ \
+  {0x00000000, 0x00000000}, /* NO_REGS                    */ \
+  {0x00000020, 0x00000000}, /* R5_REG            : 5      */ \
+  {0x00000100, 0x00000000}, /* R8_REG            : 8      */ \
+  {0x00008000, 0x00000000}, /* R15_TA_REG        : 15     */ \
+  {0x80000000, 0x00000000}, /* STACK_REG         : 31     */ \
+  {0x10000000, 0x00000000}, /* FRAME_POINTER_REG : 28     */ \
   {0x000000ff, 0x00000000}, /* LOW_REGS    : 0-7          */ \
   {0x000f0fff, 0x00000000}, /* MIDDLE_REGS : 0-11, 16-19  */ \
   {0xfff07000, 0x00000000}, /* HIGH_REGS   : 12-14, 20-31 */ \