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riscv-gcc-1
Commit 35f3782f by Paolo Bonzini Committed by Paolo Bonzini
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gcc: 

2007-08-23  Paolo Bonzini  <bonzini@gnu.org>

	* config/i386/sse.md (*sse_and<mode>3, *sse_ior<mode>3,
	*sse_nand<mode>3, *sse_xor<mode>3): New.

gcc/testsuite:
2007-08-23  Paolo Bonzini  <bonzini@gnu.org>

	* gcc.target/i386/xorps-sse.c: New.
	* gcc.target/i386/xorps-sse2.c: New.

From-SVN: r127735
parent d97ac71d
Showing with 88 additions and 6 deletions
gcc/ChangeLog
2007-08-23 Paolo Bonzini <bonzini@gnu.org>
* config/i386/sse.md (*sse_and<mode>3, *sse_ior<mode>3,
*sse_nand<mode>3, *sse_xor<mode>3): New.
2007-08-23 Uros Bizjak <ubizjak@gmail.com>
* config/i386/i386.h (PRINT_OPERAND_PUNCT_VALID_P): Add ';' code.
......
gcc/config/i386/sse.md
......@@ -3773,10 +3773,21 @@
[(set (match_operand:SSEMODEI 0 "register_operand" "")
(and:SSEMODEI (match_operand:SSEMODEI 1 "nonimmediate_operand" "")
(match_operand:SSEMODEI 2 "nonimmediate_operand" "")))]
"TARGET_SSE2"
"TARGET_SSE"
"ix86_fixup_binary_operands_no_copy (AND, <MODE>mode, operands);")
(define_insn "*and<mode>3"
(define_insn "*sse_and<mode>3"
[(set (match_operand:SSEMODEI 0 "register_operand" "=x")
(and:SSEMODEI
(match_operand:SSEMODEI 1 "nonimmediate_operand" "%0")
(match_operand:SSEMODEI 2 "nonimmediate_operand" "xm")))]
"(TARGET_SSE && !TARGET_SSE2)
&& ix86_binary_operator_ok (AND, <MODE>mode, operands)"
"andps\t{%2, %0|%0, %2}"
[(set_attr "type" "sselog")
(set_attr "mode" "V4SF")])
(define_insn "*sse2_and<mode>3"
[(set (match_operand:SSEMODEI 0 "register_operand" "=x")
(and:SSEMODEI
(match_operand:SSEMODEI 1 "nonimmediate_operand" "%0")
......@@ -3787,6 +3798,16 @@
(set_attr "prefix_data16" "1")
(set_attr "mode" "TI")])
(define_insn "*sse_nand<mode>3"
[(set (match_operand:SSEMODEI 0 "register_operand" "=x")
(and:SSEMODEI
(not:SSEMODEI (match_operand:SSEMODEI 1 "register_operand" "0"))
(match_operand:SSEMODEI 2 "nonimmediate_operand" "xm")))]
"(TARGET_SSE && !TARGET_SSE2)"
"andnps\t{%2, %0|%0, %2}"
[(set_attr "type" "sselog")
(set_attr "mode" "V4SF")])
(define_insn "sse2_nand<mode>3"
[(set (match_operand:SSEMODEI 0 "register_operand" "=x")
(and:SSEMODEI
......@@ -3831,10 +3852,21 @@
[(set (match_operand:SSEMODEI 0 "register_operand" "")
(ior:SSEMODEI (match_operand:SSEMODEI 1 "nonimmediate_operand" "")
(match_operand:SSEMODEI 2 "nonimmediate_operand" "")))]
"TARGET_SSE2"
"TARGET_SSE"
"ix86_fixup_binary_operands_no_copy (IOR, <MODE>mode, operands);")
(define_insn "*ior<mode>3"
(define_insn "*sse_ior<mode>3"
[(set (match_operand:SSEMODEI 0 "register_operand" "=x")
(ior:SSEMODEI
(match_operand:SSEMODEI 1 "nonimmediate_operand" "%0")
(match_operand:SSEMODEI 2 "nonimmediate_operand" "xm")))]
"(TARGET_SSE && !TARGET_SSE2)
&& ix86_binary_operator_ok (IOR, <MODE>mode, operands)"
"orps\t{%2, %0|%0, %2}"
[(set_attr "type" "sselog")
(set_attr "mode" "V4SF")])
(define_insn "*sse2_ior<mode>3"
[(set (match_operand:SSEMODEI 0 "register_operand" "=x")
(ior:SSEMODEI
(match_operand:SSEMODEI 1 "nonimmediate_operand" "%0")
......@@ -3867,10 +3899,21 @@
[(set (match_operand:SSEMODEI 0 "register_operand" "")
(xor:SSEMODEI (match_operand:SSEMODEI 1 "nonimmediate_operand" "")
(match_operand:SSEMODEI 2 "nonimmediate_operand" "")))]
"TARGET_SSE2"
"TARGET_SSE"
"ix86_fixup_binary_operands_no_copy (XOR, <MODE>mode, operands);")
(define_insn "*xor<mode>3"
(define_insn "*sse_xor<mode>3"
[(set (match_operand:SSEMODEI 0 "register_operand" "=x")
(xor:SSEMODEI
(match_operand:SSEMODEI 1 "nonimmediate_operand" "%0")
(match_operand:SSEMODEI 2 "nonimmediate_operand" "xm")))]
"(TARGET_SSE && !TARGET_SSE2)
&& ix86_binary_operator_ok (XOR, <MODE>mode, operands)"
"xorps\t{%2, %0|%0, %2}"
[(set_attr "type" "sselog")
(set_attr "mode" "V4SF")])
(define_insn "*sse2_xor<mode>3"
[(set (match_operand:SSEMODEI 0 "register_operand" "=x")
(xor:SSEMODEI
(match_operand:SSEMODEI 1 "nonimmediate_operand" "%0")
......
gcc/testsuite/ChangeLog
......@@ -13,6 +13,11 @@
2007-08-23 Paolo Bonzini <bonzini@gnu.org>
* gcc.target/i386/xorps-sse.c: New.
* gcc.target/i386/xorps-sse2.c: New.
2007-08-23 Paolo Bonzini <bonzini@gnu.org>
* gcc.target/i386/cmov3.c: Fix scan-assembler.
* gcc.target/i386/cmov4.c: Fix scan-assembler.
* gcc.target/i386/xchg-2.c: Fix scan-assembler.
gcc/testsuite/gcc.target/i386/xorps-sse.c 0 → 100644
/* Test that we generate xorps instruction when pxor is not available. */
/* { dg-do compile } */
/* { dg-options "-O -msse -mno-sse2" } */
/* { dg-final { scan-assembler "xorps\[ \t\]" } } */
#define vector __attribute__ ((vector_size (16)))
vector int i(vector int f)
{
vector int g = { 0x80000000, 0, 0x80000000, 0 };
vector int f_int = (vector int) f;
return (f_int ^ g);
}
gcc/testsuite/gcc.target/i386/xorps-sse2.c 0 → 100644
/* Test that we generate xorps when the result is used in FP math. */
/* { dg-do compile } */
/* { dg-options "-O -msse2 -mno-sse3" } */
/* { dg-final { scan-assembler "xorps\[ \t\]" { xfail *-*-* } } } */
/* { dg-final { scan-assembler-not "pxor" { xfail *-*-* } } } */
#define vector __attribute__ ((vector_size (16)))
vector float i(vector float f, vector float h)
{
vector int g = { 0x80000000, 0, 0x80000000, 0 };
vector int f_int = (vector int) f;
return ((vector float) (f_int ^ g)) + h;
}
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