alpha.c (secondary_reload_class): For !BWX, sub-simode outputs require a register.

        * alpha.c (secondary_reload_class): For !BWX, sub-simode
        outputs require a register.

From-SVN: r30829

gcc/ChangeLog

+Wed Dec  8 03:45:40 1999  Richard Henderson  <rth@cygnus.com>
+
+	* alpha.c (secondary_reload_class): For !BWX, sub-simode
+	outputs require a register.
+
 1999-12-08  Brendan Kehoe  <brendan@cygnus.com>
 
 	* Makefile.in (FPBIT_FUNCS, DPBIT_FUNCS): Add _sf_to_usi

gcc/config/alpha/alpha.c

@@ -1065,17 +1065,21 @@ secondary_reload_class (class, mode, x, in)
      rtx x;
      int in;
 {
-  if ((GET_CODE (x) == MEM
-       || (GET_CODE (x) == REG && REGNO (x) >= FIRST_PSEUDO_REGISTER)
-       || (GET_CODE (x) == SUBREG
-	   && (GET_CODE (SUBREG_REG (x)) == MEM
-	       || (GET_CODE (SUBREG_REG (x)) == REG
-		   && REGNO (SUBREG_REG (x)) >= FIRST_PSEUDO_REGISTER))))
-      && ((class == FLOAT_REGS
-	   && (mode == SImode || mode == HImode || mode == QImode))
-	  || ((mode == QImode || mode == HImode)
-	      && ! TARGET_BWX && ! aligned_memory_operand (x, mode))))
-    return GENERAL_REGS;
+  if (GET_CODE (x) == MEM
+      || (GET_CODE (x) == REG && REGNO (x) >= FIRST_PSEUDO_REGISTER)
+      || (GET_CODE (x) == SUBREG
+	  && (GET_CODE (SUBREG_REG (x)) == MEM
+	      || (GET_CODE (SUBREG_REG (x)) == REG
+		  && REGNO (SUBREG_REG (x)) >= FIRST_PSEUDO_REGISTER))))
+    {
+      if (class == FLOAT_REGS && mode != DImode)
+	return GENERAL_REGS;
+      if ((mode == QImode || mode == HImode) && ! TARGET_BWX)
+	{
+	  if (!in || !aligned_memory_operand(x, mode))
+	    return GENERAL_REGS;
+	}
+    }
 
   if (class == FLOAT_REGS)
     {