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riscv-gcc-1
Commit 34d5fe77 by Oleg Endo
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Remove SH5 target regs. 

gcc/
	* config/sh/constraints.md (b): Remove constraint.
	* config/sh/predicates.md (arith_reg_operand): Remove TARGET_REGISTER_P.
	* config/sh/sh-modes.def (PDI): Remove.
	* config/sh/sh.c (sh_target_reg_class,
	sh_optimize_target_register_callee_saved): Remove functions.
	(sh_option_override): Don't set MASK_SAVE_ALL_TARGET_REGS.
	(sh_expand_epilogue): Update comment.
	(sh_hard_regno_mode_ok, sh_register_move_cost, calc_live_regs,
	sh_secondary_reload): Remove TARGET_REGS related code.
	* config/sh/sh.h (FIRST_TARGET_REG, LAST_TARGET_REG,
	TARGET_REGISTER_P): Remove macros.
	(SH_DBX_REGISTER_NUMBER, REG_ALLOC_ORDER): Remove target regs.
	* config/sh/sh.md (PR_MEDIA_REG, T_MEDIA_REG, FR23_REG, TR0_REG,
	TR1_REG, TR2_REG): Remove constants.
	* config/sh/sh.opt (SAVE_ALL_TARGET_REGS): Remove.

From-SVN: r236928
parent a1443cff
Showing with 19 additions and 99 deletions
gcc/ChangeLog
2016-05-31 Oleg Endo <olegendo@gcc.gnu.org> 2016-05-31 Oleg Endo <olegendo@gcc.gnu.org>
* config/sh/constraints.md (b): Remove constraint.
* config/sh/predicates.md (arith_reg_operand): Remove TARGET_REGISTER_P.
* config/sh/sh-modes.def (PDI): Remove.
* config/sh/sh.c (sh_target_reg_class,
sh_optimize_target_register_callee_saved): Remove functions.
(sh_option_override): Don't set MASK_SAVE_ALL_TARGET_REGS.
(sh_expand_epilogue): Update comment.
(sh_hard_regno_mode_ok, sh_register_move_cost, calc_live_regs,
sh_secondary_reload): Remove TARGET_REGS related code.
* config/sh/sh.h (FIRST_TARGET_REG, LAST_TARGET_REG,
TARGET_REGISTER_P): Remove macros.
(SH_DBX_REGISTER_NUMBER, REG_ALLOC_ORDER): Remove target regs.
* config/sh/sh.md (PR_MEDIA_REG, T_MEDIA_REG, FR23_REG, TR0_REG,
TR1_REG, TR2_REG): Remove constants.
* config/sh/sh.opt (SAVE_ALL_TARGET_REGS): Remove.
2016-05-31 Oleg Endo <olegendo@gcc.gnu.org>
* config/sh/sh.md (adddi3, subdi3, negdi2, abs<mode>2): Remove * config/sh/sh.md (adddi3, subdi3, negdi2, abs<mode>2): Remove
define_expand patterns. define_expand patterns.
(adddi3_compact): Rename to adddi3. (adddi3_compact): Rename to adddi3.
......
gcc/config/sh/constraints.md
...@@ -62,9 +62,6 @@ ...@@ -62,9 +62,6 @@
(define_register_constraint "a" "ALL_REGS" (define_register_constraint "a" "ALL_REGS"
"@internal") "@internal")
(define_register_constraint "b" "TARGET_REGS"
"Branch target registers.")
(define_register_constraint "c" "FPSCR_REGS" (define_register_constraint "c" "FPSCR_REGS"
"Floating-point status register.") "Floating-point status register.")
......
gcc/config/sh/predicates.md
...@@ -34,7 +34,6 @@ ...@@ -34,7 +34,6 @@
return 1; return 1;
return (regno != T_REG && regno != PR_REG return (regno != T_REG && regno != PR_REG
&& ! TARGET_REGISTER_P (regno)
&& regno != FPUL_REG && regno != FPSCR_REG && regno != FPUL_REG && regno != FPSCR_REG
&& regno != MACH_REG && regno != MACL_REG); && regno != MACH_REG && regno != MACL_REG);
} }
......
gcc/config/sh/sh-modes.def
...@@ -17,9 +17,6 @@ You should have received a copy of the GNU General Public License ...@@ -17,9 +17,6 @@ You should have received a copy of the GNU General Public License
along with GCC; see the file COPYING3. If not see along with GCC; see the file COPYING3. If not see
<http://www.gnu.org/licenses/>. */ <http://www.gnu.org/licenses/>. */
/* PDI mode is used to represent a function address in a target register. */
PARTIAL_INT_MODE (DI, 64, PDI);
/* Vector modes. */ /* Vector modes. */
VECTOR_MODE (INT, QI, 2); /* V2QI */ VECTOR_MODE (INT, QI, 2); /* V2QI */
VECTOR_MODES (INT, 4); /* V4QI V2HI */ VECTOR_MODES (INT, 4); /* V4QI V2HI */
......
gcc/config/sh/sh.c
...@@ -234,8 +234,6 @@ static int sh_variable_issue (FILE *, int, rtx_insn *, int); ...@@ -234,8 +234,6 @@ static int sh_variable_issue (FILE *, int, rtx_insn *, int);
static bool sh_function_ok_for_sibcall (tree, tree); static bool sh_function_ok_for_sibcall (tree, tree);
static bool sh_can_follow_jump (const rtx_insn *, const rtx_insn *); static bool sh_can_follow_jump (const rtx_insn *, const rtx_insn *);
static reg_class_t sh_target_reg_class (void);
static bool sh_optimize_target_register_callee_saved (bool);
static bool sh_ms_bitfield_layout_p (const_tree); static bool sh_ms_bitfield_layout_p (const_tree);
static void sh_init_builtins (void); static void sh_init_builtins (void);
...@@ -465,11 +463,6 @@ static const struct attribute_spec sh_attribute_table[] = ...@@ -465,11 +463,6 @@ static const struct attribute_spec sh_attribute_table[] =
#undef TARGET_CAN_FOLLOW_JUMP #undef TARGET_CAN_FOLLOW_JUMP
#define TARGET_CAN_FOLLOW_JUMP sh_can_follow_jump #define TARGET_CAN_FOLLOW_JUMP sh_can_follow_jump
#undef TARGET_BRANCH_TARGET_REGISTER_CLASS
#define TARGET_BRANCH_TARGET_REGISTER_CLASS sh_target_reg_class
#undef TARGET_BRANCH_TARGET_REGISTER_CALLEE_SAVED
#define TARGET_BRANCH_TARGET_REGISTER_CALLEE_SAVED \
sh_optimize_target_register_callee_saved
#undef TARGET_MS_BITFIELD_LAYOUT_P #undef TARGET_MS_BITFIELD_LAYOUT_P
#define TARGET_MS_BITFIELD_LAYOUT_P sh_ms_bitfield_layout_p #define TARGET_MS_BITFIELD_LAYOUT_P sh_ms_bitfield_layout_p
...@@ -800,8 +793,6 @@ sh_option_override (void) ...@@ -800,8 +793,6 @@ sh_option_override (void)
int regno; int regno;
SUBTARGET_OVERRIDE_OPTIONS; SUBTARGET_OVERRIDE_OPTIONS;
if (optimize > 1 && !optimize_size)
target_flags |= MASK_SAVE_ALL_TARGET_REGS;
sh_cpu = PROCESSOR_SH1; sh_cpu = PROCESSOR_SH1;
assembler_dialect = 0; assembler_dialect = 0;
...@@ -7037,30 +7028,6 @@ calc_live_regs (HARD_REG_SET *live_regs_mask) ...@@ -7037,30 +7028,6 @@ calc_live_regs (HARD_REG_SET *live_regs_mask)
if (nosave_low_regs && reg == R8_REG) if (nosave_low_regs && reg == R8_REG)
break; break;
} }
/* If we have a target register optimization pass after prologue / epilogue
threading, we need to assume all target registers will be live even if
they aren't now. */
if (flag_branch_target_load_optimize2 && TARGET_SAVE_ALL_TARGET_REGS)
for (reg = LAST_TARGET_REG; reg >= FIRST_TARGET_REG; reg--)
if ((! call_really_used_regs[reg] || interrupt_handler)
&& ! TEST_HARD_REG_BIT (*live_regs_mask, reg))
{
SET_HARD_REG_BIT (*live_regs_mask, reg);
count += GET_MODE_SIZE (REGISTER_NATURAL_MODE (reg));
}
/* If this is an interrupt handler, we don't have any call-clobbered
registers we can conveniently use for target register save/restore.
Make sure we save at least one general purpose register when we need
to save target registers. */
if (interrupt_handler
&& hard_reg_set_intersect_p (*live_regs_mask,
reg_class_contents[TARGET_REGS])
&& ! hard_reg_set_intersect_p (*live_regs_mask,
reg_class_contents[GENERAL_REGS]))
{
SET_HARD_REG_BIT (*live_regs_mask, R0_REG);
count += GET_MODE_SIZE (REGISTER_NATURAL_MODE (R0_REG));
}
return count; return count;
} }
...@@ -7317,9 +7284,6 @@ sh_expand_epilogue (bool sibcall_p) ...@@ -7317,9 +7284,6 @@ sh_expand_epilogue (bool sibcall_p)
emit_insn (gen_sp_switch_2 ()); emit_insn (gen_sp_switch_2 ());
/* Tell flow the insn that pops PR isn't dead. */ /* Tell flow the insn that pops PR isn't dead. */
/* PR_REG will never be live in SHmedia mode, and we don't need to
USE PR_MEDIA_REG, since it will be explicitly copied to TR0_REG
by the return pattern. */
if (TEST_HARD_REG_BIT (live_regs_mask, PR_REG)) if (TEST_HARD_REG_BIT (live_regs_mask, PR_REG))
emit_use (gen_rtx_REG (SImode, PR_REG)); emit_use (gen_rtx_REG (SImode, PR_REG));
} }
...@@ -10014,19 +9978,6 @@ sh_dfa_new_cycle (FILE *sched_dump ATTRIBUTE_UNUSED, ...@@ -10014,19 +9978,6 @@ sh_dfa_new_cycle (FILE *sched_dump ATTRIBUTE_UNUSED,
return 0; return 0;
} }
static reg_class_t
sh_target_reg_class (void)
{
return NO_REGS;
}
static bool
sh_optimize_target_register_callee_saved (bool after_prologue_epilogue_gen
ATTRIBUTE_UNUSED)
{
return false;
}
static bool static bool
sh_ms_bitfield_layout_p (const_tree record_type ATTRIBUTE_UNUSED) sh_ms_bitfield_layout_p (const_tree record_type ATTRIBUTE_UNUSED)
{ {
...@@ -10582,9 +10533,6 @@ sh_hard_regno_mode_ok (unsigned int regno, machine_mode mode) ...@@ -10582,9 +10533,6 @@ sh_hard_regno_mode_ok (unsigned int regno, machine_mode mode)
if (XD_REGISTER_P (regno)) if (XD_REGISTER_P (regno))
return mode == DFmode; return mode == DFmode;
if (TARGET_REGISTER_P (regno))
return (mode == DImode || mode == SImode || mode == PDImode);
if (regno == PR_REG) if (regno == PR_REG)
return mode == SImode; return mode == SImode;
...@@ -10726,10 +10674,6 @@ sh_register_move_cost (machine_mode mode, ...@@ -10726,10 +10674,6 @@ sh_register_move_cost (machine_mode mode,
&& (dstclass == PR_REGS || dstclass == MAC_REGS))) && (dstclass == PR_REGS || dstclass == MAC_REGS)))
return 7; return 7;
if ((srcclass == TARGET_REGS && ! REGCLASS_HAS_GENERAL_REG (dstclass))
|| ((dstclass) == TARGET_REGS && ! REGCLASS_HAS_GENERAL_REG (srcclass)))
return 20;
if ((srcclass == FPSCR_REGS && ! REGCLASS_HAS_GENERAL_REG (dstclass)) if ((srcclass == FPSCR_REGS && ! REGCLASS_HAS_GENERAL_REG (dstclass))
|| (dstclass == FPSCR_REGS && ! REGCLASS_HAS_GENERAL_REG (srcclass))) || (dstclass == FPSCR_REGS && ! REGCLASS_HAS_GENERAL_REG (srcclass)))
return 4; return 4;
...@@ -11324,17 +11268,11 @@ sh_secondary_reload (bool in_p, rtx x, reg_class_t rclass_i, ...@@ -11324,17 +11268,11 @@ sh_secondary_reload (bool in_p, rtx x, reg_class_t rclass_i,
return GENERAL_REGS; return GENERAL_REGS;
return NO_REGS; // LRA wants NO_REGS here, it used to be FPUL_REGS; return NO_REGS; // LRA wants NO_REGS here, it used to be FPUL_REGS;
} }
if (rclass == TARGET_REGS
&& !satisfies_constraint_Csy (x)
&& (!REG_P (x) || ! GENERAL_REGISTER_P (REGNO (x))))
return GENERAL_REGS;
if ((rclass == MAC_REGS || rclass == PR_REGS) if ((rclass == MAC_REGS || rclass == PR_REGS)
&& REG_P (x) && ! GENERAL_REGISTER_P (REGNO (x)) && REG_P (x) && ! GENERAL_REGISTER_P (REGNO (x))
&& rclass != REGNO_REG_CLASS (REGNO (x))) && rclass != REGNO_REG_CLASS (REGNO (x)))
return GENERAL_REGS; return GENERAL_REGS;
if (rclass != GENERAL_REGS && REG_P (x)
&& TARGET_REGISTER_P (REGNO (x)))
return GENERAL_REGS;
/* If here fall back to loading FPUL register through general registers. /* If here fall back to loading FPUL register through general registers.
This case can happen when movsi_ie insn is picked initially to This case can happen when movsi_ie insn is picked initially to
......
gcc/config/sh/sh.h
...@@ -585,8 +585,6 @@ extern char sh_additional_register_names[ADDREGNAMES_SIZE] \ ...@@ -585,8 +585,6 @@ extern char sh_additional_register_names[ADDREGNAMES_SIZE] \
#define LAST_FP_REG (FIRST_FP_REG + (TARGET_SH2E ? 15 : -1)) #define LAST_FP_REG (FIRST_FP_REG + (TARGET_SH2E ? 15 : -1))
#define FIRST_XD_REG XD0_REG #define FIRST_XD_REG XD0_REG
#define LAST_XD_REG (FIRST_XD_REG + ((TARGET_SH4 && TARGET_FMOVD) ? 7 : -1)) #define LAST_XD_REG (FIRST_XD_REG + ((TARGET_SH4 && TARGET_FMOVD) ? 7 : -1))
#define FIRST_TARGET_REG TR0_REG
#define LAST_TARGET_REG (FIRST_TARGET_REG + (-1))
/* Registers that can be accessed through bank0 or bank1 depending on sr.md. */ /* Registers that can be accessed through bank0 or bank1 depending on sr.md. */
#define FIRST_BANKED_REG R0_REG #define FIRST_BANKED_REG R0_REG
...@@ -623,9 +621,6 @@ extern char sh_additional_register_names[ADDREGNAMES_SIZE] \ ...@@ -623,9 +621,6 @@ extern char sh_additional_register_names[ADDREGNAMES_SIZE] \
|| (REGNO) == MACH_REG || (REGNO) == MACL_REG \ || (REGNO) == MACH_REG || (REGNO) == MACL_REG \
|| (REGNO) == FPSCR_MODES_REG || (REGNO) == FPSCR_STAT_REG) || (REGNO) == FPSCR_MODES_REG || (REGNO) == FPSCR_STAT_REG)
#define TARGET_REGISTER_P(REGNO) \
((int) (REGNO) >= FIRST_TARGET_REG && (int) (REGNO) <= LAST_TARGET_REG)
#define VALID_REGISTER_P(REGNO) \ #define VALID_REGISTER_P(REGNO) \
(GENERAL_REGISTER_P (REGNO) || FP_REGISTER_P (REGNO) \ (GENERAL_REGISTER_P (REGNO) || FP_REGISTER_P (REGNO) \
|| XD_REGISTER_P (REGNO) \ || XD_REGISTER_P (REGNO) \
...@@ -1037,8 +1032,6 @@ extern enum reg_class regno_reg_class[FIRST_PSEUDO_REGISTER]; ...@@ -1037,8 +1032,6 @@ extern enum reg_class regno_reg_class[FIRST_PSEUDO_REGISTER];
44, 45, 46, 47, 48, 49, 50, 51, \ 44, 45, 46, 47, 48, 49, 50, 51, \
52, 53, 54, 55, 56, 57, 58, 59, \ 52, 53, 54, 55, 56, 57, 58, 59, \
/* FPUL */ 150, \ /* FPUL */ 150, \
/* SH5 branch target registers */ \
128,129,130,131,132,133,134,135, \
/* Fixed registers */ \ /* Fixed registers */ \
15, 16, 24, 25, 26, 27, 63,144, \ 15, 16, 24, 25, 26, 27, 63,144, \
145,146,147,148,149,152,153,154,155 } 145,146,147,148,149,152,153,154,155 }
...@@ -1698,13 +1691,6 @@ extern bool current_function_interrupt; ...@@ -1698,13 +1691,6 @@ extern bool current_function_interrupt;
register exists, so we should return -1 for invalid register numbers. */ register exists, so we should return -1 for invalid register numbers. */
#define DBX_REGISTER_NUMBER(REGNO) SH_DBX_REGISTER_NUMBER (REGNO) #define DBX_REGISTER_NUMBER(REGNO) SH_DBX_REGISTER_NUMBER (REGNO)
/* SHcompact PR_REG used to use the encoding 241, and SHcompact FP registers
used to use the encodings 245..260, but that doesn't make sense:
PR_REG and PR_MEDIA_REG are actually the same register, and likewise
the FP registers stay the same when switching between compact and media
mode. Hence, we also need to use the same dwarf frame columns.
Likewise, we need to support unwind information for SHmedia registers
even in compact code. */
#define SH_DBX_REGISTER_NUMBER(REGNO) \ #define SH_DBX_REGISTER_NUMBER(REGNO) \
(IN_RANGE ((REGNO), \ (IN_RANGE ((REGNO), \
(unsigned HOST_WIDE_INT) FIRST_GENERAL_REG, \ (unsigned HOST_WIDE_INT) FIRST_GENERAL_REG, \
...@@ -1716,12 +1702,8 @@ extern bool current_function_interrupt; ...@@ -1716,12 +1702,8 @@ extern bool current_function_interrupt;
? ((unsigned) (REGNO) - FIRST_FP_REG + 25) \ ? ((unsigned) (REGNO) - FIRST_FP_REG + 25) \
: XD_REGISTER_P (REGNO) \ : XD_REGISTER_P (REGNO) \
? ((unsigned) (REGNO) - FIRST_XD_REG + 87) \ ? ((unsigned) (REGNO) - FIRST_XD_REG + 87) \
: TARGET_REGISTER_P (REGNO) \
? ((unsigned) (REGNO) - FIRST_TARGET_REG + 68) \
: (REGNO) == PR_REG \ : (REGNO) == PR_REG \
? (17) \ ? (17) \
: (REGNO) == PR_MEDIA_REG \
? ((unsigned) -1) \
: (REGNO) == GBR_REG \ : (REGNO) == GBR_REG \
? (18) \ ? (18) \
: (REGNO) == MACH_REG \ : (REGNO) == MACH_REG \
......
gcc/config/sh/sh.md
...@@ -86,9 +86,6 @@ ...@@ -86,9 +86,6 @@
(FP_REG 14) (FP_REG 14)
(SP_REG 15) (SP_REG 15)
(PR_MEDIA_REG 18)
(T_MEDIA_REG 19)
(R0_REG 0) (R0_REG 0)
(R1_REG 1) (R1_REG 1)
(R2_REG 2) (R2_REG 2)
...@@ -108,11 +105,6 @@ ...@@ -108,11 +105,6 @@
(DR0_REG 64) (DR0_REG 64)
(DR2_REG 66) (DR2_REG 66)
(DR4_REG 68) (DR4_REG 68)
(FR23_REG 87)
(TR0_REG 128)
(TR1_REG 129)
(TR2_REG 130)
(XD0_REG 136) (XD0_REG 136)
......
gcc/config/sh/sh.opt
...@@ -37,9 +37,6 @@ Mask(HARD_SH2A_DOUBLE) ...@@ -37,9 +37,6 @@ Mask(HARD_SH2A_DOUBLE)
;; Set if compiling for SH4 hardware (to be used for insn costs etc.) ;; Set if compiling for SH4 hardware (to be used for insn costs etc.)
Mask(HARD_SH4) Mask(HARD_SH4)
;; Set if we should save all target registers.
Mask(SAVE_ALL_TARGET_REGS)
m1 m1
Target RejectNegative Mask(SH1) Condition(SUPPORT_SH1) Target RejectNegative Mask(SH1) Condition(SUPPORT_SH1)
Generate SH1 code. Generate SH1 code.
......
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