Change all TFmode patterns to have XFmode.

(movxf recognizer, frame version): Use movt, ldt, and stt.
(movxf recognizer, non-frame version): Delete.
(extenddfxf2): Delete * before f constraint.
(extendsfxf2): Likewise.

From-SVN: r9741

gcc/config/i960/i960.md

@@ -1918,65 +1918,41 @@
 
 ;; Tetra (16 byte) float support.
 
-(define_insn "cmptf"
+(define_expand "cmpxf"
   [(set (reg:CC 36)
-	(compare:CC (match_operand:TF 0 "register_operand" "f")
-		    (match_operand:TF 1 "nonmemory_operand" "fG")))]
+	(compare:CC (match_operand:XF 0 "register_operand" "")
+		    (match_operand:XF 1 "nonmemory_operand" "")))]
   "TARGET_NUMERICS"
-  "cmpr	%0,%1"
+  "
+{
+  i960_compare_op0 = operands[0];
+  i960_compare_op1 = operands[1];
+  DONE;
+}")
+
+(define_insn ""
+  [(set (reg:CC 36)
+	(compare:CC (match_operand:XF 0 "register_operand" "f")
+		    (match_operand:XF 1 "nonmemory_operand" "fGH")))]
+  "TARGET_NUMERICS"
+  "cmpr %0,%1"
   [(set_attr "type" "fpcc")])
 
-(define_expand "movtf"
-  [(set (match_operand:TF 0 "general_operand" "")
-	(match_operand:TF 1 "fpmove_src_operand" ""))]
+(define_expand "movxf"
+  [(set (match_operand:XF 0 "general_operand" "")
+	(match_operand:XF 1 "fpmove_src_operand" ""))]
   ""
   "
 {
-  if (emit_move_sequence (operands, TFmode))
+  if (emit_move_sequence (operands, XFmode))
     DONE;
 }")
 
 (define_insn ""
-  [(set (match_operand:TF 0 "general_operand" "=r,*f,d,d,m,o")
-	(match_operand:TF 1 "fpmove_src_operand" "r,GH,F,m,d,G"))]
-  "(current_function_args_size == 0
-    && rtx_equal_function_value_matters == 0)
-   && (register_operand (operands[0], TFmode)
-       || register_operand (operands[1], TFmode)
-       || operands[1] == CONST0_RTX (TFmode))"
-  "*
-{
-  switch (which_alternative)
-    {
-    case 0:
-      if (FP_REG_P (operands[0]) || FP_REG_P (operands[1]))
-	return \"movre	%1,%0\";
-      else
-	return \"movq	%1,%0\";
-    case 1:
-      return \"movre	%1,%0\";
-    case 2:
-      return i960_output_ldconst (operands[0], operands[1]);
-    case 3:
-      return \"ldq	%1,%0\";
-    case 4:
-      return \"stq	%1,%0\";
-    case 5:
-      operands[1] = adj_offsettable_operand (operands[0], 4);
-      operands[2] = adj_offsettable_operand (operands[0], 8);
-      operands[3] = adj_offsettable_operand (operands[0], 12);
-      return \"st	g14,%0\;st	g14,%1\;st	g14,%2\;st	g14,%3\";
-    }
-}"
-  [(set_attr "type" "move,move,load,fpload,fpstore,fpstore")])
-
-(define_insn ""
-  [(set (match_operand:TF 0 "general_operand" "=r,*f,d,d,m")
-	(match_operand:TF 1 "fpmove_src_operand" "r,GH,F,m,d"))]
-  "(current_function_args_size != 0
-    || rtx_equal_function_value_matters != 0)
-   && (register_operand (operands[0], TFmode)
-       || register_operand (operands[1], TFmode))"
+  [(set (match_operand:XF 0 "general_operand" "=r,f,d,d,m")
+	(match_operand:XF 1 "fpmove_src_operand" "r,GH,F,m,d"))]
+  "register_operand (operands[0], XFmode)
+   || register_operand (operands[1], XFmode)"
   "*
 {
   switch (which_alternative)
@@ -1991,16 +1967,16 @@
     case 2:
       return i960_output_ldconst (operands[0], operands[1]);
     case 3:
-      return \"ldq	%1,%0\";
+      return \"ldt	%1,%0\";
     case 4:
-      return \"stq	%1,%0\";
+      return \"stt	%1,%0\";
     }
 }"
   [(set_attr "type" "move,move,load,fpload,fpstore")])
 
-(define_insn "extendsftf2"
-  [(set (match_operand:TF 0 "register_operand" "=*f,d")
-	(float_extend:TF
+(define_insn "extendsfxf2"
+  [(set (match_operand:XF 0 "register_operand" "=f,d")
+	(float_extend:XF
 	 (match_operand:SF 1 "register_operand" "d,f")))]
   "TARGET_NUMERICS"
   "@
@@ -2008,9 +1984,9 @@
   movre	%1,%0"
   [(set_attr "type" "fpmove")])
 
-(define_insn "extenddftf2"
-  [(set (match_operand:TF 0 "register_operand" "=*f,d")
-	(float_extend:TF
+(define_insn "extenddfxf2"
+  [(set (match_operand:XF 0 "register_operand" "=f,d")
+	(float_extend:XF
 	 (match_operand:DF 1 "register_operand" "d,f")))]
   "TARGET_NUMERICS"
   "@
@@ -2018,85 +1994,85 @@
   movre	%1,%0"
   [(set_attr "type" "fpmove")])
 
-(define_insn "trunctfdf2"
+(define_insn "truncxfdf2"
   [(set (match_operand:DF 0 "register_operand" "=d")
 	(float_truncate:DF
-	 (match_operand:TF 1 "register_operand" "f")))]
+	 (match_operand:XF 1 "register_operand" "f")))]
   "TARGET_NUMERICS"
   "movrl	%1,%0"
   [(set_attr "type" "fpmove")])
 
-(define_insn "trunctfsf2"
+(define_insn "truncxfsf2"
   [(set (match_operand:SF 0 "register_operand" "=d")
 	(float_truncate:SF
-	 (match_operand:TF 1 "register_operand" "f")))]
+	 (match_operand:XF 1 "register_operand" "f")))]
   "TARGET_NUMERICS"
   "movr	%1,%0"
   [(set_attr "type" "fpmove")])
 
-(define_insn "floatsitf2"
-  [(set (match_operand:TF 0 "register_operand" "=f")
-	(float:TF (match_operand:SI 1 "register_operand" "d")))]
+(define_insn "floatsixf2"
+  [(set (match_operand:XF 0 "register_operand" "=f")
+	(float:XF (match_operand:SI 1 "register_operand" "d")))]
   "TARGET_NUMERICS"
   "cvtir	%1,%0"
   [(set_attr "type" "fpcvt")])
 
-(define_insn "fix_trunctfsi2"
+(define_insn "fix_truncxfsi2"
   [(set (match_operand:SI 0 "register_operand" "=d")
-	(fix:SI (fix:TF (match_operand:TF 1 "register_operand" "f"))))]
+	(fix:SI (fix:XF (match_operand:XF 1 "register_operand" "f"))))]
   "TARGET_NUMERICS"
   "cvtzri	%1,%0"
   [(set_attr "type" "fpcvt")])
 
-(define_insn "fixuns_trunctfsi2"
+(define_insn "fixuns_truncxfsi2"
   [(set (match_operand:SI 0 "register_operand" "=d")
-	(unsigned_fix:SI (fix:TF (match_operand:TF 1 "register_operand" "f"))))]
+	(unsigned_fix:SI (fix:XF (match_operand:XF 1 "register_operand" "f"))))]
   "TARGET_NUMERICS"
   "cvtzri	%1,%0"
   [(set_attr "type" "fpcvt")])
 
-(define_insn "addtf3"
-  [(set (match_operand:TF 0 "register_operand" "=f")
-	(plus:TF (match_operand:TF 1 "nonmemory_operand" "%fG")
-		 (match_operand:TF 2 "nonmemory_operand" "fG")))]
+(define_insn "addxf3"
+  [(set (match_operand:XF 0 "register_operand" "=f")
+	(plus:XF (match_operand:XF 1 "nonmemory_operand" "%fGH")
+		 (match_operand:XF 2 "nonmemory_operand" "fGH")))]
   "TARGET_NUMERICS"
   "addr	%1,%2,%0"
   [(set_attr "type" "fpadd")])
 
-(define_insn "subtf3"
-  [(set (match_operand:TF 0 "register_operand" "=f")
-	(minus:TF (match_operand:TF 1 "nonmemory_operand" "fG")
-		  (match_operand:TF 2 "nonmemory_operand" "fG")))]
+(define_insn "subxf3"
+  [(set (match_operand:XF 0 "register_operand" "=f")
+	(minus:XF (match_operand:XF 1 "nonmemory_operand" "fGH")
+		  (match_operand:XF 2 "nonmemory_operand" "fGH")))]
   "TARGET_NUMERICS"
   "subr	%2,%1,%0"
   [(set_attr "type" "fpadd")])
 
-(define_insn "multf3"
-  [(set (match_operand:TF 0 "register_operand" "=f")
-	(mult:TF (match_operand:TF 1 "nonmemory_operand" "%fG")
-		 (match_operand:TF 2 "nonmemory_operand" "fG")))]
+(define_insn "mulxf3"
+  [(set (match_operand:XF 0 "register_operand" "=f")
+	(mult:XF (match_operand:XF 1 "nonmemory_operand" "%fGH")
+		 (match_operand:XF 2 "nonmemory_operand" "fGH")))]
   "TARGET_NUMERICS"
   "mulr	%1,%2,%0"
   [(set_attr "type" "fpmul")])
 
-(define_insn "divtf3"
-  [(set (match_operand:TF 0 "register_operand" "=f")
-	(div:TF (match_operand:TF 1 "nonmemory_operand" "fG")
-		(match_operand:TF 2 "nonmemory_operand" "fG")))]
+(define_insn "divxf3"
+  [(set (match_operand:XF 0 "register_operand" "=f")
+	(div:XF (match_operand:XF 1 "nonmemory_operand" "fGH")
+		(match_operand:XF 2 "nonmemory_operand" "fGH")))]
   "TARGET_NUMERICS"
   "divr	%2,%1,%0"
   [(set_attr "type" "fpdiv")])
 
-(define_insn "negtf2"
-  [(set (match_operand:TF 0 "register_operand" "=f")
-	(neg:TF (match_operand:TF 1 "register_operand" "f")))]
+(define_insn "negxf2"
+  [(set (match_operand:XF 0 "register_operand" "=f")
+	(neg:XF (match_operand:XF 1 "register_operand" "f")))]
   "TARGET_NUMERICS"
   "subr	%1,0f0.0,%0"
   [(set_attr "type" "fpadd")])
 
-(define_insn "abstf2"
-  [(set (match_operand:TF 0 "register_operand" "=f")
-	(abs:TF (match_operand:TF 1 "register_operand" "f")))]
+(define_insn "absxf2"
+  [(set (match_operand:XF 0 "register_operand" "=f")
+	(abs:XF (match_operand:XF 1 "register_operand" "f")))]
   "(TARGET_NUMERICS)"
   "cpysre	%1,0f0.0,%0"
   [(set_attr "type" "fpmove")])