config.gcc (hppa*-*-*): Remove MASK_BIG_SWITCH from CPU default.

	* config.gcc (hppa*-*-*): Remove MASK_BIG_SWITCH from CPU default.
	* config/pa/pa.opt: Make mbig-switch a no-op.
	* config/pa/pa.h (TARGET_DEFAULT): Remove MASK_BIG_SWITCH.
	(CASE_VECTOR_MODE): Always return SImode.
	(ASM_OUTPUT_ADDR_VEC_ELT, ASM_OUTPUT_ADDR_DIFF_ELT): Remove code
	for the !TARGET_BIG_SWITCH case.
	* config/pa/pa-linux.h: Likewise.
	* config/pa/pa-openbsd.h: Likewise.
	* config/pa/pa-hpux.h: Define TARGET_DEFAULT to 0.
	* config/pa/pa.md (short_jump): Remove define_insn.
	(casesi): Remove code for the !TARGET_BIG_SWITCH case.
	(casesi0): Remove define_insn.
	(type): Remove btable_branch.
	(pa_combine_type): Likewise.
	(in_nullified_branch_delay): Likewise.
	(in_call_delay): Likewise.
	(define_delay): Likewise.
	(define_insn_reservation "Z3"): Likewise.
	(define_insn_reservation "Z4"): Likewise.
	* config/pa/pa.c  (pa_reorg): Remove code for !TARGET_BIG_SWITCH.
	(pa_adjust_insn_length): Remove adjustment for btable branches.
	* doc/invoke.texi (HPPA Options): Delete documentation for mbig-switch
	and mno-big-switch


Co-Authored-By: John David Anglin <dave.anglin@nrc-cnrc.gc.ca>

From-SVN: r198612

gcc/ChangeLog

+2013-05-05  Steven Bosscher  <steven@gcc.gnu.org>
+	    John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
+
+	* config.gcc (hppa*-*-*): Remove MASK_BIG_SWITCH from CPU default.
+	* config/pa/pa.opt: Make mbig-switch a no-op.
+	* config/pa/pa.h (TARGET_DEFAULT): Remove MASK_BIG_SWITCH.
+	(CASE_VECTOR_MODE): Always return SImode.
+	(ASM_OUTPUT_ADDR_VEC_ELT, ASM_OUTPUT_ADDR_DIFF_ELT): Remove code
+	for the !TARGET_BIG_SWITCH case.
+	* config/pa/pa-linux.h: Likewise.
+	* config/pa/pa-openbsd.h: Likewise.
+	* config/pa/pa-hpux.h: Define TARGET_DEFAULT to 0.
+	* config/pa/pa.md (short_jump): Remove define_insn.
+	(casesi): Remove code for the !TARGET_BIG_SWITCH case.
+	(casesi0): Remove define_insn.
+	(type): Remove btable_branch.
+	(pa_combine_type): Likewise.
+	(in_nullified_branch_delay): Likewise.
+	(in_call_delay): Likewise.
+	(define_delay): Likewise.
+	(define_insn_reservation "Z3"): Likewise.
+	(define_insn_reservation "Z4"): Likewise.
+	* config/pa/pa.c  (pa_reorg): Remove code for !TARGET_BIG_SWITCH.
+	(pa_adjust_insn_length): Remove adjustment for btable branches.
+	* doc/invoke.texi (HPPA Options): Delete documentation for mbig-switch
+	and mno-big-switch
+
 2013-05-05  Uros Bizjak  <ubizjak@gmail.com>
 
 	* config/i386/sse.md (*vec_extract<ssevecmodelower>_0): Merge

gcc/config.gcc

@@ -3698,10 +3698,9 @@ case ${target} in
 		;;
 
 	hppa*-*-*)
-		target_cpu_default2="MASK_BIG_SWITCH"
 		if test x$gas = xyes
 		then
-			target_cpu_default2="${target_cpu_default2}|MASK_GAS|MASK_JUMP_IN_DELAY"
+			target_cpu_default2="MASK_GAS|MASK_JUMP_IN_DELAY"
 		fi
 		;;
 

gcc/config/pa/pa-hpux.h

@@ -25,7 +25,7 @@ along with GCC; see the file COPYING3.  If not see
 #define HPUX_LONG_DOUBLE_LIBRARY 1
 
 #undef TARGET_DEFAULT
-#define TARGET_DEFAULT MASK_BIG_SWITCH
+#define TARGET_DEFAULT 0
 
 /* Make GCC agree with types.h.  */
 #undef SIZE_TYPE

gcc/config/pa/pa-linux.h

@@ -78,17 +78,11 @@ along with GCC; see the file COPYING3.  If not see
 
 #undef ASM_OUTPUT_ADDR_VEC_ELT
 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
-  if (TARGET_BIG_SWITCH)					\
-    fprintf (FILE, "\t.word .L%d\n", VALUE);			\
-  else								\
-    fprintf (FILE, "\tb .L%d\n\tnop\n", VALUE)
+  fprintf (FILE, "\t.word .L%d\n", VALUE)
 
 #undef ASM_OUTPUT_ADDR_DIFF_ELT
 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
-  if (TARGET_BIG_SWITCH)					\
-    fprintf (FILE, "\t.word .L%d-.L%d\n", VALUE, REL);		\
-  else								\
-    fprintf (FILE, "\tb .L%d\n\tnop\n", VALUE)
+  fprintf (FILE, "\t.word .L%d-.L%d\n", VALUE, REL)
 
 /* Use the default.  */
 #undef ASM_OUTPUT_LABEL

gcc/config/pa/pa-openbsd.h

@@ -49,17 +49,11 @@ along with GCC; see the file COPYING3.  If not see
 
 #undef ASM_OUTPUT_ADDR_VEC_ELT
 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
-  if (TARGET_BIG_SWITCH)					\
-    fprintf (FILE, "\t.word .L%d\n", VALUE);			\
-  else								\
-    fprintf (FILE, "\tb .L%d\n\tnop\n", VALUE)
+  fprintf (FILE, "\t.word .L%d\n", VALUE)
 
 #undef ASM_OUTPUT_ADDR_DIFF_ELT
 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
-  if (TARGET_BIG_SWITCH)					\
-    fprintf (FILE, "\t.word .L%d-.L%d\n", VALUE, REL);		\
-  else								\
-    fprintf (FILE, "\tb .L%d\n\tnop\n", VALUE)
+  fprintf (FILE, "\t.word .L%d-.L%d\n", VALUE, REL)
 
 /* Use the default.  */
 #undef ASM_OUTPUT_LABEL

gcc/config/pa/pa.c

@@ -4927,20 +4927,14 @@ pa_adjust_insn_length (rtx insn, int length)
 	}
     }
 
-  /* Jumps inside switch tables which have unfilled delay slots need
-     adjustment.  */
-  if (JUMP_P (insn)
-      && GET_CODE (pat) == PARALLEL
-      && get_attr_type (insn) == TYPE_BTABLE_BRANCH)
-    length += 4;
   /* Block move pattern.  */
-  else if (NONJUMP_INSN_P (insn)
-	   && GET_CODE (pat) == PARALLEL
-	   && GET_CODE (XVECEXP (pat, 0, 0)) == SET
-	   && GET_CODE (XEXP (XVECEXP (pat, 0, 0), 0)) == MEM
-	   && GET_CODE (XEXP (XVECEXP (pat, 0, 0), 1)) == MEM
-	   && GET_MODE (XEXP (XVECEXP (pat, 0, 0), 0)) == BLKmode
-	   && GET_MODE (XEXP (XVECEXP (pat, 0, 0), 1)) == BLKmode)
+  if (NONJUMP_INSN_P (insn)
+      && GET_CODE (pat) == PARALLEL
+      && GET_CODE (XVECEXP (pat, 0, 0)) == SET
+      && GET_CODE (XEXP (XVECEXP (pat, 0, 0), 0)) == MEM
+      && GET_CODE (XEXP (XVECEXP (pat, 0, 0), 1)) == MEM
+      && GET_MODE (XEXP (XVECEXP (pat, 0, 0), 0)) == BLKmode
+      && GET_MODE (XEXP (XVECEXP (pat, 0, 0), 1)) == BLKmode)
     length += compute_movmem_length (insn) - 4;
   /* Block clear pattern.  */
   else if (NONJUMP_INSN_P (insn)
@@ -8947,36 +8941,10 @@ pa_following_call (rtx insn)
 /* We use this hook to perform a PA specific optimization which is difficult
    to do in earlier passes.
 
-   We want the delay slots of branches within jump tables to be filled.
-   None of the compiler passes at the moment even has the notion that a
-   PA jump table doesn't contain addresses, but instead contains actual
-   instructions!
-
-   Because we actually jump into the table, the addresses of each entry
-   must stay constant in relation to the beginning of the table (which
-   itself must stay constant relative to the instruction to jump into
-   it).  I don't believe we can guarantee earlier passes of the compiler
-   will adhere to those rules.
-
-   So, late in the compilation process we find all the jump tables, and
-   expand them into real code -- e.g. each entry in the jump table vector
-   will get an appropriate label followed by a jump to the final target.
-
-   Reorg and the final jump pass can then optimize these branches and
-   fill their delay slots.  We end up with smaller, more efficient code.
-
-   The jump instructions within the table are special; we must be able
-   to identify them during assembly output (if the jumps don't get filled
-   we need to emit a nop rather than nullifying the delay slot)).  We
-   identify jumps in switch tables by using insns with the attribute
-   type TYPE_BTABLE_BRANCH.
-
-   We also surround the jump table itself with BEGIN_BRTAB and END_BRTAB
-   insns.  This serves two purposes, first it prevents jump.c from
-   noticing that the last N entries in the table jump to the instruction
-   immediately after the table and deleting the jumps.  Second, those
-   insns mark where we should emit .begin_brtab and .end_brtab directives
-   when using GAS (allows for better link time optimizations).  */
+   We surround the jump table itself with BEGIN_BRTAB and END_BRTAB
+   insns.  Those insns mark where we should emit .begin_brtab and
+   .end_brtab directives when using GAS.  This allows for better link
+   time optimizations.  */
 
 static void
 pa_reorg (void)
@@ -8988,83 +8956,23 @@ pa_reorg (void)
   if (pa_cpu < PROCESSOR_8000)
     pa_combine_instructions ();
 
-
-  /* This is fairly cheap, so always run it if optimizing.  */
-  if (optimize > 0 && !TARGET_BIG_SWITCH)
-    {
-      /* Find and explode all ADDR_VEC or ADDR_DIFF_VEC insns.  */
-      for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
-	{
-	  rtx pattern, tmp, location, label;
-	  unsigned int length, i;
-
-	  /* Find an ADDR_VEC or ADDR_DIFF_VEC insn to explode.  */
-	  if (! JUMP_TABLE_DATA_P (insn))
-	    continue;
-
-	  /* Emit marker for the beginning of the branch table.  */
-	  emit_insn_before (gen_begin_brtab (), insn);
-
-	  pattern = PATTERN (insn);
-	  location = PREV_INSN (insn);
-          length = XVECLEN (pattern, GET_CODE (pattern) == ADDR_DIFF_VEC);
-
-	  for (i = 0; i < length; i++)
-	    {
-	      /* Emit a label before each jump to keep jump.c from
-		 removing this code.  */
-	      tmp = gen_label_rtx ();
-	      LABEL_NUSES (tmp) = 1;
-	      emit_label_after (tmp, location);
-	      location = NEXT_INSN (location);
-
-	      if (GET_CODE (pattern) == ADDR_VEC)
-		label = XEXP (XVECEXP (pattern, 0, i), 0);
-	      else
-		label = XEXP (XVECEXP (pattern, 1, i), 0);
-
-	      tmp = gen_short_jump (label);
-
-	      /* Emit the jump itself.  */
-	      tmp = emit_jump_insn_after (tmp, location);
-	      JUMP_LABEL (tmp) = label;
-	      LABEL_NUSES (label)++;
-	      location = NEXT_INSN (location);
-
-	      /* Emit a BARRIER after the jump.  */
-	      emit_barrier_after (location);
-	      location = NEXT_INSN (location);
-	    }
-
-	  /* Emit marker for the end of the branch table.  */
-	  emit_insn_before (gen_end_brtab (), location);
-	  location = NEXT_INSN (location);
-	  emit_barrier_after (location);
-
-	  /* Delete the ADDR_VEC or ADDR_DIFF_VEC.  */
-	  delete_insn (insn);
-	}
-    }
-  else
-    {
-      /* Still need brtab marker insns.  FIXME: the presence of these
-	 markers disables output of the branch table to readonly memory,
-	 and any alignment directives that might be needed.  Possibly,
-	 the begin_brtab insn should be output before the label for the
-	 table.  This doesn't matter at the moment since the tables are
-	 always output in the text section.  */
-      for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
-	{
-	  /* Find an ADDR_VEC insn.  */
-	  if (! JUMP_TABLE_DATA_P (insn))
-	    continue;
-
-	  /* Now generate markers for the beginning and end of the
-	     branch table.  */
-	  emit_insn_before (gen_begin_brtab (), insn);
-	  emit_insn_after (gen_end_brtab (), insn);
-	}
-    }
+    /* Still need brtab marker insns.  FIXME: the presence of these
+       markers disables output of the branch table to readonly memory,
+       and any alignment directives that might be needed.  Possibly,
+       the begin_brtab insn should be output before the label for the
+       table.  This doesn't matter at the moment since the tables are
+       always output in the text section.  */
+    for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
+      {
+	/* Find an ADDR_VEC insn.  */
+	if (! JUMP_TABLE_DATA_P (insn))
+	  continue;
+
+	/* Now generate markers for the beginning and end of the
+	   branch table.  */
+	emit_insn_before (gen_begin_brtab (), insn);
+	emit_insn_after (gen_end_brtab (), insn);
+      }
 }
 
 /* The PA has a number of odd instructions which can perform multiple

gcc/config/pa/pa.h

@@ -114,7 +114,7 @@ extern unsigned long total_code_bytes;
 #define TARGET_HPUX_UNWIND_LIBRARY 0
 
 #ifndef TARGET_DEFAULT
-#define TARGET_DEFAULT (MASK_GAS | MASK_JUMP_IN_DELAY | MASK_BIG_SWITCH)
+#define TARGET_DEFAULT (MASK_GAS | MASK_JUMP_IN_DELAY)
 #endif
 
 #ifndef TARGET_CPU_DEFAULT
@@ -984,11 +984,9 @@ do {									     \
 #define FUNCTION_NAME_P(NAME)  (*(NAME) == '@')
 
 /* Specify the machine mode that this machine uses for the index in the
-   tablejump instruction.  For small tables, an element consists of a
-   ia-relative branch and its delay slot.  When -mbig-switch is specified,
-   we use a 32-bit absolute address for non-pic code, and a 32-bit offset
-   for both 32 and 64-bit pic code.  */
-#define CASE_VECTOR_MODE (TARGET_BIG_SWITCH ? SImode : DImode)
+   tablejump instruction.  We use a 32-bit absolute address for non-pic code,
+   and a 32-bit offset for 32 and 64-bit pic code.  */
+#define CASE_VECTOR_MODE SImode
 
 /* Jump tables must be 32-bit aligned, no matter the size of the element.  */
 #define ADDR_VEC_ALIGN(ADDR_VEC) 2
@@ -1165,13 +1163,16 @@ do {									     \
   pa_output_ascii ((FILE), (P), (SIZE))
 
 /* Jump tables are always placed in the text section.  Technically, it
-   is possible to put them in the readonly data section when -mbig-switch
-   is specified.  This has the benefit of getting the table out of .text
-   and reducing branch lengths as a result.  The downside is that an
-   additional insn (addil) is needed to access the table when generating
-   PIC code.  The address difference table also has to use 32-bit
-   pc-relative relocations.  Currently, GAS does not support these
-   relocations, although it is easily modified to do this operation.
+   is possible to put them in the readonly data section.  This has the
+   benefit of getting the table out of .text and reducing branch lengths
+   as a result.
+
+   The downside is that an additional insn (addil) is needed to access
+   the table when generating PIC code.  The address difference table
+   also has to use 32-bit pc-relative relocations.  Currently, GAS does
+   not support these relocations, although it is easily modified to do
+   this operation.
+
    The table entries need to look like "$L1+(.+8-$L0)-$PIC_pcrel$0"
    when using ELF GAS.  A simple difference can be used when using
    SOM GAS or the HP assembler.  The final downside is GDB complains
@@ -1182,20 +1183,14 @@ do {									     \
 /* This is how to output an element of a case-vector that is absolute.  */
 
 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE)  \
-  if (TARGET_BIG_SWITCH)						\
-    fprintf (FILE, "\t.word L$%04d\n", VALUE);				\
-  else									\
-    fprintf (FILE, "\tb L$%04d\n\tnop\n", VALUE)
+  fprintf (FILE, "\t.word L$%04d\n", VALUE)
 
 /* This is how to output an element of a case-vector that is relative. 
    Since we always place jump tables in the text section, the difference
    is absolute and requires no relocation.  */
 
 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL)  \
-  if (TARGET_BIG_SWITCH)						\
-    fprintf (FILE, "\t.word L$%04d-L$%04d\n", VALUE, REL);		\
-  else									\
-    fprintf (FILE, "\tb L$%04d\n\tnop\n", VALUE)
+  fprintf (FILE, "\t.word L$%04d-L$%04d\n", VALUE, REL)
 
 /* This is how to output an assembler line that says to advance the
    location counter to a multiple of 2**LOG bytes.  */

gcc/config/pa/pa.md

@@ -123,7 +123,7 @@
 ;; type "binary" insns have two input operands (1,2) and one output (0)
 
 (define_attr "type"
-  "move,unary,binary,shift,nullshift,compare,load,store,uncond_branch,btable_branch,branch,cbranch,fbranch,call,sibcall,dyncall,fpload,fpstore,fpalu,fpcc,fpmulsgl,fpmuldbl,fpdivsgl,fpdivdbl,fpsqrtsgl,fpsqrtdbl,multi,milli,sh_func_adrs,parallel_branch,fpstore_load,store_fpload"
+  "move,unary,binary,shift,nullshift,compare,load,store,uncond_branch,branch,cbranch,fbranch,call,sibcall,dyncall,fpload,fpstore,fpalu,fpcc,fpmulsgl,fpmuldbl,fpdivsgl,fpdivdbl,fpsqrtsgl,fpsqrtdbl,multi,milli,sh_func_adrs,parallel_branch,fpstore_load,store_fpload"
   (const_string "binary"))
 
 (define_attr "pa_combine_type"
@@ -166,7 +166,7 @@
 ;; For conditional branches. Frame related instructions are not allowed
 ;; because they confuse the unwind support.
 (define_attr "in_branch_delay" "false,true"
-  (if_then_else (and (eq_attr "type" "!uncond_branch,btable_branch,branch,cbranch,fbranch,call,sibcall,dyncall,multi,milli,sh_func_adrs,parallel_branch")
+  (if_then_else (and (eq_attr "type" "!uncond_branch,branch,cbranch,fbranch,call,sibcall,dyncall,multi,milli,sh_func_adrs,parallel_branch")
 		     (eq_attr "length" "4")
 		     (not (match_test "RTX_FRAME_RELATED_P (insn)")))
 		(const_string "true")
@@ -175,7 +175,7 @@
 ;; Disallow instructions which use the FPU since they will tie up the FPU
 ;; even if the instruction is nullified.
 (define_attr "in_nullified_branch_delay" "false,true"
-  (if_then_else (and (eq_attr "type" "!uncond_branch,btable_branch,branch,cbranch,fbranch,call,sibcall,dyncall,multi,milli,sh_func_adrs,fpcc,fpalu,fpmulsgl,fpmuldbl,fpdivsgl,fpdivdbl,fpsqrtsgl,fpsqrtdbl,parallel_branch")
+  (if_then_else (and (eq_attr "type" "!uncond_branch,branch,cbranch,fbranch,call,sibcall,dyncall,multi,milli,sh_func_adrs,fpcc,fpalu,fpmulsgl,fpmuldbl,fpdivsgl,fpdivdbl,fpsqrtsgl,fpsqrtdbl,parallel_branch")
 		     (eq_attr "length" "4")
 		     (not (match_test "RTX_FRAME_RELATED_P (insn)")))
 		(const_string "true")
@@ -184,7 +184,7 @@
 ;; For calls and millicode calls.  Allow unconditional branches in the
 ;; delay slot.
 (define_attr "in_call_delay" "false,true"
-  (cond [(and (eq_attr "type" "!uncond_branch,btable_branch,branch,cbranch,fbranch,call,sibcall,dyncall,multi,milli,sh_func_adrs,parallel_branch")
+  (cond [(and (eq_attr "type" "!uncond_branch,branch,cbranch,fbranch,call,sibcall,dyncall,multi,milli,sh_func_adrs,parallel_branch")
 	      (eq_attr "length" "4")
 	      (not (match_test "RTX_FRAME_RELATED_P (insn)")))
 	   (const_string "true")
@@ -208,7 +208,7 @@
   [(eq_attr "in_call_delay" "true") (nil) (nil)])
 
 ;; Return and other similar instructions.
-(define_delay (eq_attr "type" "btable_branch,branch,parallel_branch")
+(define_delay (eq_attr "type" "branch,parallel_branch")
   [(eq_attr "in_branch_delay" "true") (nil) (nil)])
 
 ;; Floating point conditional branch delay slot description.
@@ -657,7 +657,7 @@
 ;; to assume have zero latency.
 (define_insn_reservation "Z3" 0
   (and
-    (eq_attr "type" "!load,fpload,store,fpstore,uncond_branch,btable_branch,branch,cbranch,fbranch,call,sibcall,dyncall,multi,milli,sh_func_adrs,parallel_branch,fpcc,fpalu,fpmulsgl,fpmuldbl,fpsqrtsgl,fpsqrtdbl,fpdivsgl,fpdivdbl,fpstore_load,store_fpload")
+    (eq_attr "type" "!load,fpload,store,fpstore,uncond_branch,branch,cbranch,fbranch,call,sibcall,dyncall,multi,milli,sh_func_adrs,parallel_branch,fpcc,fpalu,fpmulsgl,fpmuldbl,fpsqrtsgl,fpsqrtdbl,fpdivsgl,fpdivdbl,fpstore_load,store_fpload")
     (eq_attr "cpu" "8000"))
   "inm_8000,rnm_8000")
 
@@ -665,7 +665,7 @@
 ;; retirement unit.
 (define_insn_reservation "Z4" 0
   (and
-    (eq_attr "type" "uncond_branch,btable_branch,branch,cbranch,fbranch,call,sibcall,dyncall,multi,milli,sh_func_adrs,parallel_branch")
+    (eq_attr "type" "uncond_branch,branch,cbranch,fbranch,call,sibcall,dyncall,multi,milli,sh_func_adrs,parallel_branch")
     (eq_attr "cpu" "8000"))
   "inm0_8000+inm1_8000,rnm0_8000+rnm1_8000")
 
@@ -6959,16 +6959,6 @@
   [(set_attr "type" "branch")
    (set_attr "length" "4")])
 
-;;; This jump is used in branch tables where the insn length is fixed.
-;;; The length of this insn is adjusted if the delay slot is not filled.
-(define_insn "short_jump"
-  [(set (pc) (label_ref (match_operand 0 "" "")))
-   (const_int 0)]
-  ""
-  "b%* %l0%#"
-  [(set_attr "type" "btable_branch")
-   (set_attr "length" "4")])
-
 ;; Subroutines of "casesi".
 ;; operand 0 is index
 ;; operand 1 is the minimum bound
@@ -7028,34 +7018,15 @@
       operands[0] = index;
     }
 
-  if (TARGET_BIG_SWITCH)
-    {
-      if (TARGET_64BIT)
-	emit_jump_insn (gen_casesi64p (operands[0], operands[3]));
-      else if (flag_pic)
-	emit_jump_insn (gen_casesi32p (operands[0], operands[3]));
-      else
-	emit_jump_insn (gen_casesi32 (operands[0], operands[3]));
-    }
+  if (TARGET_64BIT)
+    emit_jump_insn (gen_casesi64p (operands[0], operands[3]));
+  else if (flag_pic)
+    emit_jump_insn (gen_casesi32p (operands[0], operands[3]));
   else
-    emit_jump_insn (gen_casesi0 (operands[0], operands[3]));
+    emit_jump_insn (gen_casesi32 (operands[0], operands[3]));
   DONE;
 }")
 
-;;; The rtl for this pattern doesn't accurately describe what the insn
-;;; actually does, particularly when case-vector elements are exploded
-;;; in pa_reorg.  However, the initial SET in these patterns must show
-;;; the connection of the insn to the following jump table.
-(define_insn "casesi0"
-  [(set (pc) (mem:SI (plus:SI
-		       (mult:SI (match_operand:SI 0 "register_operand" "r")
-				(const_int 4))
-		       (label_ref (match_operand 1 "" "")))))]
-  ""
-  "blr,n %0,%%r0\;nop"
-  [(set_attr "type" "multi")
-   (set_attr "length" "8")])
-
 ;;; 32-bit code, absolute branch table.
 (define_insn "casesi32"
   [(set (pc) (mem:SI (plus:SI

gcc/config/pa/pa.opt

@@ -38,8 +38,8 @@ Target RejectNegative
 Generate PA2.0 code (requires binutils 2.10 or later)
 
 mbig-switch
-Target Report Mask(BIG_SWITCH)
-Generate code for huge switch statements
+Target Ignore
+Does nothing.  Preserved for backward compatibility.
 
 mdisable-fpregs
 Target Report Mask(DISABLE_FPREGS)

gcc/doc/invoke.texi

@@ -618,11 +618,11 @@ Objective-C and Objective-C++ Dialects}.
 
 @emph{HPPA Options}
 @gccoptlist{-march=@var{architecture-type} @gol
--mbig-switch  -mdisable-fpregs  -mdisable-indexing @gol
+-mdisable-fpregs  -mdisable-indexing @gol
 -mfast-indirect-calls  -mgas  -mgnu-ld   -mhp-ld @gol
 -mfixed-range=@var{register-range} @gol
 -mjump-in-delay -mlinker-opt -mlong-calls @gol
--mlong-load-store  -mno-big-switch  -mno-disable-fpregs @gol
+-mlong-load-store  -mno-disable-fpregs @gol
 -mno-disable-indexing  -mno-fast-indirect-calls  -mno-gas @gol
 -mno-jump-in-delay  -mno-long-load-store @gol
 -mno-portable-runtime  -mno-soft-float @gol
@@ -13510,12 +13510,6 @@ other way around.
 @opindex mpa-risc-2-0
 Synonyms for @option{-march=1.0}, @option{-march=1.1}, and @option{-march=2.0} respectively.
 
-@item -mbig-switch
-@opindex mbig-switch
-Generate code suitable for big switch tables.  Use this option only if
-the assembler/linker complain about out-of-range branches within a switch
-table.
-
 @item -mjump-in-delay
 @opindex mjump-in-delay
 Fill delay slots of function calls with unconditional jump instructions