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riscv-gcc-1
Commit 332fddad by Alan Lawrence Committed by Alan Lawrence
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Add execution tests of ARM UZP Intrinsics. 

	* gcc.target/arm/simd/vuzpqf32_1.c: New file.
	* gcc.target/arm/simd/vuzpqp16_1.c: New file.
	* gcc.target/arm/simd/vuzpqp8_1.c: New file.
	* gcc.target/arm/simd/vuzpqs16_1.c: New file.
	* gcc.target/arm/simd/vuzpqs32_1.c: New file.
	* gcc.target/arm/simd/vuzpqs8_1.c: New file.
	* gcc.target/arm/simd/vuzpqu16_1.c: New file.
	* gcc.target/arm/simd/vuzpqu32_1.c: New file.
	* gcc.target/arm/simd/vuzpqu8_1.c: New file.
	* gcc.target/arm/simd/vuzpf32_1.c: New file.
	* gcc.target/arm/simd/vuzpp16_1.c: New file.
	* gcc.target/arm/simd/vuzpp8_1.c: New file.
	* gcc.target/arm/simd/vuzps16_1.c: New file.
	* gcc.target/arm/simd/vuzps32_1.c: New file.
	* gcc.target/arm/simd/vuzps8_1.c: New file.
	* gcc.target/arm/simd/vuzpu16_1.c: New file.
	* gcc.target/arm/simd/vuzpu32_1.c: New file.
	* gcc.target/arm/simd/vuzpu8_1.c: New file.

From-SVN: r209947
parent ad5b68e0
Showing with 237 additions and 0 deletions
gcc/testsuite/ChangeLog
2014-04-30 Alan Lawrence <alan.lawrence@arm.com> 2014-04-30 Alan Lawrence <alan.lawrence@arm.com>
* gcc.target/arm/simd/vuzpqf32_1.c: New file.
* gcc.target/arm/simd/vuzpqp16_1.c: New file.
* gcc.target/arm/simd/vuzpqp8_1.c: New file.
* gcc.target/arm/simd/vuzpqs16_1.c: New file.
* gcc.target/arm/simd/vuzpqs32_1.c: New file.
* gcc.target/arm/simd/vuzpqs8_1.c: New file.
* gcc.target/arm/simd/vuzpqu16_1.c: New file.
* gcc.target/arm/simd/vuzpqu32_1.c: New file.
* gcc.target/arm/simd/vuzpqu8_1.c: New file.
* gcc.target/arm/simd/vuzpf32_1.c: New file.
* gcc.target/arm/simd/vuzpp16_1.c: New file.
* gcc.target/arm/simd/vuzpp8_1.c: New file.
* gcc.target/arm/simd/vuzps16_1.c: New file.
* gcc.target/arm/simd/vuzps32_1.c: New file.
* gcc.target/arm/simd/vuzps8_1.c: New file.
* gcc.target/arm/simd/vuzpu16_1.c: New file.
* gcc.target/arm/simd/vuzpu32_1.c: New file.
* gcc.target/arm/simd/vuzpu8_1.c: New file.
2014-04-30 Alan Lawrence <alan.lawrence@arm.com>
* gcc.target/aarch64/vuzps32_1.c: Expect zip1/2 insn rather than uzp1/2. * gcc.target/aarch64/vuzps32_1.c: Expect zip1/2 insn rather than uzp1/2.
* gcc.target/aarch64/vuzpu32_1.c: Likewise. * gcc.target/aarch64/vuzpu32_1.c: Likewise.
* gcc.target/aarch64/vuzpf32_1.c: Likewise. * gcc.target/aarch64/vuzpf32_1.c: Likewise.
......
gcc/testsuite/gcc.target/arm/simd/vuzpf32_1.c 0 → 100644
/* Test the `vuzpf32' ARM Neon intrinsic. */
/* { dg-do run } */
/* { dg-require-effective-target arm_neon_ok } */
/* { dg-options "-save-temps -O1 -fno-inline" } */
/* { dg-add-options arm_neon } */
#include "arm_neon.h"
#include "../../aarch64/simd/vuzpf32.x"
/* { dg-final { scan-assembler-times "vuzp\.32\[ \t\]+\[dD\]\[0-9\]+, ?\[dD\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
/* { dg-final { cleanup-saved-temps } } */
gcc/testsuite/gcc.target/arm/simd/vuzpp16_1.c 0 → 100644
/* Test the `vuzpp16' ARM Neon intrinsic. */
/* { dg-do run } */
/* { dg-require-effective-target arm_neon_ok } */
/* { dg-options "-save-temps -O1 -fno-inline" } */
/* { dg-add-options arm_neon } */
#include "arm_neon.h"
#include "../../aarch64/simd/vuzpp16.x"
/* { dg-final { scan-assembler-times "vuzp\.16\[ \t\]+\[dD\]\[0-9\]+, ?\[dD\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
/* { dg-final { cleanup-saved-temps } } */
gcc/testsuite/gcc.target/arm/simd/vuzpp8_1.c 0 → 100644
/* Test the `vuzpp8' ARM Neon intrinsic. */
/* { dg-do run } */
/* { dg-require-effective-target arm_neon_ok } */
/* { dg-options "-save-temps -O1 -fno-inline" } */
/* { dg-add-options arm_neon } */
#include "arm_neon.h"
#include "../../aarch64/simd/vuzpp8.x"
/* { dg-final { scan-assembler-times "vuzp\.8\[ \t\]+\[dD\]\[0-9\]+, ?\[dD\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
/* { dg-final { cleanup-saved-temps } } */
gcc/testsuite/gcc.target/arm/simd/vuzpqf32_1.c 0 → 100644
/* Test the `vuzpQf32' ARM Neon intrinsic. */
/* { dg-do run } */
/* { dg-require-effective-target arm_neon_ok } */
/* { dg-options "-save-temps -O1 -fno-inline" } */
/* { dg-add-options arm_neon } */
#include "arm_neon.h"
#include "../../aarch64/simd/vuzpqf32.x"
/* { dg-final { scan-assembler-times "vuzp\.32\[ \t\]+\[qQ\]\[0-9\]+, ?\[qQ\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
/* { dg-final { cleanup-saved-temps } } */
gcc/testsuite/gcc.target/arm/simd/vuzpqp16_1.c 0 → 100644
/* Test the `vuzpQp16' ARM Neon intrinsic. */
/* { dg-do run } */
/* { dg-require-effective-target arm_neon_ok } */
/* { dg-options "-save-temps -O1 -fno-inline" } */
/* { dg-add-options arm_neon } */
#include "arm_neon.h"
#include "../../aarch64/simd/vuzpqp16.x"
/* { dg-final { scan-assembler-times "vuzp\.16\[ \t\]+\[qQ\]\[0-9\]+, ?\[qQ\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
/* { dg-final { cleanup-saved-temps } } */
gcc/testsuite/gcc.target/arm/simd/vuzpqp8_1.c 0 → 100644
/* Test the `vuzpQp8' ARM Neon intrinsic. */
/* { dg-do run } */
/* { dg-require-effective-target arm_neon_ok } */
/* { dg-options "-save-temps -O1 -fno-inline" } */
/* { dg-add-options arm_neon } */
#include "arm_neon.h"
#include "../../aarch64/simd/vuzpqp8.x"
/* { dg-final { scan-assembler-times "vuzp\.8\[ \t\]+\[qQ\]\[0-9\]+, ?\[qQ\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
/* { dg-final { cleanup-saved-temps } } */
gcc/testsuite/gcc.target/arm/simd/vuzpqs16_1.c 0 → 100644
/* Test the `vuzpQs16' ARM Neon intrinsic. */
/* { dg-do run } */
/* { dg-require-effective-target arm_neon_ok } */
/* { dg-options "-save-temps -O1 -fno-inline" } */
/* { dg-add-options arm_neon } */
#include "arm_neon.h"
#include "../../aarch64/simd/vuzpqs16.x"
/* { dg-final { scan-assembler-times "vuzp\.16\[ \t\]+\[qQ\]\[0-9\]+, ?\[qQ\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
/* { dg-final { cleanup-saved-temps } } */
gcc/testsuite/gcc.target/arm/simd/vuzpqs32_1.c 0 → 100644
/* Test the `vuzpQs32' ARM Neon intrinsic. */
/* { dg-do run } */
/* { dg-require-effective-target arm_neon_ok } */
/* { dg-options "-save-temps -O1 -fno-inline" } */
/* { dg-add-options arm_neon } */
#include "arm_neon.h"
#include "../../aarch64/simd/vuzpqs32.x"
/* { dg-final { scan-assembler-times "vuzp\.32\[ \t\]+\[qQ\]\[0-9\]+, ?\[qQ\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
/* { dg-final { cleanup-saved-temps } } */
gcc/testsuite/gcc.target/arm/simd/vuzpqs8_1.c 0 → 100644
/* Test the `vuzpQs8' ARM Neon intrinsic. */
/* { dg-do run } */
/* { dg-require-effective-target arm_neon_ok } */
/* { dg-options "-save-temps -O1 -fno-inline" } */
/* { dg-add-options arm_neon } */
#include "arm_neon.h"
#include "../../aarch64/simd/vuzpqs8.x"
/* { dg-final { scan-assembler-times "vuzp\.8\[ \t\]+\[qQ\]\[0-9\]+, ?\[qQ\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
/* { dg-final { cleanup-saved-temps } } */
gcc/testsuite/gcc.target/arm/simd/vuzpqu16_1.c 0 → 100644
/* Test the `vuzpQu16' ARM Neon intrinsic. */
/* { dg-do run } */
/* { dg-require-effective-target arm_neon_ok } */
/* { dg-options "-save-temps -O1 -fno-inline" } */
/* { dg-add-options arm_neon } */
#include "arm_neon.h"
#include "../../aarch64/simd/vuzpqu16.x"
/* { dg-final { scan-assembler-times "vuzp\.16\[ \t\]+\[qQ\]\[0-9\]+, ?\[qQ\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
/* { dg-final { cleanup-saved-temps } } */
gcc/testsuite/gcc.target/arm/simd/vuzpqu32_1.c 0 → 100644
/* Test the `vuzpQu32' ARM Neon intrinsic. */
/* { dg-do run } */
/* { dg-require-effective-target arm_neon_ok } */
/* { dg-options "-save-temps -O1 -fno-inline" } */
/* { dg-add-options arm_neon } */
#include "arm_neon.h"
#include "../../aarch64/simd/vuzpqu32.x"
/* { dg-final { scan-assembler-times "vuzp\.32\[ \t\]+\[qQ\]\[0-9\]+, ?\[qQ\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
/* { dg-final { cleanup-saved-temps } } */
gcc/testsuite/gcc.target/arm/simd/vuzpqu8_1.c 0 → 100644
/* Test the `vuzpQu8' ARM Neon intrinsic. */
/* { dg-do run } */
/* { dg-require-effective-target arm_neon_ok } */
/* { dg-options "-save-temps -O1 -fno-inline" } */
/* { dg-add-options arm_neon } */
#include "arm_neon.h"
#include "../../aarch64/simd/vuzpqu8.x"
/* { dg-final { scan-assembler-times "vuzp\.8\[ \t\]+\[qQ\]\[0-9\]+, ?\[qQ\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
/* { dg-final { cleanup-saved-temps } } */
gcc/testsuite/gcc.target/arm/simd/vuzps16_1.c 0 → 100644
/* Test the `vuzps16' ARM Neon intrinsic. */
/* { dg-do run } */
/* { dg-require-effective-target arm_neon_ok } */
/* { dg-options "-save-temps -O1 -fno-inline" } */
/* { dg-add-options arm_neon } */
#include "arm_neon.h"
#include "../../aarch64/simd/vuzps16.x"
/* { dg-final { scan-assembler-times "vuzp\.16\[ \t\]+\[dD\]\[0-9\]+, ?\[dD\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
/* { dg-final { cleanup-saved-temps } } */
gcc/testsuite/gcc.target/arm/simd/vuzps32_1.c 0 → 100644
/* Test the `vuzps32' ARM Neon intrinsic. */
/* { dg-do run } */
/* { dg-require-effective-target arm_neon_ok } */
/* { dg-options "-save-temps -O1 -fno-inline" } */
/* { dg-add-options arm_neon } */
#include "arm_neon.h"
#include "../../aarch64/simd/vuzps32.x"
/* { dg-final { scan-assembler-times "vuzp\.32\[ \t\]+\[dD\]\[0-9\]+, ?\[dD\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
/* { dg-final { cleanup-saved-temps } } */
gcc/testsuite/gcc.target/arm/simd/vuzps8_1.c 0 → 100644
/* Test the `vuzps8' ARM Neon intrinsic. */
/* { dg-do run } */
/* { dg-require-effective-target arm_neon_ok } */
/* { dg-options "-save-temps -O1 -fno-inline" } */
/* { dg-add-options arm_neon } */
#include "arm_neon.h"
#include "../../aarch64/simd/vuzps8.x"
/* { dg-final { scan-assembler-times "vuzp\.8\[ \t\]+\[dD\]\[0-9\]+, ?\[dD\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
/* { dg-final { cleanup-saved-temps } } */
gcc/testsuite/gcc.target/arm/simd/vuzpu16_1.c 0 → 100644
/* Test the `vuzpu16' ARM Neon intrinsic. */
/* { dg-do run } */
/* { dg-require-effective-target arm_neon_ok } */
/* { dg-options "-save-temps -O1 -fno-inline" } */
/* { dg-add-options arm_neon } */
#include "arm_neon.h"
#include "../../aarch64/simd/vuzpu16.x"
/* { dg-final { scan-assembler-times "vuzp\.16\[ \t\]+\[dD\]\[0-9\]+, ?\[dD\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
/* { dg-final { cleanup-saved-temps } } */
gcc/testsuite/gcc.target/arm/simd/vuzpu32_1.c 0 → 100644
/* Test the `vuzpu32' ARM Neon intrinsic. */
/* { dg-do run } */
/* { dg-require-effective-target arm_neon_ok } */
/* { dg-options "-save-temps -O1 -fno-inline" } */
/* { dg-add-options arm_neon } */
#include "arm_neon.h"
#include "../../aarch64/simd/vuzpu32.x"
/* { dg-final { scan-assembler-times "vuzp\.32\[ \t\]+\[dD\]\[0-9\]+, ?\[dD\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
/* { dg-final { cleanup-saved-temps } } */
gcc/testsuite/gcc.target/arm/simd/vuzpu8_1.c 0 → 100644
/* Test the `vuzpu8' ARM Neon intrinsic. */
/* { dg-do run } */
/* { dg-require-effective-target arm_neon_ok } */
/* { dg-options "-save-temps -O1 -fno-inline" } */
/* { dg-add-options arm_neon } */
#include "arm_neon.h"
#include "../../aarch64/simd/vuzpu8.x"
/* { dg-final { scan-assembler-times "vuzp\.8\[ \t\]+\[dD\]\[0-9\]+, ?\[dD\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
/* { dg-final { cleanup-saved-temps } } */
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