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riscv-gcc-1
Commit 33074e5f by Richard Henderson Committed by Richard Henderson
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sparc.c: Remove all references to TARGET_EPILOGUE. 

        * config/sparc/sparc.c: Remove all references to TARGET_EPILOGUE.
        (sparc_emitting_epilogue): New.
        (leaf_label, output_return, sparc_return_peephole_ok): Remove.
        * config/sparc/sparc-protos.h: Update.
        * config/sparc/sparc.h (MASK_EPILOGUE, TARGET_EPILOGUE): Remove.
        (TARGET_SWITCHES): Update.
        * config/sparc/sparc.md (return): Remove.
        (return_*): Use sparc_emitting_epilogue, not !TARGET_EPILOGUE.
        * config/sparc/freebsd.h, config/sparc/linux64.h, config/sparc/lite.h,
        config/sparc/liteelf.h, config/sparc/netbsd-elf.h,
        config/sparc/sol2-sld-64.h, config/sparc/sol2.h,
        config/sparc/sp64-aout.h, config/sparc/sp64-elf.h,
        config/sparc/sp86x-aout.h, config/sparc/sp86x-elf.h,
        config/sparc/splet.h, config/sparc/vxsparc64.h (TARGET_DEFAULT):
        Remove MASK_EPILOGUE.
        * doc/invoke.texi: Update.

From-SVN: r51626
parent afaef726
Showing with 50 additions and 74 deletions
gcc/ChangeLog
2002-03-30 Richard Henderson <rth@redhat.com>
* config/sparc/sparc.c: Remove all references to TARGET_EPILOGUE.
(sparc_emitting_epilogue): New.
(leaf_label, output_return, sparc_return_peephole_ok): Remove.
* config/sparc/sparc-protos.h: Update.
* config/sparc/sparc.h (MASK_EPILOGUE, TARGET_EPILOGUE): Remove.
(TARGET_SWITCHES): Update.
* config/sparc/sparc.md (return): Remove.
(return_*): Use sparc_emitting_epilogue, not !TARGET_EPILOGUE.
* config/sparc/freebsd.h, config/sparc/linux64.h, config/sparc/lite.h,
config/sparc/liteelf.h, config/sparc/netbsd-elf.h,
config/sparc/sol2-sld-64.h, config/sparc/sol2.h,
config/sparc/sp64-aout.h, config/sparc/sp64-elf.h,
config/sparc/sp86x-aout.h, config/sparc/sp86x-elf.h,
config/sparc/splet.h, config/sparc/vxsparc64.h (TARGET_DEFAULT):
Remove MASK_EPILOGUE.
* doc/invoke.texi: Update.
2002-03-30 Daniel Berlin <dan@dberlin.org>
* dwarf2out.c (dwarf2out_define): Remove start_source_file call,
......
gcc/config/sparc/freebsd.h
......@@ -92,7 +92,7 @@ the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
#undef TARGET_DEFAULT
#define TARGET_DEFAULT \
(MASK_V9 + MASK_64BIT + MASK_PTR64 /* + MASK_FASTER_STRUCTS */ \
+ MASK_STACK_BIAS + MASK_APP_REGS + MASK_EPILOGUE + MASK_FPU \
+ MASK_STACK_BIAS + MASK_APP_REGS + MASK_FPU \
+ MASK_LONG_DOUBLE_128 /* + MASK_HARD_QUAD */)
/* The default code model. */
......
gcc/config/sparc/linux64.h
......@@ -36,7 +36,7 @@ Boston, MA 02111-1307, USA. */
#undef TARGET_DEFAULT
#define TARGET_DEFAULT \
(MASK_V9 + MASK_PTR64 + MASK_64BIT /* + MASK_HARD_QUAD */ \
+ MASK_STACK_BIAS + MASK_APP_REGS + MASK_EPILOGUE + MASK_FPU + MASK_LONG_DOUBLE_128)
+ MASK_STACK_BIAS + MASK_APP_REGS + MASK_FPU + MASK_LONG_DOUBLE_128)
#endif
#undef ASM_CPU_DEFAULT_SPEC
......
gcc/config/sparc/lite.h
......@@ -28,7 +28,7 @@ Boston, MA 02111-1307, USA. */
/* Enable app-regs and epilogue options. Do not enable the fpu. */
#undef TARGET_DEFAULT
#define TARGET_DEFAULT (MASK_APP_REGS + MASK_EPILOGUE)
#define TARGET_DEFAULT MASK_APP_REGS
/* US Software GOFAST library support. */
#undef INIT_SUBTARGET_OPTABS
......
gcc/config/sparc/liteelf.h
......@@ -38,7 +38,7 @@ Boston, MA 02111-1307, USA. */
/* Enable app-regs and epilogue options. Do not enable the fpu. */
#undef TARGET_DEFAULT
#define TARGET_DEFAULT (MASK_APP_REGS + MASK_EPILOGUE)
#define TARGET_DEFAULT MASK_APP_REGS
/* US Software GOFAST library support. */
#undef INIT_SUBTARGET_OPTABS
......
gcc/config/sparc/netbsd-elf.h
......@@ -137,8 +137,7 @@ Boston, MA 02111-1307, USA. */
#undef TARGET_DEFAULT
#define TARGET_DEFAULT \
(MASK_V9 + MASK_PTR64 + MASK_64BIT /* + MASK_HARD_QUAD */ \
+ MASK_STACK_BIAS + MASK_APP_REGS + MASK_EPILOGUE + MASK_FPU \
+ MASK_LONG_DOUBLE_128)
+ MASK_STACK_BIAS + MASK_APP_REGS + MASK_FPU + MASK_LONG_DOUBLE_128)
#undef SPARC_DEFAULT_CMODEL
#define SPARC_DEFAULT_CMODEL CM_MEDANY
......
gcc/config/sparc/sol2-sld-64.h
......@@ -27,7 +27,7 @@
#undef TARGET_DEFAULT
#define TARGET_DEFAULT \
(MASK_V9 + MASK_PTR64 + MASK_64BIT /* + MASK_HARD_QUAD */ + \
MASK_STACK_BIAS + MASK_EPILOGUE + MASK_FPU + MASK_LONG_DOUBLE_128)
MASK_STACK_BIAS + MASK_FPU + MASK_LONG_DOUBLE_128)
#endif
/* The default code model. */
......
gcc/config/sparc/sol2.h
......@@ -237,7 +237,7 @@ Boston, MA 02111-1307, USA. */
/* Solaris allows 64 bit out and global registers in 32 bit mode.
sparc_override_options will disable V8+ if not generating V9 code. */
#undef TARGET_DEFAULT
#define TARGET_DEFAULT (MASK_EPILOGUE + MASK_FPU + MASK_V8PLUS + MASK_LONG_DOUBLE_128)
#define TARGET_DEFAULT (MASK_FPU + MASK_V8PLUS + MASK_LONG_DOUBLE_128)
/*
* Attempt to turn on access permissions for the stack.
......
gcc/config/sparc/sp64-aout.h
......@@ -26,7 +26,7 @@ Boston, MA 02111-1307, USA. */
#undef TARGET_DEFAULT
#define TARGET_DEFAULT \
(MASK_V9 + MASK_PTR64 + MASK_64BIT + MASK_HARD_QUAD \
+ MASK_APP_REGS + MASK_EPILOGUE + MASK_FPU + MASK_STACK_BIAS)
+ MASK_APP_REGS + MASK_FPU + MASK_STACK_BIAS)
/* The only code model supported is Medium/Low. */
#undef SPARC_DEFAULT_CMODEL
......
gcc/config/sparc/sp64-elf.h
......@@ -33,7 +33,7 @@ Boston, MA 02111-1307, USA. */
#undef TARGET_DEFAULT
#define TARGET_DEFAULT \
(MASK_V9 + MASK_PTR64 + MASK_64BIT + MASK_HARD_QUAD \
+ MASK_APP_REGS + MASK_EPILOGUE + MASK_FPU + MASK_STACK_BIAS + MASK_LONG_DOUBLE_128)
+ MASK_APP_REGS + MASK_FPU + MASK_STACK_BIAS + MASK_LONG_DOUBLE_128)
#undef SPARC_DEFAULT_CMODEL
#define SPARC_DEFAULT_CMODEL CM_EMBMEDANY
......
gcc/config/sparc/sp86x-aout.h
......@@ -28,7 +28,7 @@ Boston, MA 02111-1307, USA. */
/* Enable app-regs and epilogue options. Do not enable the fpu. */
#undef TARGET_DEFAULT
#define TARGET_DEFAULT (MASK_APP_REGS + MASK_EPILOGUE)
#define TARGET_DEFAULT MASK_APP_REGS
#undef ASM_SPEC
#define ASM_SPEC "%{v:-v} %{mlittle-endian-data:--little-endian-data} %(asm_cpu)"
......
gcc/config/sparc/sp86x-elf.h
......@@ -38,7 +38,7 @@ Boston, MA 02111-1307, USA. */
/* Enable app-regs and epilogue options. Do not enable the fpu. */
#undef TARGET_DEFAULT
#define TARGET_DEFAULT (MASK_APP_REGS + MASK_EPILOGUE)
#define TARGET_DEFAULT MASK_APP_REGS
#undef ASM_SPEC
#define ASM_SPEC "%{v:-V} %{mlittle-endian-data:--little-endian-data} %(asm_cpu)"
......
gcc/config/sparc/sparc-protos.h
......@@ -24,6 +24,8 @@ Boston, MA 02111-1307, USA. */
#ifndef __SPARC_PROTOS_H__
#define __SPARC_PROTOS_H__
extern bool sparc_emitting_epilogue;
#ifdef TREE_CODE
extern struct rtx_def *function_value PARAMS ((tree, enum machine_mode, int));
extern void function_arg_advance PARAMS ((CUMULATIVE_ARGS *,
......@@ -84,7 +86,6 @@ extern void sparc_emit_set_symbolic_const64 PARAMS ((rtx, rtx, rtx));
extern int sparc_splitdi_legitimate PARAMS ((rtx, rtx));
extern int sparc_absnegfloat_split_legitimate PARAMS ((rtx, rtx));
extern char *output_cbranch PARAMS ((rtx, rtx, int, int, int, int, rtx));
extern const char *output_return PARAMS ((rtx *));
extern const char *output_sibcall PARAMS ((rtx, rtx));
extern char *output_v9branch PARAMS ((rtx, rtx, int, int, int, int, int,
rtx));
......@@ -115,7 +116,6 @@ extern char *sparc_v8plus_shift PARAMS ((rtx *, rtx, const char *));
/* Function used for V8+ code generation. Returns 1 if the high
32 bits of REG are 0 before INSN. */
extern int sparc_check_64 PARAMS ((rtx, rtx));
extern int sparc_return_peephole_ok PARAMS ((rtx, rtx));
extern rtx gen_df_reg PARAMS ((rtx, int));
#endif /* RTX_CODE */
......
gcc/config/sparc/sparc.h
......@@ -387,11 +387,6 @@ extern int target_flags;
#define MASK_FPU 1
#define TARGET_FPU (target_flags & MASK_FPU)
/* Nonzero if we should use function_epilogue(). Otherwise, we
use fast return insns, but lose some generality. */
#define MASK_EPILOGUE 2
#define TARGET_EPILOGUE (target_flags & MASK_EPILOGUE)
/* Nonzero if we should assume that double pointers might be unaligned.
This can happen when linking gcc compiled code with other compilers,
because the ABI only guarantees 4 byte alignment. */
......@@ -535,10 +530,6 @@ extern int target_flags;
{"soft-float", -MASK_FPU, \
N_("Do not use hardware fp") }, \
{"soft-float", MASK_FPU_SET, NULL }, \
{"epilogue", MASK_EPILOGUE, \
N_("Use function_epilogue()") }, \
{"no-epilogue", -MASK_EPILOGUE, \
N_("Do not use function_epilogue()") }, \
{"unaligned-doubles", MASK_UNALIGNED_DOUBLES, \
N_("Assume possible double misalignment") }, \
{"no-unaligned-doubles", -MASK_UNALIGNED_DOUBLES, \
......@@ -607,7 +598,7 @@ extern int target_flags;
/* MASK_APP_REGS must always be the default because that's what
FIXED_REGISTERS is set to and -ffixed- is processed before
CONDITIONAL_REGISTER_USAGE is called (where we process -mno-app-regs). */
#define TARGET_DEFAULT (MASK_APP_REGS + MASK_EPILOGUE + MASK_FPU)
#define TARGET_DEFAULT (MASK_APP_REGS + MASK_FPU)
/* This is meant to be redefined in target specific files. */
#define SUBTARGET_SWITCHES
......
gcc/config/sparc/sparc.md
......@@ -8744,21 +8744,6 @@
[(set_attr "type" "multi")
(set_attr "length" "3")])
(define_insn "return"
[(return)
(use (reg:SI 31))]
"! TARGET_EPILOGUE"
"* return output_return (operands);"
[(set_attr "type" "return")])
(define_peephole
[(set (match_operand:SI 0 "register_operand" "=r")
(match_operand:SI 1 "arith_operand" "rI"))
(parallel [(return)
(use (reg:SI 31))])]
"sparc_return_peephole_ok (operands[0], operands[1])"
"return\\t%%i7+8\\n\\tmov\\t%Y1, %Y0")
(define_insn "nop"
[(const_int 0)]
""
......@@ -9155,14 +9140,14 @@
(compare:CC (match_dup 1) (const_int 0)))])]
"")
;; Return peepholes. First the "normal" ones.
;; These are necessary to catch insns ending up in the epilogue delay list.
;; Return peepholes. These are generated by sparc_nonflat_function_epilogue
;; who then immediately calls final_scan_insn.
(define_insn "*return_qi"
[(set (match_operand:QI 0 "restore_operand" "")
(match_operand:QI 1 "arith_operand" "rI"))
(return)]
"! TARGET_EPILOGUE"
"sparc_emitting_epilogue"
"*
{
if (! TARGET_ARCH64 && current_function_returns_struct)
......@@ -9180,7 +9165,7 @@
[(set (match_operand:HI 0 "restore_operand" "")
(match_operand:HI 1 "arith_operand" "rI"))
(return)]
"! TARGET_EPILOGUE"
"sparc_emitting_epilogue"
"*
{
if (! TARGET_ARCH64 && current_function_returns_struct)
......@@ -9198,7 +9183,7 @@
[(set (match_operand:SI 0 "restore_operand" "")
(match_operand:SI 1 "arith_operand" "rI"))
(return)]
"! TARGET_EPILOGUE"
"sparc_emitting_epilogue"
"*
{
if (! TARGET_ARCH64 && current_function_returns_struct)
......@@ -9212,15 +9197,11 @@
[(set_attr "type" "multi")
(set_attr "length" "2")])
;; The following pattern is only generated by delayed-branch scheduling,
;; when the insn winds up in the epilogue. This can happen not only when
;; ! TARGET_FPU because we move complex types around by parts using
;; SF mode SUBREGs.
(define_insn "*return_sf_no_fpu"
[(set (match_operand:SF 0 "restore_operand" "=r")
(match_operand:SF 1 "register_operand" "r"))
(return)]
"! TARGET_EPILOGUE"
"sparc_emitting_epilogue"
"*
{
if (! TARGET_ARCH64 && current_function_returns_struct)
......@@ -9237,7 +9218,7 @@
[(set (match_operand:DF 0 "restore_operand" "=r")
(match_operand:DF 1 "register_operand" "r"))
(return)]
"! TARGET_EPILOGUE && TARGET_ARCH64"
"sparc_emitting_epilogue && TARGET_ARCH64"
"*
{
if (IN_OR_GLOBAL_P (operands[1]))
......@@ -9253,7 +9234,7 @@
(plus:SI (match_operand:SI 1 "register_operand" "r")
(match_operand:SI 2 "arith_operand" "rI")))
(return)]
"! TARGET_EPILOGUE"
"sparc_emitting_epilogue"
"*
{
if (! TARGET_ARCH64 && current_function_returns_struct)
......@@ -9274,7 +9255,7 @@
(lo_sum:SI (match_operand:SI 1 "register_operand" "r")
(match_operand:SI 2 "immediate_operand" "in")))
(return)]
"! TARGET_EPILOGUE && ! TARGET_CM_MEDMID"
"sparc_emitting_epilogue && ! TARGET_CM_MEDMID"
"*
{
if (! TARGET_ARCH64 && current_function_returns_struct)
......@@ -9292,7 +9273,7 @@
[(set (match_operand:DI 0 "restore_operand" "")
(match_operand:DI 1 "arith_double_operand" "rHI"))
(return)]
"TARGET_ARCH64 && ! TARGET_EPILOGUE"
"sparc_emitting_epilogue && TARGET_ARCH64"
"ret\;restore %%g0, %1, %Y0"
[(set_attr "type" "multi")
(set_attr "length" "2")])
......@@ -9302,7 +9283,7 @@
(plus:DI (match_operand:DI 1 "arith_operand" "%r")
(match_operand:DI 2 "arith_double_operand" "rHI")))
(return)]
"TARGET_ARCH64 && ! TARGET_EPILOGUE"
"sparc_emitting_epilogue && TARGET_ARCH64"
"ret\;restore %r1, %2, %Y0"
[(set_attr "type" "multi")
(set_attr "length" "2")])
......@@ -9312,18 +9293,16 @@
(lo_sum:DI (match_operand:DI 1 "arith_operand" "%r")
(match_operand:DI 2 "immediate_operand" "in")))
(return)]
"TARGET_ARCH64 && ! TARGET_EPILOGUE && ! TARGET_CM_MEDMID"
"sparc_emitting_epilogue && TARGET_ARCH64 && ! TARGET_CM_MEDMID"
"ret\;restore %r1, %%lo(%a2), %Y0"
[(set_attr "type" "multi")
(set_attr "length" "2")])
;; The following pattern is only generated by delayed-branch scheduling,
;; when the insn winds up in the epilogue.
(define_insn "*return_sf"
[(set (reg:SF 32)
(match_operand:SF 0 "register_operand" "f"))
(return)]
"! TARGET_EPILOGUE"
"sparc_emitting_epilogue"
"ret\;fmovs\\t%0, %%f0"
[(set_attr "type" "multi")
(set_attr "length" "2")])
......
gcc/config/sparc/splet.h
......@@ -20,7 +20,7 @@ the Free Software Foundation, 59 Temple Place - Suite 330,
Boston, MA 02111-1307, USA. */
#undef TARGET_DEFAULT
#define TARGET_DEFAULT (MASK_APP_REGS + MASK_EPILOGUE)
#define TARGET_DEFAULT MASK_APP_REGS
#define CPP_PREDEFINES "-Dsparc -Acpu=sparc -Amachine=sparc"
......
gcc/config/sparc/vxsparc64.h
......@@ -71,7 +71,7 @@ Boston, MA 02111-1307, USA. */
#define CPP_SPEC "%(cpp_cpu) %(cpp_arch) -DCPU=ULTRASPARC -D__CPU__=CPU"
#undef TARGET_DEFAULT
#define TARGET_DEFAULT (MASK_APP_REGS | MASK_EPILOGUE | MASK_FPU \
#define TARGET_DEFAULT (MASK_APP_REGS | MASK_FPU \
| MASK_LONG_DOUBLE_128 | MASK_64BIT)
#undef SPARC_DEFAULT_CMODEL
......
gcc/doc/invoke.texi
......@@ -349,10 +349,10 @@ in the following sections.
-mcmodel=@var{code-model} @gol
-m32 -m64 @gol
-mapp-regs -mbroken-saverestore -mcypress @gol
-mepilogue -mfaster-structs -mflat @gol
-mfaster-structs -mflat @gol
-mfpu -mhard-float -mhard-quad-float @gol
-mimpure-text -mlive-g0 -mno-app-regs @gol
-mno-epilogue -mno-faster-structs -mno-flat -mno-fpu @gol
-mno-faster-structs -mno-flat -mno-fpu @gol
-mno-impure-text -mno-stack-bias -mno-unaligned-doubles @gol
-msoft-float -msoft-quad-float -msparclite -mstack-bias @gol
-msupersparc -munaligned-doubles -mv8}
......@@ -5164,18 +5164,6 @@ emulates the effect of the instruction. Because of the trap handler overhead,
this is much slower than calling the ABI library routines. Thus the
@option{-msoft-quad-float} option is the default.
@item -mno-epilogue
@itemx -mepilogue
@opindex mno-epilogue
@opindex mepilogue
With @option{-mepilogue} (the default), the compiler always emits code for
function exit at the end of each function. Any function exit in
the middle of the function (such as a return statement in C) will
generate a jump to the exit code at the end of the function.
With @option{-mno-epilogue}, the compiler tries to emit exit code inline
at every function exit.
@item -mno-flat
@itemx -mflat
@opindex mno-flat
......
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