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riscv-gcc-1
Commit 30d7b5f4 by Kazu Hirata Committed by Kazu Hirata
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* config/h8300/h8300.md (two anonymous patterns): Remove. 

From-SVN: r48334
parent df8992f8
Showing with 5 additions and 27 deletions
gcc/ChangeLog
2001-12-27 Kazu Hirata <kazu@hxi.com>
* config/h8300/h8300.md (two anonymous patterns): Remove.
2001-12-27 Richard Henderson <rth@redhat.com>
* haifa-sched.c (reemit_other_notes): New.
......
gcc/config/h8300/h8300.md
......@@ -2104,24 +2104,11 @@
;;
;; Inverted loads with a 32bit destination.
;;
;; Yes, all seven cases are needed.
;; Yes, all five cases are needed.
;;
(define_insn ""
[(set (match_operand:SI 0 "register_operand" "=&r")
(and:SI (not:SI
(zero_extend:SI (match_operand:HI 1 "register_operand" "r")))
(match_operand:SI 2 "p_operand" "P")))]
""
"* return output_simode_bld (1, 1, operands);"
[(set_attr "cc" "clobber")
(set (attr "length")
(if_then_else (eq (symbol_ref "TARGET_H8300H || TARGET_H8300S")
(const_int 0))
(const_int 10)
(const_int 8)))])
(define_insn ""
[(set (match_operand:SI 0 "register_operand" "=&r")
(and:SI (not:SI
(zero_extend:SI
(lshiftrt:HI (match_operand:HI 1 "bit_operand" "Ur")
(match_operand:HI 2 "const_int_operand" "n"))))
......@@ -2138,19 +2125,6 @@
(define_insn ""
[(set (match_operand:SI 0 "register_operand" "=&r")
(and:SI (not:SI
(zero_extend:SI (match_operand:QI 1 "register_operand" "r")))
(match_operand:SI 2 "p_operand" "P")))]
""
"* return output_simode_bld (1, 1, operands);"
[(set_attr "cc" "clobber")
(set (attr "length")
(if_then_else (eq (symbol_ref "TARGET_H8300H || TARGET_H8300S")
(const_int 0))
(const_int 10)
(const_int 8)))])
(define_insn ""
[(set (match_operand:SI 0 "register_operand" "=&r")
(and:SI (not:SI
(zero_extend:SI
(lshiftrt:QI (match_operand:QI 1 "bit_operand" "Ur")
(match_operand:QI 2 "const_int_operand" "n"))))
......
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