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riscv-gcc-1
Commit 30972225 by Andreas Krebbel Committed by Andreas Krebbel
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2097.md (z10_fhex): Remove insn reservation. 

2010-06-02  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>

	* config/s390/2097.md (z10_fhex): Remove insn reservation.
	* config/s390/s390.md (UNSPEC_COPYSIGN): Remove unused constant.
	(*mov<mode>_64 TD_TF, *mov<mode>_31 TD_TF, *mov<mode>_64dfp DD_DF,
	*mov<mode>_64 DD_DF, *mov<mode>_31, mov<mode>): Remove load zero
	instruction.
	* config/s390/s390.c: Don't accept fp zeros as valid constants
	anymore.

From-SVN: r160151
parent d4fb676f
Showing with 38 additions and 79 deletions
gcc/ChangeLog
2010-06-02 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
* config/s390/2097.md (z10_fhex): Remove insn reservation.
* config/s390/s390.md (UNSPEC_COPYSIGN): Remove unused constant.
(*mov<mode>_64 TD_TF, *mov<mode>_31 TD_TF, *mov<mode>_64dfp DD_DF,
*mov<mode>_64 DD_DF, *mov<mode>_31, mov<mode>): Remove load zero
instruction.
* config/s390/s390.c: Don't accept fp zeros as valid constants
anymore.
2010-06-02 Jan Hubicka <jh@suse.cz>
* bitmap.c (bitmap_descriptor): Add search_iter.
......
gcc/config/s390/2097.md
......@@ -466,15 +466,6 @@
(eq_attr "type" "fsimpdf,fmuldf"))
"z10_e1_BOTH, z10_Gate_FP")
; LOAD ZERO produces a hex value but we need bin. Using the stage 7
; bypass causes an exception for format conversion which is very
; expensive. So, make sure subsequent instructions only get the zero
; in the normal way.
(define_insn_reservation "z10_fhex" 12
(and (eq_attr "cpu" "z10")
(eq_attr "type" "fhex"))
"z10_e1_BOTH, z10_Gate_FP")
(define_insn_reservation "z10_fsimpsf" 6
(and (eq_attr "cpu" "z10")
(eq_attr "type" "fsimpsf,fmulsf"))
......
gcc/config/s390/s390.c
......@@ -2809,11 +2809,6 @@ legitimate_reload_constant_p (rtx op)
&& larl_operand (op, VOIDmode))
return true;
/* Accept lzXX operands. */
if (GET_CODE (op) == CONST_DOUBLE
&& CONST_DOUBLE_OK_FOR_CONSTRAINT_P (op, 'G', "G"))
return true;
/* Accept double-word operands that can be split. */
if (GET_CODE (op) == CONST_INT
&& trunc_int_for_mode (INTVAL (op), word_mode) != INTVAL (op))
......
gcc/config/s390/s390.md
......@@ -105,11 +105,8 @@
(UNSPEC_SP_SET 700)
(UNSPEC_SP_TEST 701)
; Copy sign instructions
(UNSPEC_COPYSIGN 800)
; Test Data Class (TDC)
(UNSPEC_TDC_INSN 900)
(UNSPEC_TDC_INSN 800)
])
;;
......@@ -1931,11 +1928,10 @@
"")
(define_insn "*mov<mode>_64"
[(set (match_operand:TD_TF 0 "nonimmediate_operand" "=f,f,f,o, d,QS, d,o")
(match_operand:TD_TF 1 "general_operand" " G,f,o,f,QS, d,dRT,d"))]
[(set (match_operand:TD_TF 0 "nonimmediate_operand" "=f,f,o, d,QS, d,o")
(match_operand:TD_TF 1 "general_operand" " f,o,f,QS, d,dRT,d"))]
"TARGET_ZARCH"
"@
lzxr\t%0
lxr\t%0,%1
#
#
......@@ -1943,20 +1939,19 @@
stmg\t%1,%N1,%S0
#
#"
[(set_attr "op_type" "RRE,RRE,*,*,RSY,RSY,*,*")
(set_attr "type" "fhex,fsimptf,*,*,lm,stm,*,*")])
[(set_attr "op_type" "RRE,*,*,RSY,RSY,*,*")
(set_attr "type" "fsimptf,*,*,lm,stm,*,*")])
(define_insn "*mov<mode>_31"
[(set (match_operand:TD_TF 0 "nonimmediate_operand" "=f,f,f,o")
(match_operand:TD_TF 1 "general_operand" " G,f,o,f"))]
[(set (match_operand:TD_TF 0 "nonimmediate_operand" "=f,f,o")
(match_operand:TD_TF 1 "general_operand" " f,o,f"))]
"!TARGET_ZARCH"
"@
lzxr\t%0
lxr\t%0,%1
#
#"
[(set_attr "op_type" "RRE,RRE,*,*")
(set_attr "type" "fhex,fsimptf,*,*")])
[(set_attr "op_type" "RRE,*,*")
(set_attr "type" "fsimptf,*,*")])
; TFmode in GPRs splitters
......@@ -2047,12 +2042,11 @@
(define_insn "*mov<mode>_64dfp"
[(set (match_operand:DD_DF 0 "nonimmediate_operand"
"=f,f,f,d,f,f,R,T,d, d,RT")
"=f,f,d,f,f,R,T,d, d,RT")
(match_operand:DD_DF 1 "general_operand"
" G,f,d,f,R,T,f,f,d,RT, d"))]
" f,d,f,R,T,f,f,d,RT, d"))]
"TARGET_DFP"
"@
lzdr\t%0
ldr\t%0,%1
ldgr\t%0,%1
lgdr\t%0,%1
......@@ -2063,28 +2057,17 @@
lgr\t%0,%1
lg\t%0,%1
stg\t%1,%0"
[(set_attr "op_type" "RRE,RR,RRE,RRE,RX,RXY,RX,RXY,RRE,RXY,RXY")
(set_attr "type" "fhex,floaddf,floaddf,floaddf,floaddf,floaddf,
[(set_attr "op_type" "RR,RRE,RRE,RX,RXY,RX,RXY,RRE,RXY,RXY")
(set_attr "type" "floaddf,floaddf,floaddf,floaddf,floaddf,
fstoredf,fstoredf,lr,load,store")
(set_attr "z10prop" "*,
*,
*,
*,
*,
*,
*,
*,
z10_fr_E1,
z10_fwd_A3,
z10_rec")
(set_attr "z10prop" "*,*,*,*,*,*,*,z10_fr_E1,z10_fwd_A3,z10_rec")
])
(define_insn "*mov<mode>_64"
[(set (match_operand:DD_DF 0 "nonimmediate_operand" "=f,f,f,f,R,T,d, d,RT")
(match_operand:DD_DF 1 "general_operand" "G,f,R,T,f,f,d,RT, d"))]
[(set (match_operand:DD_DF 0 "nonimmediate_operand" "=f,f,f,R,T,d, d,RT")
(match_operand:DD_DF 1 "general_operand" "f,R,T,f,f,d,RT, d"))]
"TARGET_ZARCH"
"@
lzdr\t%0
ldr\t%0,%1
ld\t%0,%1
ldy\t%0,%1
......@@ -2093,27 +2076,18 @@
lgr\t%0,%1
lg\t%0,%1
stg\t%1,%0"
[(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RRE,RXY,RXY")
(set_attr "type" "fhex,fload<mode>,fload<mode>,fload<mode>,
[(set_attr "op_type" "RR,RX,RXY,RX,RXY,RRE,RXY,RXY")
(set_attr "type" "fload<mode>,fload<mode>,fload<mode>,
fstore<mode>,fstore<mode>,lr,load,store")
(set_attr "z10prop" "*,
*,
*,
*,
*,
*,
z10_fr_E1,
z10_fwd_A3,
z10_rec")])
(set_attr "z10prop" "*,*,*,*,*,*,z10_fr_E1,z10_fwd_A3,z10_rec")])
(define_insn "*mov<mode>_31"
[(set (match_operand:DD_DF 0 "nonimmediate_operand"
"=f,f,f,f,R,T,d,d,Q,S, d,o")
"=f,f,f,R,T,d,d,Q,S, d,o")
(match_operand:DD_DF 1 "general_operand"
" G,f,R,T,f,f,Q,S,d,d,dPRT,d"))]
" f,R,T,f,f,Q,S,d,d,dPRT,d"))]
"!TARGET_ZARCH"
"@
lzdr\t%0
ldr\t%0,%1
ld\t%0,%1
ldy\t%0,%1
......@@ -2125,8 +2099,8 @@
stmy\t%1,%N1,%S0
#
#"
[(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RS,RSY,RS,RSY,*,*")
(set_attr "type" "fhex,fload<mode>,fload<mode>,fload<mode>,
[(set_attr "op_type" "RR,RX,RXY,RX,RXY,RS,RSY,RS,RSY,*,*")
(set_attr "type" "fload<mode>,fload<mode>,fload<mode>,
fstore<mode>,fstore<mode>,lm,lm,stm,stm,*,*")])
(define_split
......@@ -2176,12 +2150,11 @@
(define_insn "mov<mode>"
[(set (match_operand:SD_SF 0 "nonimmediate_operand"
"=f,f,f,f,R,T,d,d,d,R,T")
"=f,f,f,R,T,d,d,d,R,T")
(match_operand:SD_SF 1 "general_operand"
" G,f,R,T,f,f,d,R,T,d,d"))]
" f,R,T,f,f,d,R,T,d,d"))]
""
"@
lzer\t%0
ler\t%0,%1
le\t%0,%1
ley\t%0,%1
......@@ -2192,20 +2165,10 @@
ly\t%0,%1
st\t%1,%0
sty\t%1,%0"
[(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RR,RX,RXY,RX,RXY")
(set_attr "type" "fhex,fload<mode>,fload<mode>,fload<mode>,
[(set_attr "op_type" "RR,RX,RXY,RX,RXY,RR,RX,RXY,RX,RXY")
(set_attr "type" "fload<mode>,fload<mode>,fload<mode>,
fstore<mode>,fstore<mode>,lr,load,load,store,store")
(set_attr "z10prop" "*,
*,
*,
*,
*,
*,
z10_fr_E1,
z10_fwd_A3,
z10_fwd_A3,
z10_rec,
z10_rec")])
(set_attr "z10prop" "*,*,*,*,*,*,z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_rec,z10_rec")])
;
; movcc instruction pattern
......
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