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riscv-gcc-1
Commit 309323c2 by David Edelsohn Committed by David Edelsohn
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{aix43.h,aix5.1} (ASM_CPU_SPEC): Add power3 synonym for 630. 

        * config/rs6000/{aix43.h,aix5.1} (ASM_CPU_SPEC): Add power3
        synonym for 630.  Add power4.  Remove embedded processors.  Use -m604
        assembler option.
        (CPP_CPU_SPEC): Add power3 and power4.
        (PROCESSOR_DEFAULT): Change to 604e.
        * config/rs6000/rs6000.h (ASM_CPU_SPEC): Similar additions.
        (CPP_CPU_SPEC): Similar additions.
        (enum process_type): Add POWER4.
        (RTX_COSTS): Add POWER4.
        (CPP_CPU_SPEC): Similar additions.
        * config/rs6000/linux64.h (PROCESSOR_DEFAULT): Define.
        * config/rs6000/rs6000.c (rs6000_override_options): Add power4.
        (rs6000_adjust_cost): Add 603, 604, 604e, 620, 630, Power4 to
        branch adjustment.
        (rs6000_issue_rate): Add Power4.
        * config/rs6000/rs6000.md (cpu attr): Add power4.
        (iu compare): Remove 604, 604e, 620, 630.
        Add basic Power4 scheduling information.
        (mfcr/mtcrf): Change type attribute to cr_logical.

From-SVN: r54405
parent 739dd3dd
Showing with 206 additions and 62 deletions
gcc/ChangeLog
2002-06-09 David Edelsohn <edelsohn@gnu.org>
* config/rs6000/{aix43.h,aix5.1} (ASM_CPU_SPEC): Add power3
synonym for 630. Add power4. Remove embedded processors. Use -m604
assembler option.
(CPP_CPU_SPEC): Add power3 and power4.
(PROCESSOR_DEFAULT): Change to 604e.
* config/rs6000/rs6000.h (ASM_CPU_SPEC): Similar additions.
(CPP_CPU_SPEC): Similar additions.
(enum process_type): Add POWER4.
(RTX_COSTS): Add POWER4.
(CPP_CPU_SPEC): Similar additions.
* config/rs6000/linux64.h (PROCESSOR_DEFAULT): Define.
* config/rs6000/rs6000.c (rs6000_override_options): Add power4.
(rs6000_adjust_cost): Add 603, 604, 604e, 620, 630, Power4 to
branch adjustment.
(rs6000_issue_rate): Add Power4.
* config/rs6000/rs6000.md (cpu attr): Add power4.
(iu compare): Remove 604, 604e, 620, 630.
Add basic Power4 scheduling information.
(mfcr/mtcrf): Change type attribute to cr_logical.
2002-06-08 Kaveh R. Ghazi <ghazi@caip.rutgers.edu>
* gengtype.h (error_at_line): Use PARAMS, not VPARAMS. Add
......
gcc/config/rs6000/aix43.h
......@@ -75,6 +75,8 @@ do { \
%{mcpu=common: -mcom} \
%{mcpu=power: -mpwr} \
%{mcpu=power2: -mpwr2} \
%{mcpu=power3: -m604} \
%{mcpu=power4: -m604} \
%{mcpu=powerpc: -mppc} \
%{mcpu=rios: -mpwr} \
%{mcpu=rios1: -mpwr} \
......@@ -82,8 +84,6 @@ do { \
%{mcpu=rsc: -mpwr} \
%{mcpu=rsc1: -mpwr} \
%{mcpu=rs64a: -mppc} \
%{mcpu=403: -mppc} \
%{mcpu=505: -mppc} \
%{mcpu=601: -m601} \
%{mcpu=602: -mppc} \
%{mcpu=603: -m603} \
......@@ -91,9 +91,7 @@ do { \
%{mcpu=604: -m604} \
%{mcpu=604e: -m604} \
%{mcpu=620: -mppc} \
%{mcpu=630: -mppc} \
%{mcpu=821: -mppc} \
%{mcpu=860: -mppc}"
%{mcpu=630: -m604}"
#undef ASM_DEFAULT_SPEC
#define ASM_DEFAULT_SPEC "-mcom"
......@@ -135,6 +133,8 @@ do { \
%{mcpu=common: -D_ARCH_COM} \
%{mcpu=power: -D_ARCH_PWR} \
%{mcpu=power2: -D_ARCH_PWR2} \
%{mcpu=power3: -D_ARCH_PPC} \
%{mcpu=power4: -D_ARCH_PPC} \
%{mcpu=powerpc: -D_ARCH_PPC} \
%{mcpu=rios: -D_ARCH_PWR} \
%{mcpu=rios1: -D_ARCH_PWR} \
......@@ -142,17 +142,13 @@ do { \
%{mcpu=rsc: -D_ARCH_PWR} \
%{mcpu=rsc1: -D_ARCH_PWR} \
%{mcpu=rs64a: -D_ARCH_PPC} \
%{mcpu=403: -D_ARCH_PPC} \
%{mcpu=505: -D_ARCH_PPC} \
%{mcpu=601: -D_ARCH_PPC -D_ARCH_PWR} \
%{mcpu=602: -D_ARCH_PPC} \
%{mcpu=603: -D_ARCH_PPC} \
%{mcpu=603e: -D_ARCH_PPC} \
%{mcpu=604: -D_ARCH_PPC} \
%{mcpu=620: -D_ARCH_PPC} \
%{mcpu=630: -D_ARCH_PPC} \
%{mcpu=821: -D_ARCH_PPC} \
%{mcpu=860: -D_ARCH_PPC}"
%{mcpu=630: -D_ARCH_PPC}"
#undef CPP_DEFAULT_SPEC
#define CPP_DEFAULT_SPEC "-D_ARCH_COM"
......@@ -161,7 +157,7 @@ do { \
#define TARGET_DEFAULT MASK_NEW_MNEMONICS
#undef PROCESSOR_DEFAULT
#define PROCESSOR_DEFAULT PROCESSOR_PPC604
#define PROCESSOR_DEFAULT PROCESSOR_PPC604e
/* Define this macro as a C expression for the initializer of an
array of string to tell the driver program which options are
......
gcc/config/rs6000/aix51.h
......@@ -75,6 +75,8 @@ do { \
%{mcpu=common: -mcom} \
%{mcpu=power: -mpwr} \
%{mcpu=power2: -mpwr2} \
%{mcpu=power3: -m604} \
%{mcpu=power4: -m604} \
%{mcpu=powerpc: -mppc} \
%{mcpu=rios: -mpwr} \
%{mcpu=rios1: -mpwr} \
......@@ -82,8 +84,6 @@ do { \
%{mcpu=rsc: -mpwr} \
%{mcpu=rsc1: -mpwr} \
%{mcpu=rs64a: -mppc} \
%{mcpu=403: -mppc} \
%{mcpu=505: -mppc} \
%{mcpu=601: -m601} \
%{mcpu=602: -mppc} \
%{mcpu=603: -m603} \
......@@ -91,9 +91,7 @@ do { \
%{mcpu=604: -m604} \
%{mcpu=604e: -m604} \
%{mcpu=620: -mppc} \
%{mcpu=630: -mppc} \
%{mcpu=821: -mppc} \
%{mcpu=860: -mppc}"
%{mcpu=630: -m604}"
#undef ASM_DEFAULT_SPEC
#define ASM_DEFAULT_SPEC "-mcom"
......@@ -135,6 +133,8 @@ do { \
%{mcpu=common: -D_ARCH_COM} \
%{mcpu=power: -D_ARCH_PWR} \
%{mcpu=power2: -D_ARCH_PWR2} \
%{mcpu=power3: -D_ARCH_PPC} \
%{mcpu=power4: -D_ARCH_PPC} \
%{mcpu=powerpc: -D_ARCH_PPC} \
%{mcpu=rios: -D_ARCH_PWR} \
%{mcpu=rios1: -D_ARCH_PWR} \
......@@ -142,17 +142,13 @@ do { \
%{mcpu=rsc: -D_ARCH_PWR} \
%{mcpu=rsc1: -D_ARCH_PWR} \
%{mcpu=rs64a: -D_ARCH_PPC} \
%{mcpu=403: -D_ARCH_PPC} \
%{mcpu=505: -D_ARCH_PPC} \
%{mcpu=601: -D_ARCH_PPC -D_ARCH_PWR} \
%{mcpu=602: -D_ARCH_PPC} \
%{mcpu=603: -D_ARCH_PPC} \
%{mcpu=603e: -D_ARCH_PPC} \
%{mcpu=604: -D_ARCH_PPC} \
%{mcpu=620: -D_ARCH_PPC} \
%{mcpu=630: -D_ARCH_PPC} \
%{mcpu=821: -D_ARCH_PPC} \
%{mcpu=860: -D_ARCH_PPC}"
%{mcpu=630: -D_ARCH_PPC}"
#undef CPP_DEFAULT_SPEC
#define CPP_DEFAULT_SPEC "-D_ARCH_COM"
......@@ -161,7 +157,7 @@ do { \
#define TARGET_DEFAULT MASK_NEW_MNEMONICS
#undef PROCESSOR_DEFAULT
#define PROCESSOR_DEFAULT PROCESSOR_PPC604
#define PROCESSOR_DEFAULT PROCESSOR_PPC604e
/* Define this macro as a C expression for the initializer of an
array of string to tell the driver program which options are
......
gcc/config/rs6000/linux64.h
......@@ -31,6 +31,9 @@ Boston, MA 02111-1307, USA. */
#define TARGET_DEFAULT \
(MASK_POWERPC | MASK_POWERPC64 | MASK_64BIT | MASK_NEW_MNEMONICS)
#undef PROCESSOR_DEFAULT
#define PROCESSOR_DEFAULT PROCESSOR_PPC630
#undef CPP_DEFAULT_SPEC
#define CPP_DEFAULT_SPEC "-D_ARCH_PPC64"
......
gcc/config/rs6000/rs6000.c
......@@ -353,6 +353,9 @@ rs6000_override_options (default_cpu)
{"power3", PROCESSOR_PPC630,
MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS,
POWER_MASKS | MASK_PPC_GPOPT},
{"power4", PROCESSOR_POWER4,
MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS,
POWER_MASKS | MASK_PPC_GPOPT},
{"powerpc", PROCESSOR_POWERPC,
MASK_POWERPC | MASK_NEW_MNEMONICS,
POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64},
......@@ -10696,18 +10699,24 @@ rs6000_adjust_cost (insn, link, dep_insn, cost)
switch (get_attr_type (insn))
{
case TYPE_JMPREG:
/* Tell the first scheduling pass about the latency between
/* Tell the first scheduling pass about the latency between
a mtctr and bctr (and mtlr and br/blr). The first
scheduling pass will not know about this latency since
the mtctr instruction, which has the latency associated
to it, will be generated by reload. */
return TARGET_POWER ? 5 : 4;
return TARGET_POWER ? 5 : 4;
case TYPE_BRANCH:
/* Leave some extra cycles between a compare and its
dependent branch, to inhibit expensive mispredicts. */
if ((rs6000_cpu_attr == CPU_PPC750
|| rs6000_cpu_attr == CPU_PPC7400
|| rs6000_cpu_attr == CPU_PPC7450)
if ((rs6000_cpu_attr == CPU_PPC603
|| rs6000_cpu_attr == CPU_PPC604
|| rs6000_cpu_attr == CPU_PPC604E
|| rs6000_cpu_attr == CPU_PPC620
|| rs6000_cpu_attr == CPU_PPC630
|| rs6000_cpu_attr == CPU_PPC750
|| rs6000_cpu_attr == CPU_PPC7400
|| rs6000_cpu_attr == CPU_PPC7450
|| rs6000_cpu_attr == CPU_POWER4)
&& recog_memoized (dep_insn)
&& (INSN_CODE (dep_insn) >= 0)
&& (get_attr_type (dep_insn) == TYPE_COMPARE
......@@ -10788,6 +10797,7 @@ rs6000_issue_rate ()
case CPU_PPC604E:
case CPU_PPC620:
case CPU_PPC630:
case CPU_POWER4:
return 4;
default:
return 1;
......
gcc/config/rs6000/rs6000.h
......@@ -58,6 +58,8 @@ Boston, MA 02111-1307, USA. */
%{mcpu=common: -D_ARCH_COM} \
%{mcpu=power: -D_ARCH_PWR} \
%{mcpu=power2: -D_ARCH_PWR2} \
%{mcpu=power3: -D_ARCH_PPC} \
%{mcpu=power4: -D_ARCH_PPC} \
%{mcpu=powerpc: -D_ARCH_PPC} \
%{mcpu=rios: -D_ARCH_PWR} \
%{mcpu=rios1: -D_ARCH_PWR} \
......@@ -98,6 +100,8 @@ Boston, MA 02111-1307, USA. */
%{mcpu=common: -mcom} \
%{mcpu=power: -mpwr} \
%{mcpu=power2: -mpwrx} \
%{mcpu=power3: -m604} \
%{mcpu=power4: -m604} \
%{mcpu=powerpc: -mppc} \
%{mcpu=rios: -mpwr} \
%{mcpu=rios1: -mpwr} \
......@@ -116,6 +120,7 @@ Boston, MA 02111-1307, USA. */
%{mcpu=604: -mppc} \
%{mcpu=604e: -mppc} \
%{mcpu=620: -mppc} \
%{mcpu=630: -m604} \
%{mcpu=740: -mppc} \
%{mcpu=7400: -mppc} \
%{mcpu=7450: -mppc} \
......@@ -395,7 +400,8 @@ enum processor_type
PROCESSOR_PPC630,
PROCESSOR_PPC750,
PROCESSOR_PPC7400,
PROCESSOR_PPC7450
PROCESSOR_PPC7450,
PROCESSOR_POWER4
};
extern enum processor_type rs6000_cpu;
......@@ -2298,6 +2304,7 @@ do { \
return COSTS_N_INSNS (4); \
case PROCESSOR_PPC620: \
case PROCESSOR_PPC630: \
case PROCESSOR_POWER4: \
return (GET_CODE (XEXP (X, 1)) != CONST_INT \
? GET_MODE (XEXP (X, 1)) != DImode \
? COSTS_N_INSNS (5) : COSTS_N_INSNS (7) \
......@@ -2337,6 +2344,7 @@ do { \
return COSTS_N_INSNS (20); \
case PROCESSOR_PPC620: \
case PROCESSOR_PPC630: \
case PROCESSOR_POWER4: \
return (GET_MODE (XEXP (X, 1)) != DImode \
? COSTS_N_INSNS (21) \
: COSTS_N_INSNS (37)); \
......
gcc/config/rs6000/rs6000.md
......@@ -56,7 +56,7 @@
;; Processor type -- this attribute must exactly match the processor_type
;; enumeration in rs6000.h.
(define_attr "cpu" "rios1,rios2,rs64a,mpccore,ppc403,ppc405,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750,ppc7400,ppc7450"
(define_attr "cpu" "rios1,rios2,rs64a,mpccore,ppc403,ppc405,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750,ppc7400,ppc7450,power4"
(const (symbol_ref "rs6000_cpu_attr")))
; (define_function_unit NAME MULTIPLICITY SIMULTANEITY
......@@ -375,42 +375,52 @@
(and (eq_attr "type" "cr_logical")
(eq_attr "cpu" "ppc7450"))
1 1)
(define_function_unit "vec_alu2" 2 0
(and (eq_attr "type" "vecsimple")
(eq_attr "cpu" "ppc7450"))
1 2 [(eq_attr "type" "vecsimple")])
(define_function_unit "vec_alu2" 2 0
(and (eq_attr "type" "vecsimple")
(eq_attr "cpu" "ppc7450"))
1 1 [(eq_attr "type" "!vecsimple")])
(define_function_unit "vec_alu2" 2 0
(and (eq_attr "type" "veccomplex")
(eq_attr "cpu" "ppc7450"))
4 2 [(eq_attr "type" "veccomplex")])
(define_function_unit "vec_alu2" 2 0
(and (eq_attr "type" "veccomplex")
(eq_attr "cpu" "ppc7450"))
4 1 [(eq_attr "type" "!veccomplex")])
(define_function_unit "vec_alu2" 2 0
(and (eq_attr "type" "veccmp")
(eq_attr "cpu" "ppc7450"))
2 2 [(eq_attr "type" "veccmp")])
(define_function_unit "vec_alu2" 2 0
(and (eq_attr "type" "veccmp")
(eq_attr "cpu" "ppc7450"))
2 1 [(eq_attr "type" "!veccmp")])
(define_function_unit "vec_alu2" 2 0
(and (eq_attr "type" "vecfloat")
(eq_attr "cpu" "ppc7450"))
4 2 [(eq_attr "type" "vecfloat")])
(define_function_unit "vec_alu2" 2 0
(and (eq_attr "type" "vecfloat")
(eq_attr "cpu" "ppc7450"))
4 1 [(eq_attr "type" "!vecfloat")])
(define_function_unit "vec_alu2" 2 0
(and (eq_attr "type" "vecperm")
(eq_attr "cpu" "ppc7450"))
2 2 [(eq_attr "type" "vecperm")])
(define_function_unit "vec_alu2" 2 0
(and (eq_attr "type" "vecperm")
(eq_attr "cpu" "ppc7450"))
......@@ -489,7 +499,7 @@
(define_function_unit "iu" 1 0
(and (eq_attr "type" "compare,delayed_compare")
(eq_attr "cpu" "rs64a,mpccore,ppc403,ppc405,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630"))
(eq_attr "cpu" "rs64a,mpccore,ppc403,ppc405,ppc601,ppc603"))
3 1)
; some extra cycles added by TARGET_SCHED_ADJUST_COST between compare
......@@ -699,22 +709,12 @@
; RIOS2 has two symmetric FPUs.
(define_function_unit "fpu2" 2 0
(and (eq_attr "type" "fp")
(eq_attr "cpu" "rios2"))
2 1)
(define_function_unit "fpu2" 2 0
(and (eq_attr "type" "fp")
(eq_attr "cpu" "ppc630"))
3 1)
(define_function_unit "fpu2" 2 0
(and (eq_attr "type" "dmul")
(and (eq_attr "type" "fp,dmul")
(eq_attr "cpu" "rios2"))
2 1)
(define_function_unit "fpu2" 2 0
(and (eq_attr "type" "dmul")
(and (eq_attr "type" "fp,dmul")
(eq_attr "cpu" "ppc630"))
3 1)
......@@ -748,6 +748,107 @@
(eq_attr "cpu" "ppc630"))
26 26)
;; Power4
(define_function_unit "lsu2" 2 0
(and (eq_attr "type" "load")
(eq_attr "cpu" "power4"))
3 1)
(define_function_unit "lsu2" 2 0
(and (eq_attr "type" "fpload")
(eq_attr "cpu" "power4"))
5 1)
(define_function_unit "lsu2" 2 0
(and (eq_attr "type" "store,fpstore")
(eq_attr "cpu" "power4"))
1 1)
(define_function_unit "iu2" 2 0
(and (eq_attr "type" "integer")
(eq_attr "cpu" "power4"))
2 1)
(define_function_unit "iu2" 2 0
(and (eq_attr "type" "imul,lmul")
(eq_attr "cpu" "power4"))
7 6)
(define_function_unit "iu2" 2 0
(and (eq_attr "type" "imul2")
(eq_attr "cpu" "power4"))
5 4)
(define_function_unit "iu2" 2 0
(and (eq_attr "type" "imul3")
(eq_attr "cpu" "power4"))
4 3)
(define_function_unit "iu2" 2 0
(and (eq_attr "type" "idiv")
(eq_attr "cpu" "power4"))
36 35)
(define_function_unit "iu2" 2 0
(and (eq_attr "type" "ldiv")
(eq_attr "cpu" "power4"))
68 67)
(define_function_unit "imuldiv" 1 0
(and (eq_attr "type" "idiv")
(eq_attr "cpu" "power4"))
36 35)
(define_function_unit "imuldiv" 1 0
(and (eq_attr "type" "ldiv")
(eq_attr "cpu" "power4"))
68 67)
(define_function_unit "iu2" 2 0
(and (eq_attr "type" "compare,delayed_compare")
(eq_attr "cpu" "power4"))
2 1)
(define_function_unit "iu2" 2 0
(and (eq_attr "type" "mtjmpr")
(eq_attr "cpu" "power4"))
3 1)
(define_function_unit "bpu" 1 0
(and (eq_attr "type" "mtjmpr")
(eq_attr "cpu" "power4"))
3 1)
(define_function_unit "bpu" 1 0
(and (eq_attr "type" "jmpreg,branch")
(eq_attr "cpu" "power4"))
2 1)
(define_function_unit "cru" 1 0
(and (eq_attr "type" "cr_logical")
(eq_attr "cpu" "power4"))
4 1)
(define_function_unit "fpu2" 2 0
(and (eq_attr "type" "fp,dmul")
(eq_attr "cpu" "power4"))
6 1)
(define_function_unit "fpu2" 2 0
(and (eq_attr "type" "fpcompare")
(eq_attr "cpu" "power4"))
8 2)
(define_function_unit "fpu2" 2 0
(and (eq_attr "type" "sdiv,ddiv")
(eq_attr "cpu" "power4"))
33 28)
(define_function_unit "fpu2" 2 0
(and (eq_attr "type" "ssqrt,dsqrt")
(eq_attr "cpu" "power4"))
40 35)
;; Start with fixed-point load and store insns. Here we put only the more
;; complex forms. Basic data transfer is done later.
......@@ -7778,7 +7879,7 @@
mr %0,%1
{l%U1%X1|lwz%U1%X1} %0,%1
{st%U0%U1|stw%U0%U1} %1,%0"
[(set_attr "type" "*,*,*,compare,*,*,load,store")
[(set_attr "type" "cr_logical,cr_logical,cr_logical,cr_logical,cr_logical,*,load,store")
(set_attr "length" "*,*,12,*,8,*,*,*")])
;; For floating-point, we normally deal with the floating-point registers
......@@ -10585,7 +10686,8 @@
(const_int 0)]))]
""
"%D1mfcr %0\;{rlinm|rlwinm} %0,%0,%J1,1"
[(set_attr "length" "12")])
[(set_attr "type" "cr_logical")
(set_attr "length" "12")])
(define_insn ""
[(set (match_operand:DI 0 "gpc_reg_operand" "=r")
......@@ -10594,7 +10696,8 @@
(const_int 0)]))]
"TARGET_POWERPC64"
"%D1mfcr %0\;{rlinm|rlwinm} %0,%0,%J1,1"
[(set_attr "length" "12")])
[(set_attr "type" "cr_logical")
(set_attr "length" "12")])
(define_insn ""
[(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
......@@ -10650,7 +10753,8 @@
return \"%D1mfcr %0\;{rlinm|rlwinm} %0,%0,%4,%5,%5\";
}"
[(set_attr "length" "12")])
[(set_attr "type" "cr_logical")
(set_attr "length" "12")])
(define_insn ""
[(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
......@@ -10719,9 +10823,10 @@
(match_operator:SI 4 "scc_comparison_operator"
[(match_operand 5 "cc_reg_operand" "y")
(const_int 0)]))]
"REGNO (operands[2]) != REGNO (operands[5])"
"%D1%D4mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1"
[(set_attr "length" "20")])
"REGNO (operands[2]) != REGNO (operands[5])"
"%D1%D4mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1"
[(set_attr "type" "cr_logical")
(set_attr "length" "20")])
(define_peephole
[(set (match_operand:DI 0 "gpc_reg_operand" "=r")
......@@ -10732,9 +10837,10 @@
(match_operator:DI 4 "scc_comparison_operator"
[(match_operand 5 "cc_reg_operand" "y")
(const_int 0)]))]
"TARGET_POWERPC64 && REGNO (operands[2]) != REGNO (operands[5])"
"%D1%D4mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1"
[(set_attr "length" "20")])
"TARGET_POWERPC64 && REGNO (operands[2]) != REGNO (operands[5])"
"%D1%D4mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1"
[(set_attr "type" "cr_logical")
(set_attr "length" "20")])
;; There are some scc insns that can be done directly, without a compare.
;; These are faster because they don't involve the communications between
......@@ -13727,7 +13833,8 @@
(unspec:SI [(reg:CC 68) (reg:CC 69) (reg:CC 70) (reg:CC 71)
(reg:CC 72) (reg:CC 73) (reg:CC 74) (reg:CC 75)] 19))]
""
"mfcr %0")
"mfcr %0"
[(set_attr "type" "cr_logical")])
(define_insn "*stmw"
[(match_parallel 0 "stmw_operation"
......@@ -13799,17 +13906,19 @@
mask |= INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1));
operands[4] = GEN_INT (mask);
return \"mtcrf %4,%2\";
}")
}"
[(set_attr "type" "cr_logical")])
(define_insn ""
[(set (match_operand:CC 0 "cc_reg_operand" "=y")
(unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
(match_operand 2 "immediate_operand" "n")] 20))]
"GET_CODE (operands[0]) == REG
&& CR_REGNO_P (REGNO (operands[0]))
&& GET_CODE (operands[2]) == CONST_INT
&& INTVAL (operands[2]) == 1 << (75 - REGNO (operands[0]))"
"mtcrf %R0,%1")
[(set (match_operand:CC 0 "cc_reg_operand" "=y")
(unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
(match_operand 2 "immediate_operand" "n")] 20))]
"GET_CODE (operands[0]) == REG
&& CR_REGNO_P (REGNO (operands[0]))
&& GET_CODE (operands[2]) == CONST_INT
&& INTVAL (operands[2]) == 1 << (75 - REGNO (operands[0]))"
"mtcrf %R0,%1"
[(set_attr "type" "cr_logical")])
; The load-multiple instructions have similar properties.
; Note that "load_multiple" is a name known to the machine-independent
......
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