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riscv-gcc-1
Commit 3049ccbb by Segher Boessenkool Committed by Segher Boessenkool
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rs6000: Fix formatting of *mov{si,di}_internal.* 


	* config/rs6000/rs6000.md (*movsi_internal1): Fix formatting.  Improve
	formatting.
	(*movdi_internal64): Ditto.

From-SVN: r278822
parent 2538ff0d
Showing with 102 additions and 96 deletions
gcc/ChangeLog
2019-11-28 Segher Boessenkool <segher@kernel.crashing.org> 2019-11-28 Segher Boessenkool <segher@kernel.crashing.org>
* config/rs6000/rs6000.md (*movsi_internal1): Fix formatting. Improve
formatting.
(*movdi_internal64): Ditto.
2019-11-28 Segher Boessenkool <segher@kernel.crashing.org>
PR target/92602 PR target/92602
* config/rs6000/rs6000.md (bswap<mode>2_load for HSI): Change the * config/rs6000/rs6000.md (bswap<mode>2_load for HSI): Change the
indexed_or_indirect_operand to be memory_operand. indexed_or_indirect_operand to be memory_operand.
gcc/config/rs6000/rs6000.md
...@@ -6889,34 +6889,34 @@ ...@@ -6889,34 +6889,34 @@
UNSPEC_MOVSI_GOT))] UNSPEC_MOVSI_GOT))]
"") "")
;; MR LA ;; MR LA
;; LWZ LFIWZX LXSIWZX ;; LWZ LFIWZX LXSIWZX
;; STW STFIWX STXSIWX ;; STW STFIWX STXSIWX
;; LI LIS # ;; LI LIS #
;; XXLOR XXSPLTIB 0 XXSPLTIB -1 VSPLTISW ;; XXLOR XXSPLTIB 0 XXSPLTIB -1 VSPLTISW
;; XXLXOR 0 XXLORC -1 P9 const ;; XXLXOR 0 XXLORC -1 P9 const
;; MTVSRWZ MFVSRWZ ;; MTVSRWZ MFVSRWZ
;; MF%1 MT%0 NOP ;; MF%1 MT%0 NOP
(define_insn "*movsi_internal1" (define_insn "*movsi_internal1"
[(set (match_operand:SI 0 "nonimmediate_operand" [(set (match_operand:SI 0 "nonimmediate_operand"
"=r, r, "=r, r,
r, d, v, r, d, v,
m, Z, Z, m, Z, Z,
r, r, r, r, r, r,
wa, wa, wa, v, wa, wa, wa, v,
wa, v, v, wa, v, v,
wa, r, wa, r,
r, *h, *h") r, *h, *h")
(match_operand:SI 1 "input_operand" (match_operand:SI 1 "input_operand"
"r, U, "r, U,
m, Z, Z, m, Z, Z,
r, d, v, r, d, v,
I, L, n, I, L, n,
wa, O, wM, wB, wa, O, wM, wB,
O, wM, wS, O, wM, wS,
r, wa, r, wa,
*h, r, 0"))] *h, r, 0"))]
"gpc_reg_operand (operands[0], SImode) "gpc_reg_operand (operands[0], SImode)
|| gpc_reg_operand (operands[1], SImode)" || gpc_reg_operand (operands[1], SImode)"
"@ "@
...@@ -6944,32 +6944,32 @@ ...@@ -6944,32 +6944,32 @@
mt%0 %1 mt%0 %1
nop" nop"
[(set_attr "type" [(set_attr "type"
"*, *, "*, *,
load, fpload, fpload, load, fpload, fpload,
store, fpstore, fpstore, store, fpstore, fpstore,
*, *, *, *, *, *,
veclogical, vecsimple, vecsimple, vecsimple, veclogical, vecsimple, vecsimple, vecsimple,
veclogical, veclogical, vecsimple, veclogical, veclogical, vecsimple,
mffgpr, mftgpr, mffgpr, mftgpr,
*, *, *") *, *, *")
(set_attr "length" (set_attr "length"
"*, *, "*, *,
*, *, *, *, *, *,
*, *, *, *, *, *,
*, *, 8, *, *, 8,
*, *, *, *, *, *, *, *,
*, *, 8, *, *, 8,
*, *, *, *,
*, *, *") *, *, *")
(set_attr "isa" (set_attr "isa"
"*, *, "*, *,
*, p8v, p8v, *, p8v, p8v,
*, p8v, p8v, *, p8v, p8v,
*, *, *, *, *, *,
p8v, p9v, p9v, p8v, p8v, p9v, p9v, p8v,
p9v, p8v, p9v, p9v, p8v, p9v,
p8v, p8v, p8v, p8v,
*, *, *")]) *, *, *")])
;; Like movsi, but adjust a SF value to be used in a SI context, i.e. ;; Like movsi, but adjust a SF value to be used in a SI context, i.e.
;; (set (reg:SI ...) (subreg:SI (reg:SF ...) 0)) ;; (set (reg:SI ...) (subreg:SI (reg:SF ...) 0))
...@@ -8827,33 +8827,33 @@ ...@@ -8827,33 +8827,33 @@
DONE; DONE;
}) })
;; GPR store GPR load GPR move ;; GPR store GPR load GPR move
;; GPR li GPR lis GPR # ;; GPR li GPR lis GPR #
;; FPR store FPR load FPR move ;; FPR store FPR load FPR move
;; AVX store AVX store AVX load AVX load VSX move ;; AVX store AVX store AVX load AVX load VSX move
;; P9 0 P9 -1 AVX 0/-1 VSX 0 VSX -1 ;; P9 0 P9 -1 AVX 0/-1 VSX 0 VSX -1
;; P9 const AVX const ;; P9 const AVX const
;; From SPR To SPR SPR<->SPR ;; From SPR To SPR SPR<->SPR
;; VSX->GPR GPR->VSX ;; VSX->GPR GPR->VSX
(define_insn "*movdi_internal64" (define_insn "*movdi_internal64"
[(set (match_operand:DI 0 "nonimmediate_operand" [(set (match_operand:DI 0 "nonimmediate_operand"
"=YZ, r, r, "=YZ, r, r,
r, r, r, r, r, r,
m, ^d, ^d, m, ^d, ^d,
wY, Z, $v, $v, ^wa, wY, Z, $v, $v, ^wa,
wa, wa, v, wa, wa, wa, wa, v, wa, wa,
v, v, v, v,
r, *h, *h, r, *h, *h,
?r, ?wa") ?r, ?wa")
(match_operand:DI 1 "input_operand" (match_operand:DI 1 "input_operand"
"r, YZ, r, "r, YZ, r,
I, L, nF, I, L, nF,
^d, m, ^d, ^d, m, ^d,
^v, $v, wY, Z, ^wa, ^v, $v, wY, Z, ^wa,
Oj, wM, OjwM, Oj, wM, Oj, wM, OjwM, Oj, wM,
wS, wB, wS, wB,
*h, r, 0, *h, r, 0,
wa, r"))] wa, r"))]
"TARGET_POWERPC64 "TARGET_POWERPC64
&& (gpc_reg_operand (operands[0], DImode) && (gpc_reg_operand (operands[0], DImode)
|| gpc_reg_operand (operands[1], DImode))" || gpc_reg_operand (operands[1], DImode))"
...@@ -8885,33 +8885,33 @@ ...@@ -8885,33 +8885,33 @@
mfvsrd %0,%x1 mfvsrd %0,%x1
mtvsrd %x0,%1" mtvsrd %x0,%1"
[(set_attr "type" [(set_attr "type"
"store, load, *, "store, load, *,
*, *, *, *, *, *,
fpstore, fpload, fpsimple, fpstore, fpload, fpsimple,
fpstore, fpstore, fpload, fpload, veclogical, fpstore, fpstore, fpload, fpload, veclogical,
vecsimple, vecsimple, vecsimple, veclogical, veclogical, vecsimple, vecsimple, vecsimple, veclogical, veclogical,
vecsimple, vecsimple, vecsimple, vecsimple,
mfjmpr, mtjmpr, *, mfjmpr, mtjmpr, *,
mftgpr, mffgpr") mftgpr, mffgpr")
(set_attr "size" "64") (set_attr "size" "64")
(set_attr "length" (set_attr "length"
"*, *, *, "*, *, *,
*, *, 20, *, *, 20,
*, *, *, *, *, *,
*, *, *, *, *, *, *, *, *, *,
*, *, *, *, *, *, *, *, *, *,
8, *, 8, *,
*, *, *, *, *, *,
*, *") *, *")
(set_attr "isa" (set_attr "isa"
"*, *, *, "*, *, *,
*, *, *, *, *, *,
*, *, *, *, *, *,
p9v, p7v, p9v, p7v, *, p9v, p7v, p9v, p7v, *,
p9v, p9v, p7v, *, *, p9v, p9v, p7v, *, *,
p7v, p7v, p7v, p7v,
*, *, *, *, *, *,
p8v, p8v")]) p8v, p8v")])
; Some DImode loads are best done as a load of -1 followed by a mask ; Some DImode loads are best done as a load of -1 followed by a mask
; instruction. ; instruction.
......
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