Skip to content

R
riscv-gcc-1
Commit 303f8933 by Dan Nicolaescu Committed by Richard Henderson
Options

sparc.md (ldd peephole2s): For load peepholes pass the destination register as a parameter to... 

        * config/sparc/sparc.md (ldd peephole2s): For load peepholes pass
        the destination register as a parameter to mems_ok_for_ldd_peep.
        For store peepholes pass NULL_RTX.  Move all volatile checks ...
        * config/sparc/sparc.c (mems_ok_for_ldd_peep): ... here.  Add a
        register parameter, check it's not the same as base for an address.
        * config/sparc/sparc-protos.h (mems_ok_for_ldd_peep): Update.

From-SVN: r48188
parent 30fa7e33
Showing with 63 additions and 57 deletions
gcc/ChangeLog
2001-12-19 Dan Nicolaescu <dann@ics.uci.edu>
* config/sparc/sparc.md (ldd peephole2s): For load peepholes pass
the destination register as a parameter to mems_ok_for_ldd_peep.
For store peepholes pass NULL_RTX. Move all volatile checks ...
* config/sparc/sparc.c (mems_ok_for_ldd_peep): ... here. Add a
register parameter, check it's not the same as base for an address.
* config/sparc/sparc-protos.h (mems_ok_for_ldd_peep): Update.
2001-12-19 Jakub Jelinek <jakub@redhat.com>
* config/ia64/ia64.c (ia64_single_set): Return first set for
......@@ -151,7 +160,7 @@ objc:
2001-12-17 Aldy Hernandez <aldyh@redhat.com>
* config/rs6000/rs6000.c: Remove is_gpr_return_reg prototype.
* config/rs6000/rs6000.c: Remove is_gpr_return_reg prototype.
2001-12-17 Neil Booth <neil@daikokuya.demon.co.uk>
......@@ -179,7 +188,7 @@ Mon Dec 17 14:21:21 2001 Jeffrey A Law (law@redhat.com)
definition.
* doc/tm.texi: Document MODE_BASE_REG_CLASS.
* config/arm/arm.h (MODE_BASE_REG_CLASS): Define.
* config/arm/arm.h (MODE_BASE_REG_CLASS): Define.
2001-12-17 Joseph S. Myers <jsm28@cam.ac.uk>
......@@ -202,12 +211,12 @@ Mon Dec 17 14:21:21 2001 Jeffrey A Law (law@redhat.com)
2001-12-17 Dale Johannesen <dalej@apple.com>
* config/rs6000/rs6000.h: CPP_CPU_SPEC: add mcpu=7400.
ASM_CPU_SPEC: Ditto.
RTX_COSTS: Fix timing info for 7450 multiply.
* config/rs6000/rs6000.md: Fix timing info for 7450 imul.
Allow floats to be kept in int regs in movsf_low,
movsf_low_st (Darwin only)
* config/rs6000/rs6000.h: CPP_CPU_SPEC: add mcpu=7400.
ASM_CPU_SPEC: Ditto.
RTX_COSTS: Fix timing info for 7450 multiply.
* config/rs6000/rs6000.md: Fix timing info for 7450 imul.
Allow floats to be kept in int regs in movsf_low,
movsf_low_st (Darwin only)
2001-12-17 Aldy Hernandez <aldyh@redhat.com>
......@@ -294,7 +303,7 @@ Mon Dec 17 17:57:05 CET 2001 Jan Hubicka <jh@suse.cz>
(dw2_asm_output_nstring): Use assemble_integer for the null terminator.
(dw2_asm_output_data_uleb128, dw2_asm_output_data_sleb128): Use
integer_asm_op to get the byte pseudo-op. Use assemble_integer
if it returns NULL.
if it returns NULL.
* dwarf2asm.h (dw2_assemble_integer): Declare.
* dwarfout.c: Include dwarf2asm.h. Use dwarf2 functions for the
default implementation of most macros.
......@@ -526,7 +535,7 @@ Mon Dec 17 17:57:05 CET 2001 Jan Hubicka <jh@suse.cz>
2001-12-16 Aldy Hernandez <aldyh@redhat.com>
* config.gcc: Add powerpc-*-eabisimaltivec*.
* config.gcc: Add powerpc-*-eabisimaltivec*.
2001-12-16 Neil Booth <neil@daikokuya.demon.co.uk>
......@@ -625,15 +634,15 @@ Sun Dec 16 13:13:01 2001 Richard Kenner <kenner@vlsi1.ultra.nyu.edu>
2001-12-15 Dan Nicolaescu <dann@ics.uci.edu>
* config/sparc/sparc.c (mems_ok_for_ldd_peep): Rename from
* config/sparc/sparc.c (mems_ok_for_ldd_peep): Rename from
addrs_ok_for_ldd_peep_withmem; take MEMs as parameters, not
addrs; eliminate restriction of only using fp and sp as base
registers.
* config/sparc/sparc-protos.h: Update.
* config/sparc/sparc.md (movdi): Use TARGET_V9 not TARGET_ARCH64.
(*cmp_cc_set, *cmp_ccx_set64, *movdi_zero): New insns derived
from old define_peepholes.
Convert all the ldd/std peepholes to peephole2.
addrs; eliminate restriction of only using fp and sp as base
registers.
* config/sparc/sparc-protos.h: Update.
* config/sparc/sparc.md (movdi): Use TARGET_V9 not TARGET_ARCH64.
(*cmp_cc_set, *cmp_ccx_set64, *movdi_zero): New insns derived
from old define_peepholes.
Convert all the ldd/std peepholes to peephole2.
2001-12-15 Ulrich Weigand <uweigand@de.ibm.com>
......
gcc/config/sparc/sparc-protos.h
......@@ -91,7 +91,7 @@ extern const char *output_sibcall PARAMS ((rtx, rtx));
extern char *output_v9branch PARAMS ((rtx, int, int, int, int, int, rtx));
extern void emit_v9_brxx_insn PARAMS ((enum rtx_code, rtx, rtx));
extern void print_operand PARAMS ((FILE *, rtx, int));
extern int mems_ok_for_ldd_peep PARAMS ((rtx, rtx));
extern int mems_ok_for_ldd_peep PARAMS ((rtx, rtx, rtx));
extern int arith_double_4096_operand PARAMS ((rtx, enum machine_mode));
extern int arith_4096_operand PARAMS ((rtx, enum machine_mode));
extern int zero_operand PARAMS ((rtx, enum machine_mode));
......
gcc/config/sparc/sparc.c
......@@ -5673,27 +5673,41 @@ registers_ok_for_ldd_peep (reg1, reg2)
}
/* Return 1 if the addresses in mem1 and mem2 are suitable for use in
an ldd or std insn.
an ldd or std insn.
This can only happen when addr1 and addr2, the addresses in mem1
and mem2, are consecutive memory locations (addr1 + 4 == addr2).
addr1 must also be aligned on a 64-bit boundary. */
addr1 must also be aligned on a 64-bit boundary.
Also iff dependent_reg_rtx is not null it should not be used to
compute the address for mem1, i.e. we cannot optimize a sequence
like:
ld [%o0], %o0
ld [%o0 + 4], %o1
to
ldd [%o0], o0
For stores we don't have a similar problem, so dependent_reg_rtx is
NULL_RTX. */
int
mems_ok_for_ldd_peep (mem1, mem2)
rtx mem1, mem2;
mems_ok_for_ldd_peep (mem1, mem2, dependent_reg_rtx)
rtx mem1, mem2, dependent_reg_rtx;
{
rtx addr1, addr2;
unsigned int reg1;
int offset1;
addr1 = XEXP (mem1, 0);
addr2 = XEXP (mem2, 0);
/* The mems cannot be volatile. */
if (MEM_VOLATILE_P (mem1) || MEM_VOLATILE_P (mem2))
return 0;
/* mem1 should be aligned on a 64-bit boundary */
/* MEM1 should be aligned on a 64-bit boundary. */
if (MEM_ALIGN (mem1) < 64)
return 0;
addr1 = XEXP (mem1, 0);
addr2 = XEXP (mem2, 0);
/* Extract a register number and offset (if used) from the first addr. */
if (GET_CODE (addr1) == PLUS)
{
......@@ -5729,6 +5743,9 @@ mems_ok_for_ldd_peep (mem1, mem2)
if (reg1 != REGNO (XEXP (addr2, 0)))
return 0;
if (dependent_reg_rtx != NULL_RTX && reg1 == REGNO (dependent_reg_rtx))
return 0;
/* The first offset must be evenly divisible by 8 to ensure the
address is 64 bit aligned. */
if (offset1 % 8 != 0)
......
gcc/config/sparc/sparc.md
......@@ -8923,9 +8923,7 @@
(set (match_operand:SI 1 "memory_operand" "")
(const_int 0))]
"TARGET_V9
&& ! MEM_VOLATILE_P (operands[0])
&& ! MEM_VOLATILE_P (operands[1])
&& mems_ok_for_ldd_peep (operands[0], operands[1])"
&& mems_ok_for_ldd_peep (operands[0], operands[1], NULL_RTX)"
[(set (match_dup 0)
(const_int 0))]
"operands[0] = change_address (operands[0], DImode, NULL);")
......@@ -8936,9 +8934,7 @@
(set (match_operand:SI 1 "memory_operand" "")
(const_int 0))]
"TARGET_V9
&& ! MEM_VOLATILE_P (operands[0])
&& ! MEM_VOLATILE_P (operands[1])
&& mems_ok_for_ldd_peep (operands[1], operands[0])"
&& mems_ok_for_ldd_peep (operands[1], operands[0], NULL_RTX)"
[(set (match_dup 1)
(const_int 0))]
"operands[1] = change_address (operands[1], DImode, NULL);")
......@@ -8949,9 +8945,7 @@
(set (match_operand:SI 2 "register_operand" "")
(match_operand:SI 3 "memory_operand" ""))]
"registers_ok_for_ldd_peep (operands[0], operands[2])
&& ! MEM_VOLATILE_P (operands[1])
&& ! MEM_VOLATILE_P (operands[3])
&& mems_ok_for_ldd_peep (operands[1], operands[3])"
&& mems_ok_for_ldd_peep (operands[1], operands[3], operands[0])"
[(set (match_dup 0)
(match_dup 1))]
"operands[1] = change_address (operands[1], DImode, NULL);
......@@ -8963,9 +8957,7 @@
(set (match_operand:SI 2 "memory_operand" "")
(match_operand:SI 3 "register_operand" ""))]
"registers_ok_for_ldd_peep (operands[1], operands[3])
&& ! MEM_VOLATILE_P (operands[0])
&& ! MEM_VOLATILE_P (operands[2])
&& mems_ok_for_ldd_peep (operands[0], operands[2])"
&& mems_ok_for_ldd_peep (operands[0], operands[2], NULL_RTX)"
[(set (match_dup 0)
(match_dup 1))]
"operands[0] = change_address (operands[0], DImode, NULL);
......@@ -8977,9 +8969,7 @@
(set (match_operand:SF 2 "register_operand" "")
(match_operand:SF 3 "memory_operand" ""))]
"registers_ok_for_ldd_peep (operands[0], operands[2])
&& ! MEM_VOLATILE_P (operands[1])
&& ! MEM_VOLATILE_P (operands[3])
&& mems_ok_for_ldd_peep (operands[1], operands[3])"
&& mems_ok_for_ldd_peep (operands[1], operands[3], operands[0])"
[(set (match_dup 0)
(match_dup 1))]
"operands[1] = change_address (operands[1], DFmode, NULL);
......@@ -8991,9 +8981,7 @@
(set (match_operand:SF 2 "memory_operand" "")
(match_operand:SF 3 "register_operand" ""))]
"registers_ok_for_ldd_peep (operands[1], operands[3])
&& ! MEM_VOLATILE_P (operands[0])
&& ! MEM_VOLATILE_P (operands[2])
&& mems_ok_for_ldd_peep (operands[0], operands[2])"
&& mems_ok_for_ldd_peep (operands[0], operands[2], NULL_RTX)"
[(set (match_dup 0)
(match_dup 1))]
"operands[0] = change_address (operands[0], DFmode, NULL);
......@@ -9005,9 +8993,7 @@
(set (match_operand:SI 2 "register_operand" "")
(match_operand:SI 3 "memory_operand" ""))]
"registers_ok_for_ldd_peep (operands[2], operands[0])
&& ! MEM_VOLATILE_P (operands[3])
&& ! MEM_VOLATILE_P (operands[1])
&& mems_ok_for_ldd_peep (operands[3], operands[1])"
&& mems_ok_for_ldd_peep (operands[3], operands[1], operands[2])"
[(set (match_dup 2)
(match_dup 3))]
"operands[3] = change_address (operands[3], DImode, NULL);
......@@ -9019,9 +9005,7 @@
(set (match_operand:SI 2 "memory_operand" "")
(match_operand:SI 3 "register_operand" ""))]
"registers_ok_for_ldd_peep (operands[3], operands[1])
&& ! MEM_VOLATILE_P (operands[2])
&& ! MEM_VOLATILE_P (operands[0])
&& mems_ok_for_ldd_peep (operands[2], operands[0])"
&& mems_ok_for_ldd_peep (operands[2], operands[0], NULL_RTX)"
[(set (match_dup 2)
(match_dup 3))]
"operands[2] = change_address (operands[2], DImode, NULL);
......@@ -9034,9 +9018,7 @@
(set (match_operand:SF 2 "register_operand" "")
(match_operand:SF 3 "memory_operand" ""))]
"registers_ok_for_ldd_peep (operands[2], operands[0])
&& ! MEM_VOLATILE_P (operands[3])
&& ! MEM_VOLATILE_P (operands[1])
&& mems_ok_for_ldd_peep (operands[3], operands[1])"
&& mems_ok_for_ldd_peep (operands[3], operands[1], operands[2])"
[(set (match_dup 2)
(match_dup 3))]
"operands[3] = change_address (operands[3], DFmode, NULL);
......@@ -9048,9 +9030,7 @@
(set (match_operand:SF 2 "memory_operand" "")
(match_operand:SF 3 "register_operand" ""))]
"registers_ok_for_ldd_peep (operands[3], operands[1])
&& ! MEM_VOLATILE_P (operands[2])
&& ! MEM_VOLATILE_P (operands[0])
&& mems_ok_for_ldd_peep (operands[2], operands[0])"
&& mems_ok_for_ldd_peep (operands[2], operands[0], NULL_RTX)"
[(set (match_dup 2)
(match_dup 3))]
"operands[2] = change_address (operands[2], DFmode, NULL);
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment