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Commit 2f6403f1 by Terry Guo Committed by Xuepeng Guo
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arm-cores.def (cortex-m7): New core name. 

2014-09-30  Terry Guo  <terry.guo@arm.com>

	* config/arm/arm-cores.def (cortex-m7): New core name.
	* config/arm/arm-fpus.def (fpv5-sp-d16): New fpu name.
	(fpv5-d16): Ditto.
	* config/arm/arm-tables.opt: Regenerated.
	* config/arm/arm-tune.md: Regenerated.
	* config/arm/arm.h (TARGET_VFP5): New macro.
	* config/arm/bpabi.h (BE8_LINK_SPEC): Include cortex-m7.
	* config/arm/vfp.md (<vrint_pattern><SDF:mode>2,
	smax<mode>3, smin<mode>3): Enabled for FPU FPv5.
	* doc/invoke.texi: Document new cpu and fpu names.

From-SVN: r215711
parent 24f21354
Showing with 45 additions and 14 deletions
gcc/ChangeLog
2014-09-30 Terry Guo <terry.guo@arm.com>
* config/arm/arm-cores.def (cortex-m7): New core name.
* config/arm/arm-fpus.def (fpv5-sp-d16): New fpu name.
(fpv5-d16): Ditto.
* config/arm/arm-tables.opt: Regenerated.
* config/arm/arm-tune.md: Regenerated.
* config/arm/arm.h (TARGET_VFP5): New macro.
* config/arm/bpabi.h (BE8_LINK_SPEC): Include cortex-m7.
* config/arm/vfp.md (<vrint_pattern><SDF:mode>2,
smax<mode>3, smin<mode>3): Enabled for FPU FPv5.
* doc/invoke.texi: Document new cpu and fpu names.
2014-09-30 Jiong Wang <jiong.wang@arm.com> 2014-09-30 Jiong Wang <jiong.wang@arm.com>
* shrink-wrap.c (move_insn_for_shrink_wrap): Check "can_throw_internal" * shrink-wrap.c (move_insn_for_shrink_wrap): Check "can_throw_internal"
gcc/config/arm/arm-cores.def
...@@ -149,6 +149,7 @@ ARM_CORE("cortex-r4", cortexr4, cortexr4, 7R, FL_LDSCHED, cortex) ...@@ -149,6 +149,7 @@ ARM_CORE("cortex-r4", cortexr4, cortexr4, 7R, FL_LDSCHED, cortex)
ARM_CORE("cortex-r4f", cortexr4f, cortexr4f, 7R, FL_LDSCHED, cortex) ARM_CORE("cortex-r4f", cortexr4f, cortexr4f, 7R, FL_LDSCHED, cortex)
ARM_CORE("cortex-r5", cortexr5, cortexr5, 7R, FL_LDSCHED | FL_ARM_DIV, cortex) ARM_CORE("cortex-r5", cortexr5, cortexr5, 7R, FL_LDSCHED | FL_ARM_DIV, cortex)
ARM_CORE("cortex-r7", cortexr7, cortexr7, 7R, FL_LDSCHED | FL_ARM_DIV, cortex) ARM_CORE("cortex-r7", cortexr7, cortexr7, 7R, FL_LDSCHED | FL_ARM_DIV, cortex)
ARM_CORE("cortex-m7", cortexm7, cortexm7, 7EM, FL_LDSCHED, v7m)
ARM_CORE("cortex-m4", cortexm4, cortexm4, 7EM, FL_LDSCHED, v7m) ARM_CORE("cortex-m4", cortexm4, cortexm4, 7EM, FL_LDSCHED, v7m)
ARM_CORE("cortex-m3", cortexm3, cortexm3, 7M, FL_LDSCHED, v7m) ARM_CORE("cortex-m3", cortexm3, cortexm3, 7M, FL_LDSCHED, v7m)
ARM_CORE("marvell-pj4", marvell_pj4, marvell_pj4, 7A, FL_LDSCHED, 9e) ARM_CORE("marvell-pj4", marvell_pj4, marvell_pj4, 7A, FL_LDSCHED, 9e)
......
gcc/config/arm/arm-fpus.def
...@@ -37,6 +37,8 @@ ARM_FPU("neon-fp16", ARM_FP_MODEL_VFP, 3, VFP_REG_D32, true, true, false) ...@@ -37,6 +37,8 @@ ARM_FPU("neon-fp16", ARM_FP_MODEL_VFP, 3, VFP_REG_D32, true, true, false)
ARM_FPU("vfpv4", ARM_FP_MODEL_VFP, 4, VFP_REG_D32, false, true, false) ARM_FPU("vfpv4", ARM_FP_MODEL_VFP, 4, VFP_REG_D32, false, true, false)
ARM_FPU("vfpv4-d16", ARM_FP_MODEL_VFP, 4, VFP_REG_D16, false, true, false) ARM_FPU("vfpv4-d16", ARM_FP_MODEL_VFP, 4, VFP_REG_D16, false, true, false)
ARM_FPU("fpv4-sp-d16", ARM_FP_MODEL_VFP, 4, VFP_REG_SINGLE, false, true, false) ARM_FPU("fpv4-sp-d16", ARM_FP_MODEL_VFP, 4, VFP_REG_SINGLE, false, true, false)
ARM_FPU("fpv5-sp-d16", ARM_FP_MODEL_VFP, 5, VFP_REG_SINGLE, false, true, false)
ARM_FPU("fpv5-d16", ARM_FP_MODEL_VFP, 5, VFP_REG_D16, false, true, false)
ARM_FPU("neon-vfpv4", ARM_FP_MODEL_VFP, 4, VFP_REG_D32, true, true, false) ARM_FPU("neon-vfpv4", ARM_FP_MODEL_VFP, 4, VFP_REG_D32, true, true, false)
ARM_FPU("fp-armv8", ARM_FP_MODEL_VFP, 8, VFP_REG_D32, false, true, false) ARM_FPU("fp-armv8", ARM_FP_MODEL_VFP, 8, VFP_REG_D32, false, true, false)
ARM_FPU("neon-fp-armv8",ARM_FP_MODEL_VFP, 8, VFP_REG_D32, true, true, false) ARM_FPU("neon-fp-armv8",ARM_FP_MODEL_VFP, 8, VFP_REG_D32, true, true, false)
......
gcc/config/arm/arm-tables.opt
...@@ -274,6 +274,9 @@ EnumValue ...@@ -274,6 +274,9 @@ EnumValue
Enum(processor_type) String(cortex-r7) Value(cortexr7) Enum(processor_type) String(cortex-r7) Value(cortexr7)
EnumValue EnumValue
Enum(processor_type) String(cortex-m7) Value(cortexm7)
EnumValue
Enum(processor_type) String(cortex-m4) Value(cortexm4) Enum(processor_type) String(cortex-m4) Value(cortexm4)
EnumValue EnumValue
...@@ -423,17 +426,23 @@ EnumValue ...@@ -423,17 +426,23 @@ EnumValue
Enum(arm_fpu) String(fpv4-sp-d16) Value(11) Enum(arm_fpu) String(fpv4-sp-d16) Value(11)
EnumValue EnumValue
Enum(arm_fpu) String(neon-vfpv4) Value(12) Enum(arm_fpu) String(fpv5-sp-d16) Value(12)
EnumValue
Enum(arm_fpu) String(fpv5-d16) Value(13)
EnumValue
Enum(arm_fpu) String(neon-vfpv4) Value(14)
EnumValue EnumValue
Enum(arm_fpu) String(fp-armv8) Value(13) Enum(arm_fpu) String(fp-armv8) Value(15)
EnumValue EnumValue
Enum(arm_fpu) String(neon-fp-armv8) Value(14) Enum(arm_fpu) String(neon-fp-armv8) Value(16)
EnumValue EnumValue
Enum(arm_fpu) String(crypto-neon-fp-armv8) Value(15) Enum(arm_fpu) String(crypto-neon-fp-armv8) Value(17)
EnumValue EnumValue
Enum(arm_fpu) String(vfp3) Value(16) Enum(arm_fpu) String(vfp3) Value(18)
gcc/config/arm/arm-tune.md
...@@ -28,7 +28,8 @@ ...@@ -28,7 +28,8 @@
genericv7a,cortexa5,cortexa7, genericv7a,cortexa5,cortexa7,
cortexa8,cortexa9,cortexa12, cortexa8,cortexa9,cortexa12,
cortexa15,cortexr4,cortexr4f, cortexa15,cortexr4,cortexr4f,
cortexr5,cortexr7,cortexm4, cortexr5,cortexr7,cortexm7,
cortexm3,marvell_pj4,cortexa15cortexa7, cortexm4,cortexm3,marvell_pj4,
cortexa53,cortexa57,cortexa57cortexa53" cortexa15cortexa7,cortexa53,cortexa57,
cortexa57cortexa53"
(const (symbol_ref "((enum attr_tune) arm_tune)"))) (const (symbol_ref "((enum attr_tune) arm_tune)")))
gcc/config/arm/arm.h
...@@ -296,6 +296,9 @@ extern void (*arm_lang_output_object_attributes_hook)(void); ...@@ -296,6 +296,9 @@ extern void (*arm_lang_output_object_attributes_hook)(void);
/* FPU supports VFPv3 instructions. */ /* FPU supports VFPv3 instructions. */
#define TARGET_VFP3 (TARGET_VFP && arm_fpu_desc->rev >= 3) #define TARGET_VFP3 (TARGET_VFP && arm_fpu_desc->rev >= 3)
/* FPU supports FPv5 instructions. */
#define TARGET_VFP5 (TARGET_VFP && arm_fpu_desc->rev >= 5)
/* FPU only supports VFP single-precision instructions. */ /* FPU only supports VFP single-precision instructions. */
#define TARGET_VFP_SINGLE (TARGET_VFP && arm_fpu_desc->regs == VFP_REG_SINGLE) #define TARGET_VFP_SINGLE (TARGET_VFP && arm_fpu_desc->regs == VFP_REG_SINGLE)
......
gcc/config/arm/bpabi.h
...@@ -73,7 +73,7 @@ ...@@ -73,7 +73,7 @@
|mcpu=generic-armv7-a \ |mcpu=generic-armv7-a \
|march=armv7ve \ |march=armv7ve \
|march=armv7-m|mcpu=cortex-m3 \ |march=armv7-m|mcpu=cortex-m3 \
|march=armv7e-m|mcpu=cortex-m4 \ |march=armv7e-m|mcpu=cortex-m4|mcpu=cortex-m7 \
|march=armv6-m|mcpu=cortex-m0 \ |march=armv6-m|mcpu=cortex-m0 \
|march=armv8-a \ |march=armv8-a \
:%{!r:--be8}}}" :%{!r:--be8}}}"
...@@ -91,7 +91,7 @@ ...@@ -91,7 +91,7 @@
|mcpu=generic-armv7-a \ |mcpu=generic-armv7-a \
|march=armv7ve \ |march=armv7ve \
|march=armv7-m|mcpu=cortex-m3 \ |march=armv7-m|mcpu=cortex-m3 \
|march=armv7e-m|mcpu=cortex-m4 \ |march=armv7e-m|mcpu=cortex-m4|mcpu=cortex-m7 \
|march=armv6-m|mcpu=cortex-m0 \ |march=armv6-m|mcpu=cortex-m0 \
|march=armv8-a \ |march=armv8-a \
:%{!r:--be8}}}" :%{!r:--be8}}}"
......
gcc/config/arm/vfp.md
...@@ -1298,7 +1298,7 @@ ...@@ -1298,7 +1298,7 @@
(unspec:SDF [(match_operand:SDF 1 (unspec:SDF [(match_operand:SDF 1
"register_operand" "<F_constraint>")] "register_operand" "<F_constraint>")]
VRINT))] VRINT))]
"TARGET_HARD_FLOAT && TARGET_FPU_ARMV8 <vfp_double_cond>" "TARGET_HARD_FLOAT && TARGET_VFP5 <vfp_double_cond>"
"vrint<vrint_variant>%?.<V_if_elem>\\t%<V_reg>0, %<V_reg>1" "vrint<vrint_variant>%?.<V_if_elem>\\t%<V_reg>0, %<V_reg>1"
[(set_attr "predicable" "<vrint_predicable>") [(set_attr "predicable" "<vrint_predicable>")
(set_attr "predicable_short_it" "no") (set_attr "predicable_short_it" "no")
...@@ -1329,7 +1329,7 @@ ...@@ -1329,7 +1329,7 @@
[(set (match_operand:SDF 0 "register_operand" "=<F_constraint>") [(set (match_operand:SDF 0 "register_operand" "=<F_constraint>")
(smax:SDF (match_operand:SDF 1 "register_operand" "<F_constraint>") (smax:SDF (match_operand:SDF 1 "register_operand" "<F_constraint>")
(match_operand:SDF 2 "register_operand" "<F_constraint>")))] (match_operand:SDF 2 "register_operand" "<F_constraint>")))]
"TARGET_HARD_FLOAT && TARGET_FPU_ARMV8 <vfp_double_cond>" "TARGET_HARD_FLOAT && TARGET_VFP5 <vfp_double_cond>"
"vmaxnm.<V_if_elem>\\t%<V_reg>0, %<V_reg>1, %<V_reg>2" "vmaxnm.<V_if_elem>\\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
[(set_attr "type" "f_minmax<vfp_type>") [(set_attr "type" "f_minmax<vfp_type>")
(set_attr "conds" "unconditional")] (set_attr "conds" "unconditional")]
...@@ -1339,7 +1339,7 @@ ...@@ -1339,7 +1339,7 @@
[(set (match_operand:SDF 0 "register_operand" "=<F_constraint>") [(set (match_operand:SDF 0 "register_operand" "=<F_constraint>")
(smin:SDF (match_operand:SDF 1 "register_operand" "<F_constraint>") (smin:SDF (match_operand:SDF 1 "register_operand" "<F_constraint>")
(match_operand:SDF 2 "register_operand" "<F_constraint>")))] (match_operand:SDF 2 "register_operand" "<F_constraint>")))]
"TARGET_HARD_FLOAT && TARGET_FPU_ARMV8 <vfp_double_cond>" "TARGET_HARD_FLOAT && TARGET_VFP5 <vfp_double_cond>"
"vminnm.<V_if_elem>\\t%<V_reg>0, %<V_reg>1, %<V_reg>2" "vminnm.<V_if_elem>\\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
[(set_attr "type" "f_minmax<vfp_type>") [(set_attr "type" "f_minmax<vfp_type>")
(set_attr "conds" "unconditional")] (set_attr "conds" "unconditional")]
......
gcc/doc/invoke.texi
...@@ -12632,7 +12632,8 @@ Permissible names are: @samp{arm2}, @samp{arm250}, ...@@ -12632,7 +12632,8 @@ Permissible names are: @samp{arm2}, @samp{arm250},
@samp{cortex-a5}, @samp{cortex-a7}, @samp{cortex-a8}, @samp{cortex-a9}, @samp{cortex-a5}, @samp{cortex-a7}, @samp{cortex-a8}, @samp{cortex-a9},
@samp{cortex-a12}, @samp{cortex-a15}, @samp{cortex-a53}, @samp{cortex-a57}, @samp{cortex-a12}, @samp{cortex-a15}, @samp{cortex-a53}, @samp{cortex-a57},
@samp{cortex-r4}, @samp{cortex-r4},
@samp{cortex-r4f}, @samp{cortex-r5}, @samp{cortex-r7}, @samp{cortex-m4}, @samp{cortex-r4f}, @samp{cortex-r5}, @samp{cortex-r7}, @samp{cortex-m7},
@samp{cortex-m4},
@samp{cortex-m3}, @samp{cortex-m3},
@samp{cortex-m1}, @samp{cortex-m1},
@samp{cortex-m0}, @samp{cortex-m0},
...@@ -12686,6 +12687,7 @@ available on the target. Permissible names are: @samp{vfp}, @samp{vfpv3}, ...@@ -12686,6 +12687,7 @@ available on the target. Permissible names are: @samp{vfp}, @samp{vfpv3},
@samp{vfpv3-fp16}, @samp{vfpv3-d16}, @samp{vfpv3-d16-fp16}, @samp{vfpv3xd}, @samp{vfpv3-fp16}, @samp{vfpv3-d16}, @samp{vfpv3-d16-fp16}, @samp{vfpv3xd},
@samp{vfpv3xd-fp16}, @samp{neon}, @samp{neon-fp16}, @samp{vfpv4}, @samp{vfpv3xd-fp16}, @samp{neon}, @samp{neon-fp16}, @samp{vfpv4},
@samp{vfpv4-d16}, @samp{fpv4-sp-d16}, @samp{neon-vfpv4}, @samp{vfpv4-d16}, @samp{fpv4-sp-d16}, @samp{neon-vfpv4},
@samp{fpv5-d16}, @samp{fpv5-sp-d16},
@samp{fp-armv8}, @samp{neon-fp-armv8}, and @samp{crypto-neon-fp-armv8}. @samp{fp-armv8}, @samp{neon-fp-armv8}, and @samp{crypto-neon-fp-armv8}.
If @option{-msoft-float} is specified this specifies the format of If @option{-msoft-float} is specified this specifies the format of
......
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