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Commit 2f5b1308 by Joern Rennecke Committed by Joern Rennecke
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re PR target/46735 (frv-elf --enable-werror-always build fails for 64 bit host) 

	PR target/46735
	* config/frv/predicates.md (gpr_or_int12_operand): Use IN_RANGE.
	(gpr_fpr_or_int12_operand, gpr_or_int10_operand): Likewise.
	(int12_operand, int_2word_operand, uint16_operand): Likewise.
	(fpr_or_int6_operand, int6_operand, int5_operand): Likewise.
	(uint5_operand, uint4_operand): Likewise.
	* config/frv/frv.h (IN_RANGE_P): Delete.
	(GPR_P, FPR_P, CC_P, ICC_P, FCC_P, CR_P, ICR_P, FCR_P): Use IN_RANGE.
	(ACC_P, ACCG_P, SPR_P, CONST_OK_FOR_I, CONST_OK_FOR_J): Likewise.
	(CONST_OK_FOR_L, CONST_OK_FOR_M, CONST_OK_FOR_N): Likewise.
	(CONST_OK_FOR_P): Likewise.
	* config/frv/frv.md (*movqicc_internal2_int): Likewise.
	(*movqicc_internal2_float, *movhicc_internal2_int): Likewise.
	(*movhicc_internal2_float, *movsicc_internal2_int): Likewise.
	(*movsicc_internal2_float, casesi): Likewise.
	* config/frv/frv.c (frv_frame_offset_rtx): Likewise.
	(frv_asm_output_mi_thunk, frv_legitimate_address_p_1): Likewise.
	(frv_emit_movsi, output_move_single, frv_emit_cond_move): Likewise.
	(frv_split_cond_move, frv_rtx_costs): Likewise.

From-SVN: r167508
parent c0f9d583
Showing with 84 additions and 68 deletions
gcc/ChangeLog
2010-12-06 Joern Rennecke <amylaar@spamcop.net>
PR target/46735
* config/frv/predicates.md (gpr_or_int12_operand): Use IN_RANGE.
(gpr_fpr_or_int12_operand, gpr_or_int10_operand): Likewise.
(int12_operand, int_2word_operand, uint16_operand): Likewise.
(fpr_or_int6_operand, int6_operand, int5_operand): Likewise.
(uint5_operand, uint4_operand): Likewise.
* config/frv/frv.h (IN_RANGE_P): Delete.
(GPR_P, FPR_P, CC_P, ICC_P, FCC_P, CR_P, ICR_P, FCR_P): Use IN_RANGE.
(ACC_P, ACCG_P, SPR_P, CONST_OK_FOR_I, CONST_OK_FOR_J): Likewise.
(CONST_OK_FOR_L, CONST_OK_FOR_M, CONST_OK_FOR_N): Likewise.
(CONST_OK_FOR_P): Likewise.
* config/frv/frv.md (*movqicc_internal2_int): Likewise.
(*movqicc_internal2_float, *movhicc_internal2_int): Likewise.
(*movhicc_internal2_float, *movsicc_internal2_int): Likewise.
(*movsicc_internal2_float, casesi): Likewise.
* config/frv/frv.c (frv_frame_offset_rtx): Likewise.
(frv_asm_output_mi_thunk, frv_legitimate_address_p_1): Likewise.
(frv_emit_movsi, output_move_single, frv_emit_cond_move): Likewise.
(frv_split_cond_move, frv_rtx_costs): Likewise.
2010-12-06 H.J. Lu <hongjiu.lu@intel.com> 2010-12-06 H.J. Lu <hongjiu.lu@intel.com>
* config/i386/i386.c (m_COREI7): New. * config/i386/i386.c (m_COREI7): New.
gcc/config/frv/frv.c
...@@ -1624,12 +1624,12 @@ static rtx ...@@ -1624,12 +1624,12 @@ static rtx
frv_frame_offset_rtx (int offset) frv_frame_offset_rtx (int offset)
{ {
rtx offset_rtx = GEN_INT (offset); rtx offset_rtx = GEN_INT (offset);
if (IN_RANGE_P (offset, -2048, 2047)) if (IN_RANGE (offset, -2048, 2047))
return offset_rtx; return offset_rtx;
else else
{ {
rtx reg_rtx = gen_rtx_REG (SImode, OFFSET_REGNO); rtx reg_rtx = gen_rtx_REG (SImode, OFFSET_REGNO);
if (IN_RANGE_P (offset, -32768, 32767)) if (IN_RANGE (offset, -32768, 32767))
emit_insn (gen_movsi (reg_rtx, offset_rtx)); emit_insn (gen_movsi (reg_rtx, offset_rtx));
else else
{ {
...@@ -2057,7 +2057,7 @@ frv_asm_output_mi_thunk (FILE *file, ...@@ -2057,7 +2057,7 @@ frv_asm_output_mi_thunk (FILE *file,
const char *parallel = (frv_issue_rate () > 1 ? ".p" : ""); const char *parallel = (frv_issue_rate () > 1 ? ".p" : "");
/* Do the add using an addi if possible. */ /* Do the add using an addi if possible. */
if (IN_RANGE_P (delta, -2048, 2047)) if (IN_RANGE (delta, -2048, 2047))
fprintf (file, "\taddi %s,#%d,%s\n", name_arg0, (int) delta, name_arg0); fprintf (file, "\taddi %s,#%d,%s\n", name_arg0, (int) delta, name_arg0);
else else
{ {
...@@ -3459,13 +3459,13 @@ frv_legitimate_address_p_1 (enum machine_mode mode, ...@@ -3459,13 +3459,13 @@ frv_legitimate_address_p_1 (enum machine_mode mode,
ret = FALSE; ret = FALSE;
else else
{ {
ret = IN_RANGE_P (INTVAL (x), -2048, 2047); ret = IN_RANGE (INTVAL (x), -2048, 2047);
/* If we can't use load/store double operations, make sure we can /* If we can't use load/store double operations, make sure we can
address the second word. */ address the second word. */
if (ret && GET_MODE_SIZE (mode) > UNITS_PER_WORD) if (ret && GET_MODE_SIZE (mode) > UNITS_PER_WORD)
ret = IN_RANGE_P (INTVAL (x) + GET_MODE_SIZE (mode) - 1, ret = IN_RANGE (INTVAL (x) + GET_MODE_SIZE (mode) - 1,
-2048, 2047); -2048, 2047);
} }
break; break;
...@@ -3511,12 +3511,12 @@ frv_legitimate_address_p_1 (enum machine_mode mode, ...@@ -3511,12 +3511,12 @@ frv_legitimate_address_p_1 (enum machine_mode mode,
else else
{ {
value = INTVAL (x1); value = INTVAL (x1);
ret = IN_RANGE_P (value, -2048, 2047); ret = IN_RANGE (value, -2048, 2047);
/* If we can't use load/store double operations, make sure we can /* If we can't use load/store double operations, make sure we can
address the second word. */ address the second word. */
if (ret && GET_MODE_SIZE (mode) > UNITS_PER_WORD) if (ret && GET_MODE_SIZE (mode) > UNITS_PER_WORD)
ret = IN_RANGE_P (value + GET_MODE_SIZE (mode) - 1, -2048, 2047); ret = IN_RANGE (value + GET_MODE_SIZE (mode) - 1, -2048, 2047);
} }
break; break;
...@@ -4076,9 +4076,9 @@ frv_emit_movsi (rtx dest, rtx src) ...@@ -4076,9 +4076,9 @@ frv_emit_movsi (rtx dest, rtx src)
add instruction, so expose this to CSE by copying to add instruction, so expose this to CSE by copying to
an intermediate register. */ an intermediate register. */
|| (GET_CODE (src) == REG || (GET_CODE (src) == REG
&& IN_RANGE_P (REGNO (src), && IN_RANGE (REGNO (src),
FIRST_VIRTUAL_REGISTER, FIRST_VIRTUAL_REGISTER,
LAST_VIRTUAL_POINTER_REGISTER)))) LAST_VIRTUAL_POINTER_REGISTER))))
{ {
emit_insn (gen_rtx_SET (VOIDmode, dest, copy_to_mode_reg (SImode, src))); emit_insn (gen_rtx_SET (VOIDmode, dest, copy_to_mode_reg (SImode, src)));
return TRUE; return TRUE;
...@@ -4380,7 +4380,7 @@ output_move_single (rtx operands[], rtx insn) ...@@ -4380,7 +4380,7 @@ output_move_single (rtx operands[], rtx insn)
else else
value = CONST_DOUBLE_LOW (src); value = CONST_DOUBLE_LOW (src);
if (IN_RANGE_P (value, -32768, 32767)) if (IN_RANGE (value, -32768, 32767))
return "setlos %1, %0"; return "setlos %1, %0";
return "#"; return "#";
...@@ -4951,8 +4951,8 @@ frv_emit_cond_move (rtx dest, rtx test_rtx, rtx src1, rtx src2) ...@@ -4951,8 +4951,8 @@ frv_emit_cond_move (rtx dest, rtx test_rtx, rtx src1, rtx src2)
between the two fits in an addi's range, load up the difference, then between the two fits in an addi's range, load up the difference, then
conditionally move in 0, and then unconditionally add the first conditionally move in 0, and then unconditionally add the first
value. */ value. */
else if (IN_RANGE_P (value1, -2048, 2047) else if (IN_RANGE (value1, -2048, 2047)
&& IN_RANGE_P (value2 - value1, -2048, 2047)) && IN_RANGE (value2 - value1, -2048, 2047))
; ;
/* If neither condition holds, just force the constant into a /* If neither condition holds, just force the constant into a
...@@ -5046,8 +5046,8 @@ frv_split_cond_move (rtx operands[]) ...@@ -5046,8 +5046,8 @@ frv_split_cond_move (rtx operands[])
between the two fits in an addi's range, load up the difference, then between the two fits in an addi's range, load up the difference, then
conditionally move in 0, and then unconditionally add the first conditionally move in 0, and then unconditionally add the first
value. */ value. */
else if (IN_RANGE_P (value1, -2048, 2047) else if (IN_RANGE (value1, -2048, 2047)
&& IN_RANGE_P (value2 - value1, -2048, 2047)) && IN_RANGE (value2 - value1, -2048, 2047))
{ {
rtx dest_si = ((GET_MODE (dest) == SImode) rtx dest_si = ((GET_MODE (dest) == SImode)
? dest ? dest
...@@ -9611,7 +9611,7 @@ frv_rtx_costs (rtx x, ...@@ -9611,7 +9611,7 @@ frv_rtx_costs (rtx x,
{ {
case CONST_INT: case CONST_INT:
/* Make 12-bit integers really cheap. */ /* Make 12-bit integers really cheap. */
if (IN_RANGE_P (INTVAL (x), -2048, 2047)) if (IN_RANGE (INTVAL (x), -2048, 2047))
{ {
*total = 0; *total = 0;
return true; return true;
......
gcc/config/frv/frv.h
...@@ -26,12 +26,6 @@ ...@@ -26,12 +26,6 @@
/* Frv general purpose macros. */ /* Frv general purpose macros. */
/* Align an address. */ /* Align an address. */
#define ADDR_ALIGN(addr,align) (((addr) + (align) - 1) & ~((align) - 1)) #define ADDR_ALIGN(addr,align) (((addr) + (align) - 1) & ~((align) - 1))
/* Return true if a value is inside a range. */
#define IN_RANGE_P(VALUE, LOW, HIGH) \
( (((HOST_WIDE_INT)(VALUE)) >= (HOST_WIDE_INT)(LOW)) \
&& (((HOST_WIDE_INT)(VALUE)) <= ((HOST_WIDE_INT)(HIGH))))
/* Driver configuration. */ /* Driver configuration. */
...@@ -604,18 +598,18 @@ ...@@ -604,18 +598,18 @@
#define IACC_FIRST (SPR_FIRST + 2) #define IACC_FIRST (SPR_FIRST + 2)
#define IACC_LAST (SPR_FIRST + 3) #define IACC_LAST (SPR_FIRST + 3)
#define GPR_P(R) IN_RANGE_P (R, GPR_FIRST, GPR_LAST) #define GPR_P(R) IN_RANGE (R, GPR_FIRST, GPR_LAST)
#define GPR_OR_AP_P(R) (GPR_P (R) || (R) == ARG_POINTER_REGNUM) #define GPR_OR_AP_P(R) (GPR_P (R) || (R) == ARG_POINTER_REGNUM)
#define FPR_P(R) IN_RANGE_P (R, FPR_FIRST, FPR_LAST) #define FPR_P(R) IN_RANGE (R, FPR_FIRST, FPR_LAST)
#define CC_P(R) IN_RANGE_P (R, CC_FIRST, CC_LAST) #define CC_P(R) IN_RANGE (R, CC_FIRST, CC_LAST)
#define ICC_P(R) IN_RANGE_P (R, ICC_FIRST, ICC_LAST) #define ICC_P(R) IN_RANGE (R, ICC_FIRST, ICC_LAST)
#define FCC_P(R) IN_RANGE_P (R, FCC_FIRST, FCC_LAST) #define FCC_P(R) IN_RANGE (R, FCC_FIRST, FCC_LAST)
#define CR_P(R) IN_RANGE_P (R, CR_FIRST, CR_LAST) #define CR_P(R) IN_RANGE (R, CR_FIRST, CR_LAST)
#define ICR_P(R) IN_RANGE_P (R, ICR_FIRST, ICR_LAST) #define ICR_P(R) IN_RANGE (R, ICR_FIRST, ICR_LAST)
#define FCR_P(R) IN_RANGE_P (R, FCR_FIRST, FCR_LAST) #define FCR_P(R) IN_RANGE (R, FCR_FIRST, FCR_LAST)
#define ACC_P(R) IN_RANGE_P (R, ACC_FIRST, ACC_LAST) #define ACC_P(R) IN_RANGE (R, ACC_FIRST, ACC_LAST)
#define ACCG_P(R) IN_RANGE_P (R, ACCG_FIRST, ACCG_LAST) #define ACCG_P(R) IN_RANGE (R, ACCG_FIRST, ACCG_LAST)
#define SPR_P(R) IN_RANGE_P (R, SPR_FIRST, SPR_LAST) #define SPR_P(R) IN_RANGE (R, SPR_FIRST, SPR_LAST)
#define GPR_OR_PSEUDO_P(R) (GPR_P (R) || (R) >= FIRST_PSEUDO_REGISTER) #define GPR_OR_PSEUDO_P(R) (GPR_P (R) || (R) >= FIRST_PSEUDO_REGISTER)
#define FPR_OR_PSEUDO_P(R) (FPR_P (R) || (R) >= FIRST_PSEUDO_REGISTER) #define FPR_OR_PSEUDO_P(R) (FPR_P (R) || (R) >= FIRST_PSEUDO_REGISTER)
...@@ -1166,21 +1160,21 @@ extern enum reg_class reg_class_from_letter[]; ...@@ -1166,21 +1160,21 @@ extern enum reg_class reg_class_from_letter[];
#define ZERO_P(x) (x == CONST0_RTX (GET_MODE (x))) #define ZERO_P(x) (x == CONST0_RTX (GET_MODE (x)))
/* 6-bit signed immediate. */ /* 6-bit signed immediate. */
#define CONST_OK_FOR_I(VALUE) IN_RANGE_P(VALUE, -32, 31) #define CONST_OK_FOR_I(VALUE) IN_RANGE (VALUE, -32, 31)
/* 10-bit signed immediate. */ /* 10-bit signed immediate. */
#define CONST_OK_FOR_J(VALUE) IN_RANGE_P(VALUE, -512, 511) #define CONST_OK_FOR_J(VALUE) IN_RANGE (VALUE, -512, 511)
/* Unused */ /* Unused */
#define CONST_OK_FOR_K(VALUE) 0 #define CONST_OK_FOR_K(VALUE) 0
/* 16-bit signed immediate. */ /* 16-bit signed immediate. */
#define CONST_OK_FOR_L(VALUE) IN_RANGE_P(VALUE, -32768, 32767) #define CONST_OK_FOR_L(VALUE) IN_RANGE (VALUE, -32768, 32767)
/* 16-bit unsigned immediate. */ /* 16-bit unsigned immediate. */
#define CONST_OK_FOR_M(VALUE) IN_RANGE_P (VALUE, 0, 65535) #define CONST_OK_FOR_M(VALUE) IN_RANGE (VALUE, 0, 65535)
/* 12-bit signed immediate that is negative. */ /* 12-bit signed immediate that is negative. */
#define CONST_OK_FOR_N(VALUE) IN_RANGE_P(VALUE, -2048, -1) #define CONST_OK_FOR_N(VALUE) IN_RANGE (VALUE, -2048, -1)
/* Zero */ /* Zero */
#define CONST_OK_FOR_O(VALUE) ((VALUE) == 0) #define CONST_OK_FOR_O(VALUE) ((VALUE) == 0)
/* 12-bit signed immediate that is negative. */ /* 12-bit signed immediate that is negative. */
#define CONST_OK_FOR_P(VALUE) IN_RANGE_P(VALUE, 1, 2047) #define CONST_OK_FOR_P(VALUE) IN_RANGE (VALUE, 1, 2047)
/* A C expression that defines the machine-dependent operand constraint letters /* A C expression that defines the machine-dependent operand constraint letters
(`I', `J', `K', .. 'P') that specify particular ranges of integer values. (`I', `J', `K', .. 'P') that specify particular ranges of integer values.
......
gcc/config/frv/frv.md
...@@ -4628,8 +4628,8 @@ ...@@ -4628,8 +4628,8 @@
(clobber (match_operand:CC_CCR 5 "icr_operand" "=v,v,v,v,v"))] (clobber (match_operand:CC_CCR 5 "icr_operand" "=v,v,v,v,v"))]
"(INTVAL (operands[3]) == 0 "(INTVAL (operands[3]) == 0
|| INTVAL (operands[4]) == 0 || INTVAL (operands[4]) == 0
|| (IN_RANGE_P (INTVAL (operands[3]), -2048, 2047) || (IN_RANGE (INTVAL (operands[3]), -2048, 2047)
&& IN_RANGE_P (INTVAL (operands[4]) - INTVAL (operands[3]), -2048, 2047)))" && IN_RANGE (INTVAL (operands[4]) - INTVAL (operands[3]), -2048, 2047)))"
"#" "#"
[(set_attr "length" "8,12,8,12,12") [(set_attr "length" "8,12,8,12,12")
(set_attr "type" "multi")]) (set_attr "type" "multi")])
...@@ -4645,8 +4645,8 @@ ...@@ -4645,8 +4645,8 @@
"TARGET_HARD_FLOAT "TARGET_HARD_FLOAT
&& (INTVAL (operands[3]) == 0 && (INTVAL (operands[3]) == 0
|| INTVAL (operands[4]) == 0 || INTVAL (operands[4]) == 0
|| (IN_RANGE_P (INTVAL (operands[3]), -2048, 2047) || (IN_RANGE (INTVAL (operands[3]), -2048, 2047)
&& IN_RANGE_P (INTVAL (operands[4]) - INTVAL (operands[3]), -2048, 2047)))" && IN_RANGE (INTVAL (operands[4]) - INTVAL (operands[3]), -2048, 2047)))"
"#" "#"
[(set_attr "length" "8,12,8,12,12") [(set_attr "length" "8,12,8,12,12")
(set_attr "type" "multi")]) (set_attr "type" "multi")])
...@@ -4713,8 +4713,8 @@ ...@@ -4713,8 +4713,8 @@
(clobber (match_operand:CC_CCR 5 "icr_operand" "=v,v,v,v,v"))] (clobber (match_operand:CC_CCR 5 "icr_operand" "=v,v,v,v,v"))]
"(INTVAL (operands[3]) == 0 "(INTVAL (operands[3]) == 0
|| INTVAL (operands[4]) == 0 || INTVAL (operands[4]) == 0
|| (IN_RANGE_P (INTVAL (operands[3]), -2048, 2047) || (IN_RANGE (INTVAL (operands[3]), -2048, 2047)
&& IN_RANGE_P (INTVAL (operands[4]) - INTVAL (operands[3]), -2048, 2047)))" && IN_RANGE (INTVAL (operands[4]) - INTVAL (operands[3]), -2048, 2047)))"
"#" "#"
[(set_attr "length" "8,12,8,12,12") [(set_attr "length" "8,12,8,12,12")
(set_attr "type" "multi")]) (set_attr "type" "multi")])
...@@ -4730,8 +4730,8 @@ ...@@ -4730,8 +4730,8 @@
"TARGET_HARD_FLOAT "TARGET_HARD_FLOAT
&& (INTVAL (operands[3]) == 0 && (INTVAL (operands[3]) == 0
|| INTVAL (operands[4]) == 0 || INTVAL (operands[4]) == 0
|| (IN_RANGE_P (INTVAL (operands[3]), -2048, 2047) || (IN_RANGE (INTVAL (operands[3]), -2048, 2047)
&& IN_RANGE_P (INTVAL (operands[4]) - INTVAL (operands[3]), -2048, 2047)))" && IN_RANGE (INTVAL (operands[4]) - INTVAL (operands[3]), -2048, 2047)))"
"#" "#"
[(set_attr "length" "8,12,8,12,12") [(set_attr "length" "8,12,8,12,12")
(set_attr "type" "multi")]) (set_attr "type" "multi")])
...@@ -4798,8 +4798,8 @@ ...@@ -4798,8 +4798,8 @@
(clobber (match_operand:CC_CCR 5 "icr_operand" "=v,v,v,v,v"))] (clobber (match_operand:CC_CCR 5 "icr_operand" "=v,v,v,v,v"))]
"(INTVAL (operands[3]) == 0 "(INTVAL (operands[3]) == 0
|| INTVAL (operands[4]) == 0 || INTVAL (operands[4]) == 0
|| (IN_RANGE_P (INTVAL (operands[3]), -2048, 2047) || (IN_RANGE (INTVAL (operands[3]), -2048, 2047)
&& IN_RANGE_P (INTVAL (operands[4]) - INTVAL (operands[3]), -2048, 2047)))" && IN_RANGE (INTVAL (operands[4]) - INTVAL (operands[3]), -2048, 2047)))"
"#" "#"
[(set_attr "length" "8,12,8,12,12") [(set_attr "length" "8,12,8,12,12")
(set_attr "type" "multi")]) (set_attr "type" "multi")])
...@@ -4815,8 +4815,8 @@ ...@@ -4815,8 +4815,8 @@
"TARGET_HARD_FLOAT "TARGET_HARD_FLOAT
&& (INTVAL (operands[3]) == 0 && (INTVAL (operands[3]) == 0
|| INTVAL (operands[4]) == 0 || INTVAL (operands[4]) == 0
|| (IN_RANGE_P (INTVAL (operands[3]), -2048, 2047) || (IN_RANGE (INTVAL (operands[3]), -2048, 2047)
&& IN_RANGE_P (INTVAL (operands[4]) - INTVAL (operands[3]), -2048, 2047)))" && IN_RANGE (INTVAL (operands[4]) - INTVAL (operands[3]), -2048, 2047)))"
"#" "#"
[(set_attr "length" "8,12,8,12,12") [(set_attr "length" "8,12,8,12,12")
(set_attr "type" "multi")]) (set_attr "type" "multi")])
...@@ -5564,7 +5564,7 @@ ...@@ -5564,7 +5564,7 @@
gcc_assert (GET_CODE (operands[2]) == CONST_INT); gcc_assert (GET_CODE (operands[2]) == CONST_INT);
/* If we can't generate an immediate instruction, promote to register. */ /* If we can't generate an immediate instruction, promote to register. */
if (! IN_RANGE_P (INTVAL (range), -2048, 2047)) if (! IN_RANGE (INTVAL (range), -2048, 2047))
range = force_reg (SImode, range); range = force_reg (SImode, range);
/* If low bound is 0, we don't have to subtract it. */ /* If low bound is 0, we don't have to subtract it. */
...@@ -5573,7 +5573,7 @@ ...@@ -5573,7 +5573,7 @@
else else
{ {
indx = gen_reg_rtx (SImode); indx = gen_reg_rtx (SImode);
if (IN_RANGE_P (INTVAL (low), -2047, 2048)) if (IN_RANGE (INTVAL (low), -2047, 2048))
emit_insn (gen_addsi3 (indx, operands[0], GEN_INT (- INTVAL (low)))); emit_insn (gen_addsi3 (indx, operands[0], GEN_INT (- INTVAL (low))));
else else
emit_insn (gen_subsi3 (indx, operands[0], force_reg (SImode, low))); emit_insn (gen_subsi3 (indx, operands[0], force_reg (SImode, low)));
......
gcc/config/frv/predicates.md
...@@ -110,7 +110,7 @@ ...@@ -110,7 +110,7 @@
(match_code "reg,subreg,const_int,const") (match_code "reg,subreg,const_int,const")
{ {
if (GET_CODE (op) == CONST_INT) if (GET_CODE (op) == CONST_INT)
return IN_RANGE_P (INTVAL (op), -2048, 2047); return IN_RANGE (INTVAL (op), -2048, 2047);
if (got12_operand (op, mode)) if (got12_operand (op, mode))
return true; return true;
...@@ -141,7 +141,7 @@ ...@@ -141,7 +141,7 @@
int regno; int regno;
if (GET_CODE (op) == CONST_INT) if (GET_CODE (op) == CONST_INT)
return IN_RANGE_P (INTVAL (op), -2048, 2047); return IN_RANGE (INTVAL (op), -2048, 2047);
if (GET_MODE (op) != mode && mode != VOIDmode) if (GET_MODE (op) != mode && mode != VOIDmode)
return FALSE; return FALSE;
...@@ -170,7 +170,7 @@ ...@@ -170,7 +170,7 @@
(match_code "reg,subreg,const_int") (match_code "reg,subreg,const_int")
{ {
if (GET_CODE (op) == CONST_INT) if (GET_CODE (op) == CONST_INT)
return IN_RANGE_P (INTVAL (op), -512, 511); return IN_RANGE (INTVAL (op), -512, 511);
if (GET_MODE (op) != mode && mode != VOIDmode) if (GET_MODE (op) != mode && mode != VOIDmode)
return FALSE; return FALSE;
...@@ -493,7 +493,7 @@ ...@@ -493,7 +493,7 @@
if (GET_CODE (op) != CONST_INT) if (GET_CODE (op) != CONST_INT)
return FALSE; return FALSE;
return IN_RANGE_P (INTVAL (op), -2048, 2047); return IN_RANGE (INTVAL (op), -2048, 2047);
}) })
;; Return 1 if operand is an integer constant that takes 2 ;; Return 1 if operand is an integer constant that takes 2
...@@ -535,7 +535,7 @@ ...@@ -535,7 +535,7 @@
return (flag_pic == 0) && (! SYMBOL_REF_SMALL_P (op)); return (flag_pic == 0) && (! SYMBOL_REF_SMALL_P (op));
case CONST_INT: case CONST_INT:
return ! IN_RANGE_P (INTVAL (op), -32768, 32767); return ! IN_RANGE (INTVAL (op), -32768, 32767);
case CONST_DOUBLE: case CONST_DOUBLE:
if (GET_MODE (op) == SFmode) if (GET_MODE (op) == SFmode)
...@@ -543,12 +543,12 @@ ...@@ -543,12 +543,12 @@
REAL_VALUE_FROM_CONST_DOUBLE (rv, op); REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
REAL_VALUE_TO_TARGET_SINGLE (rv, l); REAL_VALUE_TO_TARGET_SINGLE (rv, l);
value = l; value = l;
return ! IN_RANGE_P (value, -32768, 32767); return ! IN_RANGE (value, -32768, 32767);
} }
else if (GET_MODE (op) == VOIDmode) else if (GET_MODE (op) == VOIDmode)
{ {
value = CONST_DOUBLE_LOW (op); value = CONST_DOUBLE_LOW (op);
return ! IN_RANGE_P (value, -32768, 32767); return ! IN_RANGE (value, -32768, 32767);
} }
break; break;
} }
...@@ -1117,7 +1117,7 @@ ...@@ -1117,7 +1117,7 @@
if (GET_CODE (op) != CONST_INT) if (GET_CODE (op) != CONST_INT)
return FALSE; return FALSE;
return IN_RANGE_P (INTVAL (op), 0, 0xffff); return IN_RANGE (INTVAL (op), 0, 0xffff);
}) })
;; Returns 1 if OP is either a SYMBOL_REF or a constant. ;; Returns 1 if OP is either a SYMBOL_REF or a constant.
...@@ -1444,7 +1444,7 @@ ...@@ -1444,7 +1444,7 @@
(match_code "reg,subreg,const_int") (match_code "reg,subreg,const_int")
{ {
if (GET_CODE (op) == CONST_INT) if (GET_CODE (op) == CONST_INT)
return IN_RANGE_P (INTVAL (op), -32, 31); return IN_RANGE (INTVAL (op), -32, 31);
if (GET_MODE (op) != mode && mode != VOIDmode) if (GET_MODE (op) != mode && mode != VOIDmode)
return FALSE; return FALSE;
...@@ -1471,7 +1471,7 @@ ...@@ -1471,7 +1471,7 @@
if (GET_CODE (op) != CONST_INT) if (GET_CODE (op) != CONST_INT)
return FALSE; return FALSE;
return IN_RANGE_P (INTVAL (op), -32, 31); return IN_RANGE (INTVAL (op), -32, 31);
}) })
;; Return 1 if operand is a 5-bit signed immediate. ;; Return 1 if operand is a 5-bit signed immediate.
...@@ -1479,7 +1479,7 @@ ...@@ -1479,7 +1479,7 @@
(define_predicate "int5_operand" (define_predicate "int5_operand"
(match_code "const_int") (match_code "const_int")
{ {
return GET_CODE (op) == CONST_INT && IN_RANGE_P (INTVAL (op), -16, 15); return GET_CODE (op) == CONST_INT && IN_RANGE (INTVAL (op), -16, 15);
}) })
;; Return 1 if operand is a 5-bit unsigned immediate. ;; Return 1 if operand is a 5-bit unsigned immediate.
...@@ -1487,7 +1487,7 @@ ...@@ -1487,7 +1487,7 @@
(define_predicate "uint5_operand" (define_predicate "uint5_operand"
(match_code "const_int") (match_code "const_int")
{ {
return GET_CODE (op) == CONST_INT && IN_RANGE_P (INTVAL (op), 0, 31); return GET_CODE (op) == CONST_INT && IN_RANGE (INTVAL (op), 0, 31);
}) })
;; Return 1 if operand is a 4-bit unsigned immediate. ;; Return 1 if operand is a 4-bit unsigned immediate.
...@@ -1495,7 +1495,7 @@ ...@@ -1495,7 +1495,7 @@
(define_predicate "uint4_operand" (define_predicate "uint4_operand"
(match_code "const_int") (match_code "const_int")
{ {
return GET_CODE (op) == CONST_INT && IN_RANGE_P (INTVAL (op), 0, 15); return GET_CODE (op) == CONST_INT && IN_RANGE (INTVAL (op), 0, 15);
}) })
;; Return 1 if operand is a 1-bit unsigned immediate (0 or 1). ;; Return 1 if operand is a 1-bit unsigned immediate (0 or 1).
...@@ -1503,7 +1503,7 @@ ...@@ -1503,7 +1503,7 @@
(define_predicate "uint1_operand" (define_predicate "uint1_operand"
(match_code "const_int") (match_code "const_int")
{ {
return GET_CODE (op) == CONST_INT && IN_RANGE_P (INTVAL (op), 0, 1); return GET_CODE (op) == CONST_INT && IN_RANGE (INTVAL (op), 0, 1);
}) })
;; Return 1 if operand is a valid ACC register number. ;; Return 1 if operand is a valid ACC register number.
......
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