sh.c (sh_use_dfa_interface): Remove.

2004-07-19  Paolo Bonzini  <bonzini@gnu.org>

	* config/sh/sh.c (sh_use_dfa_interface): Remove.
	(TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE): Set to
	hook_int_void_1.
	* config/sh/sh.md: Extract pipeline descriptions
	into separate files.
	* config/sh/sh1.md: New file, extracted from sh.md.
	* config/sh/sh4.md: New file, extracted from sh.md.
	* config/sh/shmedia.md: New file, extracted from sh.md
	and rewritten using new-style pipeline description.

From-SVN: r84910

gcc/ChangeLog

+2004-07-12  Paolo Bonzini  <bonzini@gnu.org>
+
+	* config/sh/sh.c (sh_use_dfa_interface): Remove.
+	(TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE): Set to
+	hook_int_void_1.
+	* config/sh/sh.md: Extract pipeline descriptions
+	into separate files.
+	* config/sh/sh1.md: New file, extracted from sh.md.
+	* config/sh/sh4.md: New file, extracted from sh.md.
+	* config/sh/shmedia.md: New file, extracted from sh.md
+	and rewritten using new-style pipeline description.
+
 2004-07-18  Zack Weinberg  <zack@codesourcery.com>
 
 	* config/pa/pa.md: Delete the two remaining define_peephole
 	patterns.
 
-2004-07-10  Steven Bosscher  <stevenb@suse.de>
+2004-07-18  Steven Bosscher  <stevenb@suse.de>
 	    Joseph S. Myers  <jsm@polyomino.org.uk>
 
 	* c-common.c (c_common_truthvalue_conversion): Don't warn if

gcc/config/sh/sh.c

@@ -227,7 +227,6 @@ static tree sh_handle_renesas_attribute (tree *, tree, tree, int, bool *);
 static void sh_output_function_epilogue (FILE *, HOST_WIDE_INT);
 static void sh_insert_attributes (tree, tree *);
 static int sh_adjust_cost (rtx, rtx, rtx, int);
-static int sh_use_dfa_interface (void);
 static int sh_issue_rate (void);
 static int sh_dfa_new_cycle (FILE *, int, rtx, int, int, int *sort_p);
 static short find_set_regmode_weight (rtx, enum machine_mode);
@@ -323,8 +322,8 @@ static bool sh_pass_by_reference (CUMULATIVE_ARGS *, enum machine_mode,
 #define TARGET_SCHED_ADJUST_COST sh_adjust_cost
 
 #undef TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE 
-#define TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE \
-				sh_use_dfa_interface
+#define TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE hook_int_void_1
+
 #undef TARGET_SCHED_ISSUE_RATE
 #define TARGET_SCHED_ISSUE_RATE sh_issue_rate
 
@@ -8551,19 +8550,6 @@ sh_pr_n_sets (void)
   return REG_N_SETS (TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG);
 }
 
-/* This Function returns nonzero if the DFA based scheduler interface
-   is to be used.  At present this is only supported properly for the SH4.
-   For the SH1 the current DFA model is just the converted form of the old
-   pipeline model description.  */
-static int
-sh_use_dfa_interface (void)
-{
-  if (TARGET_SH1)
-    return 1;
-  else
-    return 0;
-}
-
 /* This function returns "2" to indicate dual issue for the SH4
    processor.  To be used by the DFA pipeline description.  */
 static int

gcc/config/sh/sh1.md

+;; DFA scheduling description for Renesas / SuperH SH.
+;; Copyright (C) 2004 Free Software Foundation, Inc.
+
+;; This file is part of GCC.
+
+;; GCC is free software; you can redistribute it and/or modify
+;; it under the terms of the GNU General Public License as published by
+;; the Free Software Foundation; either version 2, or (at your option)
+;; any later version.
+
+;; GCC is distributed in the hope that it will be useful,
+;; but WITHOUT ANY WARRANTY; without even the implied warranty of
+;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+;; GNU General Public License for more details.
+
+;; You should have received a copy of the GNU General Public License
+;; along with GCC; see the file COPYING.  If not, write to
+;; the Free Software Foundation, 59 Temple Place - Suite 330,
+;; Boston, MA 02111-1307, USA.
+
+;; Load and store instructions save a cycle if they are aligned on a
+;; four byte boundary.  Using a function unit for stores encourages
+;; gcc to separate load and store instructions by one instruction,
+;; which makes it more likely that the linker will be able to word
+;; align them when relaxing.
+
+;; SH-1 scheduling.  This is just a conversion of the old scheduling
+;; model, using define_function_unit.
+
+(define_automaton "sh1")
+(define_cpu_unit "sh1memory,sh1int,sh1mpy,sh1fp" "sh1")
+
+;; Loads have a latency of two.
+;; However, call insns can have a delay slot, so that we want one more
+;; insn to be scheduled between the load of the function address and the call.
+;; This is equivalent to a latency of three.
+;; ADJUST_COST can only properly handle reductions of the cost, so we
+;; use a latency of three here.
+;; We only do this for SImode loads of general registers, to make the work
+;; for ADJUST_COST easier.
+(define_insn_reservation "sh1_load_si" 3
+  (and (eq_attr "pipe_model" "sh1")
+       (eq_attr "type" "load_si,pcload_si"))
+  "sh1memory*2")
+
+(define_insn_reservation "sh1_load_store" 2
+  (and (eq_attr "pipe_model" "sh1")
+       (eq_attr "type" "load,pcload,pload,store,pstore"))
+  "sh1memory*2")
+
+(define_insn_reservation "sh1_arith3" 3
+  (and (eq_attr "pipe_model" "sh1")
+       (eq_attr "type" "arith3,arith3b"))
+  "sh1int*3")
+
+(define_insn_reservation "sh1_dyn_shift" 2
+  (and (eq_attr "pipe_model" "sh1")
+       (eq_attr "type" "dyn_shift"))
+  "sh1int*2")
+
+(define_insn_reservation "sh1_int" 1
+  (and (eq_attr "pipe_model" "sh1")
+       (eq_attr "type" "!arith3,arith3b,dyn_shift"))
+  "sh1int")
+
+;; ??? These are approximations.
+(define_insn_reservation "sh1_smpy" 2
+  (and (eq_attr "pipe_model" "sh1")
+       (eq_attr "type" "smpy"))
+  "sh1mpy*2")
+
+(define_insn_reservation "sh1_dmpy" 3
+  (and (eq_attr "pipe_model" "sh1")
+       (eq_attr "type" "dmpy"))
+  "sh1mpy*3")
+
+(define_insn_reservation "sh1_fp" 2
+  (and (eq_attr "pipe_model" "sh1")
+       (eq_attr "type" "fp,fmove"))
+  "sh1fp")
+
+(define_insn_reservation "sh1_fdiv" 13
+  (and (eq_attr "pipe_model" "sh1")
+       (eq_attr "type" "fdiv"))
+  "sh1fp*12")
+

gcc/config/sh/shmedia.md

+;; DFA scheduling description for SH-5 SHmedia instructions.
+;; Copyright (C) 2004 Free Software Foundation, Inc.
+
+;; This file is part of GCC.
+
+;; GCC is free software; you can redistribute it and/or modify
+;; it under the terms of the GNU General Public License as published by
+;; the Free Software Foundation; either version 2, or (at your option)
+;; any later version.
+
+;; GCC is distributed in the hope that it will be useful,
+;; but WITHOUT ANY WARRANTY; without even the implied warranty of
+;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+;; GNU General Public License for more details.
+
+;; You should have received a copy of the GNU General Public License
+;; along with GCC; see the file COPYING.  If not, write to
+;; the Free Software Foundation, 59 Temple Place - Suite 330,
+;; Boston, MA 02111-1307, USA.
+
+;; This is just a conversion of the old model using define_function_unit.
+
+;; When executing SHmedia code, the SH-5 is a fairly straightforward
+;; single-issue machine.  It has four pipelines, the branch unit (br),
+;; the integer and multimedia unit (imu), the load/store unit (lsu), and
+;; the floating point unit (fpu).
+
+(define_automaton "shmedia")
+
+(define_cpu_unit "sh5issue,sh5fds" "shmedia")
+
+;; Every instruction on SH-5 occupies the issue resource for at least one
+;; cycle.
+(define_insn_reservation "shmedia1" 1
+  (and (eq_attr "pipe_model" "sh5media")
+       (eq_attr "type" "!pt_media,ptabs_media,invalidate_line_media,dmpy_media,load_media,fload_media,fcmp_media,fmove_media,fparith_media,dfparith_media,fpconv_media,dfpconv_media,dfmul_media,store_media,fstore_media,mcmp_media,mac_media,d2mpy_media,atrans_media,ustore_media"))
+  "sh5issue")
+
+;; Specify the various types of instruction which have latency > 1
+(define_insn_reservation "shmedia2" 2
+  (and (eq_attr "pipe_model" "sh5media")
+       (eq_attr "type" "mcmp_media"))
+  "sh5issue")
+
+(define_insn_reservation "shmedia3" 3
+  (and (eq_attr "pipe_model" "sh5media")
+       (eq_attr "type" "dmpy_media,load_media,fcmp_media,mac_media"))
+  "sh5issue")
+;; but see sh_adjust_cost for mac_media exception.
+
+(define_insn_reservation "shmedia4" 4
+  (and (eq_attr "pipe_model" "sh5media")
+       (eq_attr "type" "fload_media,fmove_media"))
+  "sh5issue")
+
+(define_insn_reservation "shmedia_d2mpy" 4
+  (and (eq_attr "pipe_model" "sh5media")
+       (eq_attr "type" "d2mpy_media"))
+  "sh5issue*2")
+
+(define_insn_reservation "shmedia5" 5
+  (and (eq_attr "pipe_model" "sh5media")
+       (eq_attr "type" "pt_media,ptabs_media"))
+  "sh5issue")
+
+(define_insn_reservation "shmedia6" 6
+  (and (eq_attr "pipe_model" "sh5media")
+       (eq_attr "type" "fparith_media,dfparith_media,fpconv_media,dfpconv_media"))
+  "sh5issue")
+
+(define_insn_reservation "shmedia_invalidate" 7
+  (and (eq_attr "pipe_model" "sh5media")
+       (eq_attr "type" "invalidate_line_media"))
+  "sh5issue*7")
+
+(define_insn_reservation "shmedia_dfmul" 9
+  (and (eq_attr "pipe_model" "sh5media") (eq_attr "type" "dfmul_media"))
+  "sh5issue*4")
+
+(define_insn_reservation "shmedia_atrans" 10
+  (and (eq_attr "pipe_model" "sh5media") (eq_attr "type" "atrans_media"))
+  "sh5issue*5")
+
+;; Floating-point divide and square-root occupy an additional resource,
+;; which is not internally pipelined.  However, other instructions
+;; can continue to issue.
+(define_insn_reservation "shmedia_fdiv" 19
+  (and (eq_attr "pipe_model" "sh5media") (eq_attr "type" "fdiv_media"))
+  "sh5fds*19")
+
+(define_insn_reservation "shmedia_dfdiv" 35
+  (and (eq_attr "pipe_model" "sh5media") (eq_attr "type" "dfdiv_media"))
+  "sh5fds*35")