AVX-512. Avoid upper-bank registers when splitting vec_extract_lo instruction.

gcc/
	PR target/67849
	* config/i386/sse.md (define_split vec_select/V8FI): Restrict
	split for upper-bank registers when target does not support
	AVX512VL.
	(define_insn "vec_extract_lo_<mode><mask_name>"): Restrict
	split when target does not support AVX512VL.

From-SVN: r228525

gcc/ChangeLog

+2015-10-06  Alexander Fomin  <alexander.fomin@intel.com>
+
+	PR target/67849
+	* config/i386/sse.md (define_split vec_select/V8FI): Restrict
+	split for upper-bank registers when target does not support
+	AVX512VL.
+	(define_insn "vec_extract_lo_<mode><mask_name>"): Restrict
+	split when target does not support AVX512VL.
+
 2015-10-06  David Edelsohn  <dje.gcc@gmail.com>
 
 	PR c/65345
 	* config/rs6000/rs6000.c (rs6000_atomic_assign_expand_fenv):
 	Adjust to use create_tmp_var_raw instead of create_tmp_var.
-	
+
 2015-10-06  Nick Clifton  <nickc@redhat.com>
 
 	* config/rl78/rl78.c (rl78_rtx_costs): Improve cost estimates for
@@ -596,6 +605,7 @@
 	readability.
 
 2015-10-02  Kirill Yukhin  <kirill.yukhin@intel.com>
+
 	* config/i386/i386.c (processor_features): Add F_AVX512VBMI,
 	F_AVX512IFMA.
 	(isa_names_table): Handle F_AVX512VBMI and F_AVX512IFMA.

gcc/config/i386/sse.md

@@ -6926,7 +6926,8 @@
 	  (parallel [(const_int 0) (const_int 1)
             (const_int 2) (const_int 3)])))]
   "TARGET_AVX512F && !(MEM_P (operands[0]) && MEM_P (operands[1]))
-  && reload_completed"
+  && reload_completed
+  && (TARGET_AVX512VL || (REG_P (operands[0]) && !EXT_REX_SSE_REG_P (operands[1])))"
   [(const_int 0)]
 {
   rtx op1 = operands[1];
@@ -6964,7 +6965,7 @@
             (const_int 2) (const_int 3)])))]
   "TARGET_AVX512F && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
 {
-  if (<mask_applied>)
+  if (<mask_applied> || !TARGET_AVX512VL)
     return "vextract<shuffletype>64x4\t{$0x0, %1, %0<mask_operand2>|%0<mask_operand2>, %1, 0x0}";
   else
     return "#";