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Commit 2d2a50c3 by Chris Demetriou Committed by Chris Demetriou
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config.gcc (mipsisa32r2-*-elf*, [...]): New targets, to support MIPS32 Release 2… 

config.gcc (mipsisa32r2-*-elf*, [...]): New targets, to support MIPS32 Release 2 (MIPS32R2) configurations.

2003-01-08  Chris Demetriou  <cgd@broadcom.com>

	* config.gcc (mipsisa32r2-*-elf*, mipsisa32r2el-*-elf*): New
	targets, to support MIPS32 Release 2 (MIPS32R2) configurations.
	* config/mips/mips.h (enum processor_type): Rename
	PROCESSOR_R4KC to PROCESSOR_4KC, PROCESSOR_R5KC to
	PROCESSOR_5KC, and PROCESSOR_R20KC to PROCESSOR_20KC.
	Add PROCESSOR_M4K.
	(TARGET_MIPS4KC, TARGET_MIPS5KC): Update for the renaming.
	(ISA_MIPS32R2): New define.
	(GENERATE_MULT3_SI, ISA_HAS_CONDMOVE, ISA_HAS_8CC)
	(ISA_HAS_MADD_MSUB, ISA_HAS_CLZ_CLO)
	(ISA_HAS_PREFETCH): Add support for MIPS32R2.
	(MIPS_ISA_DEFAULT): Likewise.  Also, fix indentation.
	(TARGET_CPU_CPP_BUILTINS): Add support for MIPS32R2.  Add new
	predefine __mips_isa_rev for MIPS32, MIPS32R2, and MIPS64.
	(ISA_HAS_ROTR_SI): Add support for MIPS32R2, and avoid if
	compiling MIPS16 code.
	(ISA_HAS_ROTR_DI): Do not use if compiling MIPS16 code, and fix
	comment.
	(ISA_HAS_SEB_SEH): New define.
	(ASM_SPEC, LINK_SPEC): Pass -mips32r2 to assembler and linker.
	* config/mips/mips.c (mips_cpu_info_table): Adjust for enum
	processor_type value renaming.  Add support for MIPS32R2.
	Clean up comments, and move "sb1" entry with other MIPS64 CPU
	entries.
	(override_options): Reimplement -mipsN option handling so that
	it will work correctly for -mips32r2.  Avoid branch-likely
	instructions on MIPS32R2.
	* config/mips/mips.md (mulsi3_mult3): Add support for MIPS32R2.
	(extendhisi2): Use extendhisi2_hw if ISA_HAS_SEB_SEH.
	(extendqisi2): Use extendqisi2_hw if ISA_HAS_SEB_SEH.
	(extendhisi2_hw, extendqisi2_hw): New.
	* config/mips/netbsd.h (TARGET_CPU_CPP_BUILTINS): Add support
	for MIPS32R2.  Add new predefine __mips_isa_rev for MIPS32,
	MIPS32R2, and MIPS64.
	(LINK_SPEC): Pass -mips32r2 to linker.
	* config/mips/t-isa3264: Built -mips32r2 multilibs.
	* doc/invoke.texi (MIPS Options): Add -mips32r2, add support
	for mips32r2 in the -march description.  Alphabetically sort
	CPU names in the -march description.  Add long-missed -mips32
	and -mips64 to MIPS option summary.

	* config.gcc: Update copyright years to include 2003.
	* config/mips/mips.c: Likewise.
	* config/mips/mips.h: Likewise.
	* config/mips/mips.md: Likewise.
	* config/mips/netbsd.h: Likewise.

From-SVN: r61053
parent 7ec3af37
Showing with 199 additions and 60 deletions
gcc/ChangeLog
2003-01-08 Chris Demetriou <cgd@broadcom.com>
* config.gcc (mipsisa32r2-*-elf*, mipsisa32r2el-*-elf*): New
targets, to support MIPS32 Release 2 (MIPS32R2) configurations.
* config/mips/mips.h (enum processor_type): Rename
PROCESSOR_R4KC to PROCESSOR_4KC, PROCESSOR_R5KC to
PROCESSOR_5KC, and PROCESSOR_R20KC to PROCESSOR_20KC.
Add PROCESSOR_M4K.
(TARGET_MIPS4KC, TARGET_MIPS5KC): Update for the renaming.
(ISA_MIPS32R2): New define.
(GENERATE_MULT3_SI, ISA_HAS_CONDMOVE, ISA_HAS_8CC)
(ISA_HAS_MADD_MSUB, ISA_HAS_CLZ_CLO)
(ISA_HAS_PREFETCH): Add support for MIPS32R2.
(MIPS_ISA_DEFAULT): Likewise. Also, fix indentation.
(TARGET_CPU_CPP_BUILTINS): Add support for MIPS32R2. Add new
predefine __mips_isa_rev for MIPS32, MIPS32R2, and MIPS64.
(ISA_HAS_ROTR_SI): Add support for MIPS32R2, and avoid if
compiling MIPS16 code.
(ISA_HAS_ROTR_DI): Do not use if compiling MIPS16 code, and fix
comment.
(ISA_HAS_SEB_SEH): New define.
(ASM_SPEC, LINK_SPEC): Pass -mips32r2 to assembler and linker.
* config/mips/mips.c (mips_cpu_info_table): Adjust for enum
processor_type value renaming. Add support for MIPS32R2.
Clean up comments, and move "sb1" entry with other MIPS64 CPU
entries.
(override_options): Reimplement -mipsN option handling so that
it will work correctly for -mips32r2. Avoid branch-likely
instructions on MIPS32R2.
* config/mips/mips.md (mulsi3_mult3): Add support for MIPS32R2.
(extendhisi2): Use extendhisi2_hw if ISA_HAS_SEB_SEH.
(extendqisi2): Use extendqisi2_hw if ISA_HAS_SEB_SEH.
(extendhisi2_hw, extendqisi2_hw): New.
* config/mips/netbsd.h (TARGET_CPU_CPP_BUILTINS): Add support
for MIPS32R2. Add new predefine __mips_isa_rev for MIPS32,
MIPS32R2, and MIPS64.
(LINK_SPEC): Pass -mips32r2 to linker.
* config/mips/t-isa3264: Built -mips32r2 multilibs.
* doc/invoke.texi (MIPS Options): Add -mips32r2, add support
for mips32r2 in the -march description. Alphabetically sort
CPU names in the -march description. Add long-missed -mips32
and -mips64 to MIPS option summary.
* config.gcc: Update copyright years to include 2003.
* config/mips/mips.c: Likewise.
* config/mips/mips.h: Likewise.
* config/mips/mips.md: Likewise.
* config/mips/netbsd.h: Likewise.
* doc/invoke.texi: Likewise.
2003-01-08 Andreas Schwab <schwab@suse.de> 2003-01-08 Andreas Schwab <schwab@suse.de>
* aclocal.m4 (gcc_AC_INITFINI_ARRAY): Fix spelling of cache * aclocal.m4 (gcc_AC_INITFINI_ARRAY): Fix spelling of cache
......
gcc/config.gcc
# GCC build-, host- and target-specific configuration file. # GCC build-, host- and target-specific configuration file.
# Copyright (C) 1997, 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. # Copyright (C) 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
#This file is part of GCC. #This file is part of GCC.
...@@ -1830,6 +1830,11 @@ mipsisa32-*-elf* | mipsisa32el-*-elf*) ...@@ -1830,6 +1830,11 @@ mipsisa32-*-elf* | mipsisa32el-*-elf*)
tmake_file=mips/t-isa3264 tmake_file=mips/t-isa3264
tm_defines="MIPS_ISA_DEFAULT=32 MIPS_ABI_DEFAULT=ABI_EABI" tm_defines="MIPS_ISA_DEFAULT=32 MIPS_ABI_DEFAULT=ABI_EABI"
;; ;;
mipsisa32r2-*-elf* | mipsisa32r2el-*-elf*)
tm_file="${tm_file} mips/elf.h"
tmake_file=mips/t-isa3264
tm_defines="MIPS_ISA_DEFAULT=33 MIPS_ABI_DEFAULT=ABI_EABI"
;;
mipsisa64-*-elf* | mipsisa64el-*-elf*) mipsisa64-*-elf* | mipsisa64el-*-elf*)
tm_file="${tm_file} mips/elf.h" tm_file="${tm_file} mips/elf.h"
tmake_file=mips/t-isa3264 tmake_file=mips/t-isa3264
......
gcc/config/mips/mips.c
/* Subroutines for insn-output.c for MIPS /* Subroutines for insn-output.c for MIPS
Copyright (C) 1989, 1990, 1991, 1993, 1994, 1995, 1996, 1997, 1998, Copyright (C) 1989, 1990, 1991, 1993, 1994, 1995, 1996, 1997, 1998,
1999, 2000, 2001, 2002 Free Software Foundation, Inc. 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
Contributed by A. Lichnewsky, lich@inria.inria.fr. Contributed by A. Lichnewsky, lich@inria.inria.fr.
Changes by Michael Meissner, meissner@osf.org. Changes by Michael Meissner, meissner@osf.org.
64 bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and 64 bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and
...@@ -583,8 +583,9 @@ const struct mips_cpu_info mips_cpu_info_table[] = { ...@@ -583,8 +583,9 @@ const struct mips_cpu_info mips_cpu_info_table[] = {
{ "mips2", PROCESSOR_R6000, 2 }, { "mips2", PROCESSOR_R6000, 2 },
{ "mips3", PROCESSOR_R4000, 3 }, { "mips3", PROCESSOR_R4000, 3 },
{ "mips4", PROCESSOR_R8000, 4 }, { "mips4", PROCESSOR_R8000, 4 },
{ "mips32", PROCESSOR_R4KC, 32 }, { "mips32", PROCESSOR_4KC, 32 },
{ "mips64", PROCESSOR_R5KC, 64 }, { "mips32r2", PROCESSOR_M4K, 33 },
{ "mips64", PROCESSOR_5KC, 64 },
/* MIPS I */ /* MIPS I */
{ "r3000", PROCESSOR_R3000, 1 }, { "r3000", PROCESSOR_R3000, 1 },
...@@ -611,18 +612,18 @@ const struct mips_cpu_info mips_cpu_info_table[] = { ...@@ -611,18 +612,18 @@ const struct mips_cpu_info mips_cpu_info_table[] = {
{ "vr5400", PROCESSOR_R5400, 4 }, { "vr5400", PROCESSOR_R5400, 4 },
{ "vr5500", PROCESSOR_R5500, 4 }, { "vr5500", PROCESSOR_R5500, 4 },
/* MIPS32 */
{ "4kc", PROCESSOR_4KC, 32 },
{ "4kp", PROCESSOR_4KC, 32 }, /* = 4kc */
/* MIPS 32 */ /* MIPS32 Release 2 */
{ "4kc", PROCESSOR_R4KC, 32 }, { "m4k", PROCESSOR_M4K, 33 },
{ "4kp", PROCESSOR_R4KC, 32 }, /* = 4kc */
/* MIPS 64 */ /* MIPS64 */
{ "5kc", PROCESSOR_R5KC, 64 }, { "5kc", PROCESSOR_5KC, 64 },
{ "20kc", PROCESSOR_R20KC, 64 }, { "20kc", PROCESSOR_20KC, 64 },
{ "sr71000", PROCESSOR_SR71000, 64 },
/* Broadcom SB-1 CPU core */
{ "sb1", PROCESSOR_SB1, 64 }, { "sb1", PROCESSOR_SB1, 64 },
{ "sr71000", PROCESSOR_SR71000, 64 },
/* End marker */ /* End marker */
{ 0, 0, 0 } { 0, 0, 0 }
...@@ -5127,28 +5128,31 @@ override_options () ...@@ -5127,28 +5128,31 @@ override_options ()
if (mips_isa_string != 0) if (mips_isa_string != 0)
{ {
/* Handle -mipsN. */ /* Handle -mipsN. */
int level = atoi (mips_isa_string);
if (level == 16) if (strcmp (mips_isa_string, "16") == 0)
{ {
/* -mips16 specifies an ASE rather than a processor, so don't /* -mips16 specifies an ASE rather than a processor, so don't
change mips_arch here. -mno-mips16 overrides -mips16. */ change mips_arch here. -mno-mips16 overrides -mips16. */
if (mips_no_mips16_string == NULL) if (mips_no_mips16_string == NULL)
target_flags |= MASK_MIPS16; target_flags |= MASK_MIPS16;
} }
else if (mips_arch_info != 0) else
{ {
char *whole_isa_str = concat ("mips", mips_isa_string, NULL);
const struct mips_cpu_info *isa_info;
isa_info = mips_parse_cpu ("-mips option", whole_isa_str);
free (whole_isa_str);
/* -march takes precedence over -mipsN, since it is more descriptive. /* -march takes precedence over -mipsN, since it is more descriptive.
There's no harm in specifying both as long as the ISA levels There's no harm in specifying both as long as the ISA levels
are the same. */ are the same. */
if (mips_isa != level) if (mips_arch_info != 0 && mips_isa != isa_info->isa)
error ("-mips%d conflicts with the other architecture options, which specify a MIPS%d processor", error ("-mips%s conflicts with the other architecture options, which specify a MIPS%d processor",
level, mips_isa); mips_isa_string, mips_isa);
}
else /* Set architecture based on the given option. */
{ mips_set_architecture (isa_info);
mips_set_architecture (mips_cpu_info_from_isa (level));
if (mips_arch_info == 0)
error ("bad value (%s) for -mips switch", mips_isa_string);
} }
} }
...@@ -5265,7 +5269,7 @@ override_options () ...@@ -5265,7 +5269,7 @@ override_options ()
of the [MIPS32 and MIPS64] architecture." Therefore, we do not of the [MIPS32 and MIPS64] architecture." Therefore, we do not
issue those instructions unless instructed to do so by issue those instructions unless instructed to do so by
-mbranch-likely. */ -mbranch-likely. */
if (ISA_HAS_BRANCHLIKELY && !(ISA_MIPS32 || ISA_MIPS64)) if (ISA_HAS_BRANCHLIKELY && !(ISA_MIPS32 || ISA_MIPS32R2 || ISA_MIPS64))
target_flags |= MASK_BRANCHLIKELY; target_flags |= MASK_BRANCHLIKELY;
else else
target_flags &= ~MASK_BRANCHLIKELY; target_flags &= ~MASK_BRANCHLIKELY;
......
gcc/config/mips/mips.h
/* Definitions of target machine for GNU compiler. MIPS version. /* Definitions of target machine for GNU compiler. MIPS version.
Copyright (C) 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998 Copyright (C) 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998
1999, 2000, 2001, 2002 Free Software Foundation, Inc. 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
Contributed by A. Lichnewsky (lich@inria.inria.fr). Contributed by A. Lichnewsky (lich@inria.inria.fr).
Changed by Michael Meissner (meissner@osf.org). Changed by Michael Meissner (meissner@osf.org).
64 bit r4000 support by Ian Lance Taylor (ian@cygnus.com) and 64 bit r4000 support by Ian Lance Taylor (ian@cygnus.com) and
...@@ -72,9 +72,10 @@ enum processor_type { ...@@ -72,9 +72,10 @@ enum processor_type {
PROCESSOR_R5400, PROCESSOR_R5400,
PROCESSOR_R5500, PROCESSOR_R5500,
PROCESSOR_R8000, PROCESSOR_R8000,
PROCESSOR_R4KC, PROCESSOR_4KC,
PROCESSOR_R5KC, PROCESSOR_5KC,
PROCESSOR_R20KC, PROCESSOR_20KC,
PROCESSOR_M4K,
PROCESSOR_SR71000, PROCESSOR_SR71000,
PROCESSOR_SB1 PROCESSOR_SB1
}; };
...@@ -351,6 +352,7 @@ extern void sbss_section PARAMS ((void)); ...@@ -351,6 +352,7 @@ extern void sbss_section PARAMS ((void));
#define ISA_MIPS3 (mips_isa == 3) #define ISA_MIPS3 (mips_isa == 3)
#define ISA_MIPS4 (mips_isa == 4) #define ISA_MIPS4 (mips_isa == 4)
#define ISA_MIPS32 (mips_isa == 32) #define ISA_MIPS32 (mips_isa == 32)
#define ISA_MIPS32R2 (mips_isa == 33)
#define ISA_MIPS64 (mips_isa == 64) #define ISA_MIPS64 (mips_isa == 64)
/* Architecture target defines. */ /* Architecture target defines. */
...@@ -359,8 +361,8 @@ extern void sbss_section PARAMS ((void)); ...@@ -359,8 +361,8 @@ extern void sbss_section PARAMS ((void));
#define TARGET_MIPS4100 (mips_arch == PROCESSOR_R4100) #define TARGET_MIPS4100 (mips_arch == PROCESSOR_R4100)
#define TARGET_MIPS4120 (mips_arch == PROCESSOR_R4120) #define TARGET_MIPS4120 (mips_arch == PROCESSOR_R4120)
#define TARGET_MIPS4300 (mips_arch == PROCESSOR_R4300) #define TARGET_MIPS4300 (mips_arch == PROCESSOR_R4300)
#define TARGET_MIPS4KC (mips_arch == PROCESSOR_R4KC) #define TARGET_MIPS4KC (mips_arch == PROCESSOR_4KC)
#define TARGET_MIPS5KC (mips_arch == PROCESSOR_R5KC) #define TARGET_MIPS5KC (mips_arch == PROCESSOR_5KC)
#define TARGET_MIPS5400 (mips_arch == PROCESSOR_R5400) #define TARGET_MIPS5400 (mips_arch == PROCESSOR_R5400)
#define TARGET_MIPS5500 (mips_arch == PROCESSOR_R5500) #define TARGET_MIPS5500 (mips_arch == PROCESSOR_R5500)
#define TARGET_SB1 (mips_arch == PROCESSOR_SB1) #define TARGET_SB1 (mips_arch == PROCESSOR_SB1)
...@@ -456,11 +458,19 @@ extern void sbss_section PARAMS ((void)); ...@@ -456,11 +458,19 @@ extern void sbss_section PARAMS ((void));
else if (ISA_MIPS32) \ else if (ISA_MIPS32) \
{ \ { \
builtin_define ("__mips=32"); \ builtin_define ("__mips=32"); \
builtin_define ("__mips_isa_rev=1"); \
builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32"); \
} \
else if (ISA_MIPS32R2) \
{ \
builtin_define ("__mips=32"); \
builtin_define ("__mips_isa_rev=2"); \
builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32"); \ builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32"); \
} \ } \
else if (ISA_MIPS64) \ else if (ISA_MIPS64) \
{ \ { \
builtin_define ("__mips=64"); \ builtin_define ("__mips=64"); \
builtin_define ("__mips_isa_rev=1"); \
builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS64"); \ builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS64"); \
} \ } \
\ \
...@@ -707,13 +717,17 @@ extern void sbss_section PARAMS ((void)); ...@@ -707,13 +717,17 @@ extern void sbss_section PARAMS ((void));
# if MIPS_ISA_DEFAULT == 32 # if MIPS_ISA_DEFAULT == 32
# define MULTILIB_ISA_DEFAULT "mips32" # define MULTILIB_ISA_DEFAULT "mips32"
# else # else
# if MIPS_ISA_DEFAULT == 64 # if MIPS_ISA_DEFAULT == 33
# define MULTILIB_ISA_DEFAULT "mips64" # define MULTILIB_ISA_DEFAULT "mips32r2"
# else # else
# define MULTILIB_ISA_DEFAULT "mips1" # if MIPS_ISA_DEFAULT == 64
# endif # define MULTILIB_ISA_DEFAULT "mips64"
# else
# define MULTILIB_ISA_DEFAULT "mips1"
# endif
# endif
# endif
# endif # endif
# endif
# endif # endif
# endif # endif
# endif # endif
...@@ -770,6 +784,7 @@ extern void sbss_section PARAMS ((void)); ...@@ -770,6 +784,7 @@ extern void sbss_section PARAMS ((void));
|| TARGET_MIPS5400 \ || TARGET_MIPS5400 \
|| TARGET_MIPS5500 \ || TARGET_MIPS5500 \
|| ISA_MIPS32 \ || ISA_MIPS32 \
|| ISA_MIPS32R2 \
|| ISA_MIPS64) \ || ISA_MIPS64) \
&& !TARGET_MIPS16) && !TARGET_MIPS16)
...@@ -806,6 +821,7 @@ extern void sbss_section PARAMS ((void)); ...@@ -806,6 +821,7 @@ extern void sbss_section PARAMS ((void));
/* ISA has the conditional move instructions introduced in mips4. */ /* ISA has the conditional move instructions introduced in mips4. */
#define ISA_HAS_CONDMOVE ((ISA_MIPS4 \ #define ISA_HAS_CONDMOVE ((ISA_MIPS4 \
|| ISA_MIPS32 \ || ISA_MIPS32 \
|| ISA_MIPS32R2 \
|| ISA_MIPS64) \ || ISA_MIPS64) \
&& !TARGET_MIPS5500 \ && !TARGET_MIPS5500 \
&& !TARGET_MIPS16) && !TARGET_MIPS16)
...@@ -817,6 +833,7 @@ extern void sbss_section PARAMS ((void)); ...@@ -817,6 +833,7 @@ extern void sbss_section PARAMS ((void));
branch on CC, and move (both FP and non-FP) on CC. */ branch on CC, and move (both FP and non-FP) on CC. */
#define ISA_HAS_8CC (ISA_MIPS4 \ #define ISA_HAS_8CC (ISA_MIPS4 \
|| ISA_MIPS32 \ || ISA_MIPS32 \
|| ISA_MIPS32R2 \
|| ISA_MIPS64) || ISA_MIPS64)
/* This is a catch all for the other new mips4 instructions: indexed load and /* This is a catch all for the other new mips4 instructions: indexed load and
...@@ -832,6 +849,7 @@ extern void sbss_section PARAMS ((void)); ...@@ -832,6 +849,7 @@ extern void sbss_section PARAMS ((void));
/* ISA has integer multiply-accumulate instructions, madd and msub. */ /* ISA has integer multiply-accumulate instructions, madd and msub. */
#define ISA_HAS_MADD_MSUB ((ISA_MIPS32 \ #define ISA_HAS_MADD_MSUB ((ISA_MIPS32 \
|| ISA_MIPS32R2 \
|| ISA_MIPS64 \ || ISA_MIPS64 \
) && !TARGET_MIPS16) ) && !TARGET_MIPS16)
...@@ -843,6 +861,7 @@ extern void sbss_section PARAMS ((void)); ...@@ -843,6 +861,7 @@ extern void sbss_section PARAMS ((void));
/* ISA has count leading zeroes/ones instruction (not implemented). */ /* ISA has count leading zeroes/ones instruction (not implemented). */
#define ISA_HAS_CLZ_CLO ((ISA_MIPS32 \ #define ISA_HAS_CLZ_CLO ((ISA_MIPS32 \
|| ISA_MIPS32R2 \
|| ISA_MIPS64 \ || ISA_MIPS64 \
) && !TARGET_MIPS16) ) && !TARGET_MIPS16)
...@@ -879,22 +898,25 @@ extern void sbss_section PARAMS ((void)); ...@@ -879,22 +898,25 @@ extern void sbss_section PARAMS ((void));
) )
/* ISA has 32-bit rotate right instruction. */ /* ISA has 32-bit rotate right instruction. */
#define ISA_HAS_ROTR_SI (TARGET_MIPS5400 \ #define ISA_HAS_ROTR_SI (!TARGET_MIPS16 \
|| TARGET_MIPS5500 \ && (ISA_MIPS32R2 \
|| TARGET_SR71K \ || TARGET_MIPS5400 \
) || TARGET_MIPS5500 \
|| TARGET_SR71K \
))
/* ISA has 32-bit rotate right instruction. */ /* ISA has 64-bit rotate right instruction. */
#define ISA_HAS_ROTR_DI (TARGET_64BIT \ #define ISA_HAS_ROTR_DI (TARGET_64BIT \
&& !TARGET_MIPS16 \
&& (TARGET_MIPS5400 \ && (TARGET_MIPS5400 \
|| TARGET_MIPS5500 \ || TARGET_MIPS5500 \
|| TARGET_SR71K \ || TARGET_SR71K \
)) ))
/* ISA has data prefetch instruction. */ /* ISA has data prefetch instruction. */
#define ISA_HAS_PREFETCH ((ISA_MIPS4 \ #define ISA_HAS_PREFETCH ((ISA_MIPS4 \
|| ISA_MIPS32 \ || ISA_MIPS32 \
|| ISA_MIPS32R2 \
|| ISA_MIPS64) \ || ISA_MIPS64) \
&& !TARGET_MIPS16) && !TARGET_MIPS16)
...@@ -903,6 +925,11 @@ extern void sbss_section PARAMS ((void)); ...@@ -903,6 +925,11 @@ extern void sbss_section PARAMS ((void));
also requires TARGET_DOUBLE_FLOAT. */ also requires TARGET_DOUBLE_FLOAT. */
#define ISA_HAS_TRUNC_W (!ISA_MIPS1) #define ISA_HAS_TRUNC_W (!ISA_MIPS1)
/* ISA includes the MIPS32r2 seb and seh instructions. */
#define ISA_HAS_SEB_SEH (!TARGET_MIPS16 \
&& (ISA_MIPS32R2 \
))
/* CC1_SPEC causes -mips3 and -mips4 to set -mfp64 and -mgp64; -mips1 or /* CC1_SPEC causes -mips3 and -mips4 to set -mfp64 and -mgp64; -mips1 or
-mips2 sets -mfp32 and -mgp32. This can be overridden by an explicit -mips2 sets -mfp32 and -mgp32. This can be overridden by an explicit
-mfp32, -mfp64, -mgp32 or -mgp64. -mfp64 sets MASK_FLOAT64 in -mfp32, -mfp64, -mgp32 or -mgp64. -mfp64 sets MASK_FLOAT64 in
...@@ -1066,7 +1093,8 @@ extern int mips_abi; ...@@ -1066,7 +1093,8 @@ extern int mips_abi;
#undef ASM_SPEC #undef ASM_SPEC
#define ASM_SPEC "\ #define ASM_SPEC "\
%{G*} %(endian_spec) %{mips1} %{mips2} %{mips3} %{mips4} %{mips32} %{mips64}\ %{G*} %(endian_spec) %{mips1} %{mips2} %{mips3} %{mips4} \
%{mips32} %{mips32r2} %{mips64} \
%{mips16:%{!mno-mips16:-mips16}} %{mno-mips16:-no-mips16} \ %{mips16:%{!mno-mips16:-mips16}} %{mno-mips16:-no-mips16} \
%(subtarget_asm_optimizing_spec) \ %(subtarget_asm_optimizing_spec) \
%(subtarget_asm_debugging_spec) \ %(subtarget_asm_debugging_spec) \
...@@ -1123,7 +1151,7 @@ extern int mips_abi; ...@@ -1123,7 +1151,7 @@ extern int mips_abi;
#ifndef LINK_SPEC #ifndef LINK_SPEC
#define LINK_SPEC "\ #define LINK_SPEC "\
%(endian_spec) \ %(endian_spec) \
%{G*} %{mips1} %{mips2} %{mips3} %{mips4} %{mips32} %{mips64} \ %{G*} %{mips1} %{mips2} %{mips3} %{mips4} %{mips32} %{mips32r2} %{mips64} \
%{bestGnum} %{shared} %{non_shared}" %{bestGnum} %{shared} %{non_shared}"
#endif /* LINK_SPEC defined */ #endif /* LINK_SPEC defined */
......
gcc/config/mips/mips.md
;; Mips.md Machine Description for MIPS based processors ;; Mips.md Machine Description for MIPS based processors
;; Copyright (C) 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, ;; Copyright (C) 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
;; 1999, 2000, 2001, 2002 Free Software Foundation, Inc. ;; 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
;; Contributed by A. Lichnewsky, lich@inria.inria.fr ;; Contributed by A. Lichnewsky, lich@inria.inria.fr
;; Changes by Michael Meissner, meissner@osf.org ;; Changes by Michael Meissner, meissner@osf.org
;; 64 bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and ;; 64 bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and
...@@ -1808,6 +1808,7 @@ ...@@ -1808,6 +1808,7 @@
|| TARGET_MIPS5400 || TARGET_MIPS5400
|| TARGET_MIPS5500 || TARGET_MIPS5500
|| ISA_MIPS32 || ISA_MIPS32
|| ISA_MIPS32R2
|| ISA_MIPS64) || ISA_MIPS64)
return \"mul\\t%0,%1,%2\"; return \"mul\\t%0,%1,%2\";
return \"mult\\t%0,%1,%2\"; return \"mult\\t%0,%1,%2\";
...@@ -4379,6 +4380,13 @@ move\\t%0,%z4\\n\\ ...@@ -4379,6 +4380,13 @@ move\\t%0,%z4\\n\\
"" ""
" "
{ {
if (ISA_HAS_SEB_SEH)
{
emit_insn (gen_extendhisi2_hw (operands[0],
force_reg (HImode, operands[1])));
DONE;
}
if (optimize && GET_CODE (operands[1]) == MEM) if (optimize && GET_CODE (operands[1]) == MEM)
operands[1] = force_not_mem (operands[1]); operands[1] = force_not_mem (operands[1]);
...@@ -4394,6 +4402,14 @@ move\\t%0,%z4\\n\\ ...@@ -4394,6 +4402,14 @@ move\\t%0,%z4\\n\\
} }
}") }")
(define_insn "extendhisi2_hw"
[(set (match_operand:SI 0 "register_operand" "=r")
(sign_extend:SI (match_operand:HI 1 "register_operand" "r")))]
"ISA_HAS_SEB_SEH"
"seh\\t%0,%1"
[(set_attr "type" "arith")
(set_attr "mode" "SI")])
(define_insn "extendhisi2_internal" (define_insn "extendhisi2_internal"
[(set (match_operand:SI 0 "register_operand" "=d,d") [(set (match_operand:SI 0 "register_operand" "=d,d")
(sign_extend:SI (match_operand:HI 1 "memory_operand" "R,m")))] (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,m")))]
...@@ -4441,6 +4457,12 @@ move\\t%0,%z4\\n\\ ...@@ -4441,6 +4457,12 @@ move\\t%0,%z4\\n\\
"" ""
" "
{ {
if (ISA_HAS_SEB_SEH)
{
emit_insn (gen_extendqisi2_hw (operands[0],
force_reg (QImode, operands[1])));
DONE;
}
if (optimize && GET_CODE (operands[1]) == MEM) if (optimize && GET_CODE (operands[1]) == MEM)
operands[1] = force_not_mem (operands[1]); operands[1] = force_not_mem (operands[1]);
...@@ -4456,6 +4478,14 @@ move\\t%0,%z4\\n\\ ...@@ -4456,6 +4478,14 @@ move\\t%0,%z4\\n\\
} }
}") }")
(define_insn "extendqisi2_hw"
[(set (match_operand:SI 0 "register_operand" "=r")
(sign_extend:SI (match_operand:QI 1 "register_operand" "r")))]
"ISA_HAS_SEB_SEH"
"seb\\t%0,%1"
[(set_attr "type" "arith")
(set_attr "mode" "SI")])
(define_insn "extendqisi2_insn" (define_insn "extendqisi2_insn"
[(set (match_operand:SI 0 "register_operand" "=d,d") [(set (match_operand:SI 0 "register_operand" "=d,d")
(sign_extend:SI (match_operand:QI 1 "memory_operand" "R,m")))] (sign_extend:SI (match_operand:QI 1 "memory_operand" "R,m")))]
......
gcc/config/mips/netbsd.h
/* Definitions of target machine for GNU compiler, for MIPS NetBSD systems. /* Definitions of target machine for GNU compiler, for MIPS NetBSD systems.
Copyright (C) 1993, 1995, 1996, 1997, 1999, 2000, 2001, 2002 Copyright (C) 1993, 1995, 1996, 1997, 1999, 2000, 2001, 2002, 2003
Free Software Foundation, Inc. Free Software Foundation, Inc.
This file is part of GNU CC. This file is part of GNU CC.
...@@ -93,9 +93,20 @@ Boston, MA 02111-1307, USA. */ ...@@ -93,9 +93,20 @@ Boston, MA 02111-1307, USA. */
else if (ISA_MIPS4) \ else if (ISA_MIPS4) \
builtin_define ("__mips=4"); \ builtin_define ("__mips=4"); \
else if (ISA_MIPS32) \ else if (ISA_MIPS32) \
builtin_define ("__mips=32"); \ { \
builtin_define ("__mips=32"); \
builtin_define ("__mips_isa_rev=1"); \
} \
else if (ISA_MIPS32R2) \
{ \
builtin_define ("__mips=32"); \
builtin_define ("__mips_isa_rev=2"); \
} \
else if (ISA_MIPS64) \ else if (ISA_MIPS64) \
builtin_define ("__mips=64"); \ { \
builtin_define ("__mips=64"); \
builtin_define ("__mips_isa_rev=1"); \
} \
\ \
if (TARGET_HARD_FLOAT) \ if (TARGET_HARD_FLOAT) \
builtin_define ("__mips_hard_float"); \ builtin_define ("__mips_hard_float"); \
...@@ -153,7 +164,7 @@ Boston, MA 02111-1307, USA. */ ...@@ -153,7 +164,7 @@ Boston, MA 02111-1307, USA. */
"%{EL:-m elf32lmip} \ "%{EL:-m elf32lmip} \
%{EB:-m elf32bmip} \ %{EB:-m elf32bmip} \
%(endian_spec) \ %(endian_spec) \
%{G*} %{mips1} %{mips2} %{mips3} %{mips4} %{mips32} %{mips64} \ %{G*} %{mips1} %{mips2} %{mips3} %{mips4} %{mips32} %{mips32r2} %{mips64} \
%{bestGnum} %{call_shared} %{no_archive} %{exact_version} \ %{bestGnum} %{call_shared} %{no_archive} %{exact_version} \
%(netbsd_link_spec)" %(netbsd_link_spec)"
......
gcc/config/mips/t-isa3264
...@@ -33,8 +33,8 @@ TARGET_LIBGCC2_CFLAGS = -G 0 ...@@ -33,8 +33,8 @@ TARGET_LIBGCC2_CFLAGS = -G 0
# Build the libraries for both hard and soft floating point # Build the libraries for both hard and soft floating point
MULTILIB_OPTIONS = msoft-float EL/EB mips32/mips64 MULTILIB_OPTIONS = msoft-float EL/EB mips32/mips32r2/mips64
MULTILIB_DIRNAMES = soft-float el eb mips32 mips64 MULTILIB_DIRNAMES = soft-float el eb mips32 mips32r2 mips64
MULTILIB_MATCHES = EL=mel EB=meb MULTILIB_MATCHES = EL=mel EB=meb
EXTRA_MULTILIB_PARTS = crtbegin.o crtend.o crti.o crtn.o EXTRA_MULTILIB_PARTS = crtbegin.o crtend.o crti.o crtn.o
......
gcc/doc/invoke.texi
...@@ -481,7 +481,8 @@ in the following sections. ...@@ -481,7 +481,8 @@ in the following sections.
-membedded-pic -mfp32 -mfp64 -mfused-madd -mno-fused-madd @gol -membedded-pic -mfp32 -mfp64 -mfused-madd -mno-fused-madd @gol
-mgas -mgp32 -mgp64 @gol -mgas -mgp32 -mgp64 @gol
-mgpopt -mhalf-pic -mhard-float -mint64 -mips1 @gol -mgpopt -mhalf-pic -mhard-float -mint64 -mips1 @gol
-mips2 -mips3 -mips4 -mlong64 -mlong32 -mlong-calls -mmemcpy @gol -mips2 -mips3 -mips4 -mips32 -mips32r2 -mips64 @gol
-mlong64 -mlong32 -mlong-calls -mmemcpy @gol
-mmips-as -mmips-tfile -mno-abicalls @gol -mmips-as -mmips-tfile -mno-abicalls @gol
-mno-embedded-data -mno-uninit-const-in-rodata @gol -mno-embedded-data -mno-uninit-const-in-rodata @gol
-mno-embedded-pic -mno-gpopt -mno-long-calls @gol -mno-embedded-pic -mno-gpopt -mno-long-calls @gol
...@@ -7298,13 +7299,19 @@ These @samp{-m} options are defined for the MIPS family of computers: ...@@ -7298,13 +7299,19 @@ These @samp{-m} options are defined for the MIPS family of computers:
@item -march=@var{arch} @item -march=@var{arch}
@opindex march @opindex march
Generate code that will run on @var{arch}, which can be the name of a Generate code that will run on @var{arch}, which can be the name of a
generic MIPS ISA, or the name of a particular processor. The ISA names generic MIPS ISA, or the name of a particular processor.
are: @samp{mips1}, @samp{mips2}, @samp{mips3}, @samp{mips4}, @samp{mips32} The ISA names are:
and @samp{mips64}. The processor names are: @samp{r2000}, @samp{mips1}, @samp{mips2}, @samp{mips3}, @samp{mips4},
@samp{r3000}, @samp{r3900}, @samp{r4000}, @samp{vr4100}, @samp{vr4300}, @samp{mips32}, @samp{mips32r2}, and @samp{mips64}.
@samp{r4400}, @samp{r4600}, @samp{r4650}, @samp{vr5000}, @samp{r6000}, The processor names are:
@samp{r8000}, @samp{4kc}, @samp{4kp}, @samp{5kc}, @samp{20kc}, @samp{4kc}, @samp{4kp}, @samp{5kc}, @samp{20kc},
@samp{orion}, and @samp{sb1}. The special value @samp{from-abi} selects the @samp{m4k},
@samp{r2000}, @samp{r3000}, @samp{r3900}, @samp{r4000}, @samp{r4400},
@samp{r4600}, @samp{r4650}, @samp{r6000}, @samp{r8000},
@samp{orion},
@samp{sb1},
@samp{vr4100}, @samp{vr4300}, and @samp{vr5000}.
The special value @samp{from-abi} selects the
most compatible architecture for the selected ABI (that is, most compatible architecture for the selected ABI (that is,
@samp{mips1} for 32-bit ABIs and @samp{mips3} for 64-bit ABIs)@. @samp{mips1} for 32-bit ABIs and @samp{mips3} for 64-bit ABIs)@.
...@@ -7363,6 +7370,10 @@ Equivalent to @samp{-march=mips4}. ...@@ -7363,6 +7370,10 @@ Equivalent to @samp{-march=mips4}.
@opindex mips32 @opindex mips32
Equivalent to @samp{-march=mips32}. Equivalent to @samp{-march=mips32}.
@item -mips32r2
@opindex mips32r2
Equivalent to @samp{-march=mips32r2}.
@item -mips64 @item -mips64
@opindex mips64 @opindex mips64
Equivalent to @samp{-march=mips64}. Equivalent to @samp{-march=mips64}.
......
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