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riscv-gcc-1
Commit 2ce145f5 by Venkataramanan Kumar Committed by Venkataramanan Kumar
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Fix PR63190 

From-SVN: r215004
parent 9d31ea5b
Showing with 8 additions and 2 deletions
gcc/ChangeLog
2014-09-07 Venkataramanan Kumar <venkataramanan.kumar@linaro.org>
PR target/63190
* config/aarch64/aarch64.md (stack_protect_test_<mode>) Add register
constraint for operand0 and remove write only modifier from operand3.
2014-09-07 Richard Sandiford <rdsandiford@googlemail.com>
PR rtl-optimization/62208
gcc/config/aarch64/aarch64.md
......@@ -4027,11 +4027,11 @@
})
(define_insn "stack_protect_test_<mode>"
[(set (match_operand:PTR 0 "register_operand")
[(set (match_operand:PTR 0 "register_operand" "=r")
(unspec:PTR [(match_operand:PTR 1 "memory_operand" "m")
(match_operand:PTR 2 "memory_operand" "m")]
UNSPEC_SP_TEST))
(clobber (match_scratch:PTR 3 "=&r"))]
(clobber (match_scratch:PTR 3 "&r"))]
""
"ldr\t%<w>3, %x1\;ldr\t%<w>0, %x2\;eor\t%<w>0, %<w>3, %<w>0"
[(set_attr "length" "12")
......
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