Skip to content

R
riscv-gcc-1
Commit 2c2aa74d by Segher Boessenkool Committed by Segher Boessenkool
Options

rs6000: Remove Xilinx FP 

This removes the special Xilinx FP support.  It was deprecated in
GCC 8.

After this patch all of TARGET_{DOUBLE,SINGLE}_FLOAT,
TARGET_{DF,SF}_INSN, and TARGET_{DF,SF}_FPR are replaced by
TARGET_HARD_FLOAT.  Also the fp_type attribute is deleted.


	* common/config/rs6000/rs6000-common.c (rs6000_handle_option): Remove
	Xilinx FP support.
	* config.gcc (powerpc-xilinx-eabi*): Remove.
	* config/rs6000/predicates.md (easy_fp_constant): Remove Xilinx FP
	support.
	(fusion_addis_mem_combo_load): Ditto.
	* config/rs6000/rs6000-c.c (rs6000_target_modify_macros): Remove Xilinx
	FP support.
	(rs6000_cpu_cpp_builtins): Ditto.
	* config/rs6000/rs6000-linux.c
	(rs6000_linux_float_exceptions_rounding_supported_p): Ditto.
	* config/rs6000/rs6000-opts.h (enum fpu_type_t): Delete.
	* config/rs6000/rs6000.c (rs6000_debug_reg_global): Remove Xilinx FP
	support.
	(rs6000_setup_reg_addr_masks): Ditto.
	(rs6000_init_hard_regno_mode_ok): Ditto.
	(rs6000_option_override_internal): Ditto.
	(legitimate_lo_sum_address_p): Ditto.
	(rs6000_legitimize_address): Ditto.
	(rs6000_legitimize_reload_address): Ditto.
	(rs6000_legitimate_address_p): Ditto.
	(abi_v4_pass_in_fpr): Ditto.
	(setup_incoming_varargs): Ditto.
	(rs6000_gimplify_va_arg): Ditto.
	(rs6000_split_multireg_move): Ditto.
	(rs6000_savres_strategy): Ditto.
	(rs6000_emit_prologue_components): Ditto.
	(rs6000_emit_epilogue_components): Ditto.
	(rs6000_emit_prologue): Ditto.
	(rs6000_emit_epilogue): Ditto.
	(rs6000_elf_file_end): Ditto.
	(rs6000_function_value): Ditto.
	(rs6000_libcall_value): Ditto.
	* config/rs6000/rs6000.h: Ditto.
	(TARGET_MINMAX_SF, TARGET_MINMAX_DF): Delete, merge to ...
	(TARGET_MINMAX): ... this.  New.
	(TARGET_SF_FPR, TARGET_DF_FPR, TARGET_SF_INSN, TARGET_DF_INSN): Delete.
	* config/rs6000/rs6000.md: Remove Xilinx FP support.
	(*movsi_internal1_single): Delete.
	* config/rs6000/rs6000.opt (msingle-float, mdouble-float, msimple-fpu,
	mfpu=, mxilinx-fpu): Delete.
	* config/rs6000/singlefp.h: Delete.
	* config/rs6000/sysv4.h: Remove Xilinx FP support.
	* config/rs6000/t-rs6000: Ditto.
	* config/rs6000/t-xilinx: Delete.
	* gcc/config/rs6000/titan.md: Adjust for fp_type removal.
	* gcc/config/rs6000/vsx.md: Remove Xilinx FP support.
	(VStype_simple): Delete.
	(VSfptype_simple, VSfptype_mul, VSfptype_div, VSfptype_sqrt): Delete.
	* config/rs6000/xfpu.h: Delete.
	* config/rs6000/xfpu.md: Delete.
	* config/rs6000/xilinx.h: Delete.
	* config/rs6000/xilinx.opt: Delete.
	* gcc/doc/invoke.texi (RS/6000 and PowerPC Options): Remove
	-msingle-float, -mdouble-float, -msimple-fpu, -mfpu=, and -mxilinx-fpu.

From-SVN: r259929
parent d6ed6b07
Showing with 107 additions and 602 deletions
gcc/ChangeLog
2018-05-04 Segher Boessenkool <segher@kernel.crashing.org>
* common/config/rs6000/rs6000-common.c (rs6000_handle_option): Remove
Xilinx FP support.
* config.gcc (powerpc-xilinx-eabi*): Remove.
* config/rs6000/predicates.md (easy_fp_constant): Remove Xilinx FP
support.
(fusion_addis_mem_combo_load): Ditto.
* config/rs6000/rs6000-c.c (rs6000_target_modify_macros): Remove Xilinx
FP support.
(rs6000_cpu_cpp_builtins): Ditto.
* config/rs6000/rs6000-linux.c
(rs6000_linux_float_exceptions_rounding_supported_p): Ditto.
* config/rs6000/rs6000-opts.h (enum fpu_type_t): Delete.
* config/rs6000/rs6000.c (rs6000_debug_reg_global): Remove Xilinx FP
support.
(rs6000_setup_reg_addr_masks): Ditto.
(rs6000_init_hard_regno_mode_ok): Ditto.
(rs6000_option_override_internal): Ditto.
(legitimate_lo_sum_address_p): Ditto.
(rs6000_legitimize_address): Ditto.
(rs6000_legitimize_reload_address): Ditto.
(rs6000_legitimate_address_p): Ditto.
(abi_v4_pass_in_fpr): Ditto.
(setup_incoming_varargs): Ditto.
(rs6000_gimplify_va_arg): Ditto.
(rs6000_split_multireg_move): Ditto.
(rs6000_savres_strategy): Ditto.
(rs6000_emit_prologue_components): Ditto.
(rs6000_emit_epilogue_components): Ditto.
(rs6000_emit_prologue): Ditto.
(rs6000_emit_epilogue): Ditto.
(rs6000_elf_file_end): Ditto.
(rs6000_function_value): Ditto.
(rs6000_libcall_value): Ditto.
* config/rs6000/rs6000.h: Ditto.
(TARGET_MINMAX_SF, TARGET_MINMAX_DF): Delete, merge to ...
(TARGET_MINMAX): ... this. New.
(TARGET_SF_FPR, TARGET_DF_FPR, TARGET_SF_INSN, TARGET_DF_INSN): Delete.
* config/rs6000/rs6000.md: Remove Xilinx FP support.
(*movsi_internal1_single): Delete.
* config/rs6000/rs6000.opt (msingle-float, mdouble-float, msimple-fpu,
mfpu=, mxilinx-fpu): Delete.
* config/rs6000/singlefp.h: Delete.
* config/rs6000/sysv4.h: Remove Xilinx FP support.
* config/rs6000/t-rs6000: Ditto.
* config/rs6000/t-xilinx: Delete.
* gcc/config/rs6000/titan.md: Adjust for fp_type removal.
* gcc/config/rs6000/vsx.md: Remove Xilinx FP support.
(VStype_simple): Delete.
(VSfptype_simple, VSfptype_mul, VSfptype_div, VSfptype_sqrt): Delete.
* config/rs6000/xfpu.h: Delete.
* config/rs6000/xfpu.md: Delete.
* config/rs6000/xilinx.h: Delete.
* config/rs6000/xilinx.opt: Delete.
* gcc/doc/invoke.texi (RS/6000 and PowerPC Options): Remove
-msingle-float, -mdouble-float, -msimple-fpu, -mfpu=, and -mxilinx-fpu.
2018-05-04 Tom de Vries <tom@codesourcery.com> 2018-05-04 Tom de Vries <tom@codesourcery.com>
PR libgomp/85639 PR libgomp/85639
......
gcc/common/config/rs6000/rs6000-common.c
...@@ -83,7 +83,6 @@ rs6000_handle_option (struct gcc_options *opts, struct gcc_options *opts_set, ...@@ -83,7 +83,6 @@ rs6000_handle_option (struct gcc_options *opts, struct gcc_options *opts_set,
const struct cl_decoded_option *decoded, const struct cl_decoded_option *decoded,
location_t loc) location_t loc)
{ {
enum fpu_type_t fpu_type = FPU_NONE;
char *p, *q; char *p, *q;
size_t code = decoded->opt_index; size_t code = decoded->opt_index;
const char *arg = decoded->arg; const char *arg = decoded->arg;
...@@ -225,63 +224,6 @@ rs6000_handle_option (struct gcc_options *opts, struct gcc_options *opts_set, ...@@ -225,63 +224,6 @@ rs6000_handle_option (struct gcc_options *opts, struct gcc_options *opts_set,
} }
break; break;
case OPT_msingle_float:
if (!TARGET_SINGLE_FPU)
warning_at (loc, 0,
"-msingle-float option equivalent to -mhard-float");
/* -msingle-float implies -mno-double-float and TARGET_HARD_FLOAT. */
opts->x_rs6000_double_float = 0;
opts->x_rs6000_isa_flags &= ~OPTION_MASK_SOFT_FLOAT;
opts_set->x_rs6000_isa_flags |= OPTION_MASK_SOFT_FLOAT;
break;
case OPT_mdouble_float:
/* -mdouble-float implies -msingle-float and TARGET_HARD_FLOAT. */
opts->x_rs6000_single_float = 1;
opts->x_rs6000_isa_flags &= ~OPTION_MASK_SOFT_FLOAT;
opts_set->x_rs6000_isa_flags |= OPTION_MASK_SOFT_FLOAT;
break;
case OPT_msimple_fpu:
if (!TARGET_SINGLE_FPU)
warning_at (loc, 0, "-msimple-fpu option ignored");
break;
case OPT_mhard_float:
/* -mhard_float implies -msingle-float and -mdouble-float. */
opts->x_rs6000_single_float = opts->x_rs6000_double_float = 1;
break;
case OPT_msoft_float:
/* -msoft_float implies -mnosingle-float and -mnodouble-float. */
opts->x_rs6000_single_float = opts->x_rs6000_double_float = 0;
break;
case OPT_mfpu_:
fpu_type = (enum fpu_type_t) value;
if (fpu_type != FPU_NONE)
{
/* If -mfpu is not none, then turn off SOFT_FLOAT, turn on
HARD_FLOAT. */
opts->x_rs6000_isa_flags &= ~OPTION_MASK_SOFT_FLOAT;
opts_set->x_rs6000_isa_flags |= OPTION_MASK_SOFT_FLOAT;
opts->x_rs6000_xilinx_fpu = 1;
if (fpu_type == FPU_SF_LITE || fpu_type == FPU_SF_FULL)
opts->x_rs6000_single_float = 1;
if (fpu_type == FPU_DF_LITE || fpu_type == FPU_DF_FULL)
opts->x_rs6000_single_float = opts->x_rs6000_double_float = 1;
if (fpu_type == FPU_SF_LITE || fpu_type == FPU_DF_LITE)
opts->x_rs6000_simple_fpu = 1;
}
else
{
/* -mfpu=none is equivalent to -msoft-float. */
opts->x_rs6000_isa_flags |= OPTION_MASK_SOFT_FLOAT;
opts_set->x_rs6000_isa_flags |= OPTION_MASK_SOFT_FLOAT;
opts->x_rs6000_single_float = opts->x_rs6000_double_float = 0;
}
break;
case OPT_mrecip: case OPT_mrecip:
opts->x_rs6000_recip_name = (value) ? "default" : "none"; opts->x_rs6000_recip_name = (value) ? "default" : "none";
break; break;
......
gcc/config.gcc
...@@ -2451,12 +2451,6 @@ powerpc-*-eabialtivec*) ...@@ -2451,12 +2451,6 @@ powerpc-*-eabialtivec*)
tmake_file="rs6000/t-fprules rs6000/t-ppcendian rs6000/t-ppccomm" tmake_file="rs6000/t-fprules rs6000/t-ppcendian rs6000/t-ppccomm"
use_gcc_stdint=wrap use_gcc_stdint=wrap
;; ;;
powerpc-xilinx-eabi*)
tm_file="${tm_file} dbxelf.h elfos.h usegas.h freebsd-spec.h newlib-stdint.h rs6000/sysv4.h rs6000/eabi.h rs6000/singlefp.h rs6000/xfpu.h rs6000/xilinx.h"
extra_options="${extra_options} rs6000/sysv4.opt rs6000/xilinx.opt"
tmake_file="rs6000/t-fprules rs6000/t-ppcgas rs6000/t-ppccomm rs6000/t-xilinx"
use_gcc_stdint=wrap
;;
powerpc-*-eabi*) powerpc-*-eabi*)
tm_file="${tm_file} dbxelf.h elfos.h usegas.h freebsd-spec.h newlib-stdint.h rs6000/sysv4.h rs6000/eabi.h" tm_file="${tm_file} dbxelf.h elfos.h usegas.h freebsd-spec.h newlib-stdint.h rs6000/sysv4.h rs6000/eabi.h"
extra_options="${extra_options} rs6000/sysv4.opt" extra_options="${extra_options} rs6000/sysv4.opt"
......
gcc/config/rs6000/predicates.md
...@@ -611,9 +611,7 @@ ...@@ -611,9 +611,7 @@
return 0; return 0;
/* Consider all constants with -msoft-float to be easy. */ /* Consider all constants with -msoft-float to be easy. */
if ((TARGET_SOFT_FLOAT if (TARGET_SOFT_FLOAT && mode != DImode)
|| (TARGET_HARD_FLOAT && (TARGET_SINGLE_FLOAT && ! TARGET_DOUBLE_FLOAT)))
&& mode != DImode)
return 1; return 1;
/* 0.0D is not all zero bits. */ /* 0.0D is not all zero bits. */
...@@ -1835,7 +1833,7 @@ ...@@ -1835,7 +1833,7 @@
DFmode in 32-bit if -msoft-float since it splits into two separate DFmode in 32-bit if -msoft-float since it splits into two separate
instructions. */ instructions. */
case E_DFmode: case E_DFmode:
if ((!TARGET_POWERPC64 && !TARGET_DF_FPR) || !TARGET_P9_FUSION) if ((!TARGET_POWERPC64 && !TARGET_HARD_FLOAT) || !TARGET_P9_FUSION)
return 0; return 0;
break; break;
...@@ -1895,7 +1893,7 @@ ...@@ -1895,7 +1893,7 @@
into two separate instructions. Do allow fusion if we have hardware into two separate instructions. Do allow fusion if we have hardware
floating point. */ floating point. */
case E_DFmode: case E_DFmode:
if (!TARGET_POWERPC64 && !TARGET_DF_FPR) if (!TARGET_POWERPC64 && !TARGET_HARD_FLOAT)
return 0; return 0;
break; break;
......
gcc/config/rs6000/rs6000-c.c
...@@ -490,8 +490,7 @@ rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT flags, ...@@ -490,8 +490,7 @@ rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT flags,
the following conditions: the following conditions:
1. The operating system does not support saving of AltiVec 1. The operating system does not support saving of AltiVec
registers (OS_MISSING_ALTIVEC). registers (OS_MISSING_ALTIVEC).
2. If any of the options TARGET_HARD_FLOAT, TARGET_SINGLE_FLOAT, 2. If the option TARGET_HARD_FLOAT is turned off. Hereafter, the
or TARGET_DOUBLE_FLOAT are turned off. Hereafter, the
OPTION_MASK_VSX flag is considered to have been turned off OPTION_MASK_VSX flag is considered to have been turned off
explicitly. explicitly.
3. If TARGET_AVOID_XFORM is turned on explicitly at the outermost 3. If TARGET_AVOID_XFORM is turned on explicitly at the outermost
...@@ -635,7 +634,7 @@ rs6000_cpu_cpp_builtins (cpp_reader *pfile) ...@@ -635,7 +634,7 @@ rs6000_cpu_cpp_builtins (cpp_reader *pfile)
cpp_get_callbacks (pfile)->macro_to_expand = rs6000_macro_to_expand; cpp_get_callbacks (pfile)->macro_to_expand = rs6000_macro_to_expand;
} }
} }
if (!TARGET_HARD_FLOAT || !TARGET_DOUBLE_FLOAT) if (!TARGET_HARD_FLOAT)
builtin_define ("_SOFT_DOUBLE"); builtin_define ("_SOFT_DOUBLE");
/* Used by lwarx/stwcx. errata work-around. */ /* Used by lwarx/stwcx. errata work-around. */
if (rs6000_cpu == PROCESSOR_PPC405) if (rs6000_cpu == PROCESSOR_PPC405)
...@@ -766,26 +765,6 @@ rs6000_cpu_cpp_builtins (cpp_reader *pfile) ...@@ -766,26 +765,6 @@ rs6000_cpu_cpp_builtins (cpp_reader *pfile)
|| DEFAULT_ABI == ABI_ELFv2 || DEFAULT_ABI == ABI_ELFv2
|| (DEFAULT_ABI == ABI_AIX && !rs6000_compat_align_parm)) || (DEFAULT_ABI == ABI_AIX && !rs6000_compat_align_parm))
builtin_define ("__STRUCT_PARM_ALIGN__=16"); builtin_define ("__STRUCT_PARM_ALIGN__=16");
/* Generate defines for Xilinx FPU. */
if (rs6000_xilinx_fpu)
{
builtin_define ("_XFPU");
if (rs6000_single_float && ! rs6000_double_float)
{
if (rs6000_simple_fpu)
builtin_define ("_XFPU_SP_LITE");
else
builtin_define ("_XFPU_SP_FULL");
}
if (rs6000_double_float)
{
if (rs6000_simple_fpu)
builtin_define ("_XFPU_DP_LITE");
else
builtin_define ("_XFPU_DP_FULL");
}
}
} }
......
gcc/config/rs6000/rs6000-linux.c
...@@ -34,5 +34,5 @@ rs6000_linux_float_exceptions_rounding_supported_p (void) ...@@ -34,5 +34,5 @@ rs6000_linux_float_exceptions_rounding_supported_p (void)
if (OPTION_GLIBC) if (OPTION_GLIBC)
return true; return true;
else else
return TARGET_DF_INSN; return TARGET_HARD_FLOAT;
} }
gcc/config/rs6000/rs6000-opts.h
...@@ -70,17 +70,6 @@ enum processor_type ...@@ -70,17 +70,6 @@ enum processor_type
}; };
/* FP processor type. */
enum fpu_type_t
{
FPU_NONE, /* No FPU */
FPU_SF_LITE, /* Limited Single Precision FPU */
FPU_DF_LITE, /* Limited Double Precision FPU */
FPU_SF_FULL, /* Full Single Precision FPU */
FPU_DF_FULL /* Full Double Single Precision FPU */
};
/* Types of costly dependences. */ /* Types of costly dependences. */
enum rs6000_dependence_cost enum rs6000_dependence_cost
{ {
......
gcc/config/rs6000/rs6000.h
...@@ -378,15 +378,6 @@ extern const char *host_detect_local_cpu (int argc, const char **argv); ...@@ -378,15 +378,6 @@ extern const char *host_detect_local_cpu (int argc, const char **argv);
#define TARGET_DEFAULT (MASK_MULTIPLE) #define TARGET_DEFAULT (MASK_MULTIPLE)
/* FPU operations supported.
Each use of TARGET_SINGLE_FLOAT or TARGET_DOUBLE_FLOAT must
also test TARGET_HARD_FLOAT. */
#define TARGET_SINGLE_FLOAT 1
#define TARGET_DOUBLE_FLOAT 1
#define TARGET_SINGLE_FPU 0
#define TARGET_SIMPLE_FPU 0
#define TARGET_XILINX_FPU 0
/* Define generic processor types based upon current deployment. */ /* Define generic processor types based upon current deployment. */
#define PROCESSOR_COMMON PROCESSOR_PPC601 #define PROCESSOR_COMMON PROCESSOR_PPC601
#define PROCESSOR_POWERPC PROCESSOR_PPC604 #define PROCESSOR_POWERPC PROCESSOR_PPC604
...@@ -567,14 +558,12 @@ extern int rs6000_vector_align[]; ...@@ -567,14 +558,12 @@ extern int rs6000_vector_align[];
#endif #endif
/* ISA 2.01 allowed FCFID to be done in 32-bit, previously it was 64-bit only. /* ISA 2.01 allowed FCFID to be done in 32-bit, previously it was 64-bit only.
Enable 32-bit fcfid's on any of the switches for newer ISA machines or Enable 32-bit fcfid's on any of the switches for newer ISA machines. */
XILINX. */
#define TARGET_FCFID (TARGET_POWERPC64 \ #define TARGET_FCFID (TARGET_POWERPC64 \
|| TARGET_PPC_GPOPT /* 970/power4 */ \ || TARGET_PPC_GPOPT /* 970/power4 */ \
|| TARGET_POPCNTB /* ISA 2.02 */ \ || TARGET_POPCNTB /* ISA 2.02 */ \
|| TARGET_CMPB /* ISA 2.05 */ \ || TARGET_CMPB /* ISA 2.05 */ \
|| TARGET_POPCNTD /* ISA 2.06 */ \ || TARGET_POPCNTD) /* ISA 2.06 */
|| TARGET_XILINX_FPU)
#define TARGET_FCTIDZ TARGET_FCFID #define TARGET_FCTIDZ TARGET_FCFID
#define TARGET_STFIWX TARGET_PPC_GFXOPT #define TARGET_STFIWX TARGET_PPC_GFXOPT
...@@ -622,11 +611,8 @@ extern int rs6000_vector_align[]; ...@@ -622,11 +611,8 @@ extern int rs6000_vector_align[];
/* ISA 3.0 has new min/max functions that don't need fast math that are being /* ISA 3.0 has new min/max functions that don't need fast math that are being
phased in. Min/max using FSEL or XSMAXDP/XSMINDP do not return the correct phased in. Min/max using FSEL or XSMAXDP/XSMINDP do not return the correct
answers if the arguments are not in the normal range. */ answers if the arguments are not in the normal range. */
#define TARGET_MINMAX_SF (TARGET_SF_FPR && TARGET_PPC_GFXOPT \ #define TARGET_MINMAX (TARGET_HARD_FLOAT && TARGET_PPC_GFXOPT \
&& (TARGET_P9_MINMAX || !flag_trapping_math)) && (TARGET_P9_MINMAX || !flag_trapping_math))
#define TARGET_MINMAX_DF (TARGET_DF_FPR && TARGET_PPC_GFXOPT \
&& (TARGET_P9_MINMAX || !flag_trapping_math))
/* In switching from using target_flags to using rs6000_isa_flags, the options /* In switching from using target_flags to using rs6000_isa_flags, the options
machinery creates OPTION_MASK_<xxx> instead of MASK_<xxx>. For now map machinery creates OPTION_MASK_<xxx> instead of MASK_<xxx>. For now map
...@@ -707,26 +693,16 @@ extern int rs6000_vector_align[]; ...@@ -707,26 +693,16 @@ extern int rs6000_vector_align[];
|| rs6000_cpu == PROCESSOR_PPC8548) || rs6000_cpu == PROCESSOR_PPC8548)
/* Whether SF/DF operations are supported by the normal floating point unit
(or the vector/scalar unit). */
#define TARGET_SF_FPR (TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT)
#define TARGET_DF_FPR (TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT)
/* Whether SF/DF operations are supported by any hardware. */
#define TARGET_SF_INSN TARGET_SF_FPR
#define TARGET_DF_INSN TARGET_DF_FPR
/* Which machine supports the various reciprocal estimate instructions. */ /* Which machine supports the various reciprocal estimate instructions. */
#define TARGET_FRES (TARGET_HARD_FLOAT && TARGET_PPC_GFXOPT \ #define TARGET_FRES (TARGET_HARD_FLOAT && TARGET_PPC_GFXOPT)
&& TARGET_SINGLE_FLOAT)
#define TARGET_FRE (TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT \ #define TARGET_FRE (TARGET_HARD_FLOAT \
&& (TARGET_POPCNTB || VECTOR_UNIT_VSX_P (DFmode))) && (TARGET_POPCNTB || VECTOR_UNIT_VSX_P (DFmode)))
#define TARGET_FRSQRTES (TARGET_HARD_FLOAT && TARGET_POPCNTB \ #define TARGET_FRSQRTES (TARGET_HARD_FLOAT && TARGET_POPCNTB \
&& TARGET_PPC_GFXOPT && TARGET_SINGLE_FLOAT) && TARGET_PPC_GFXOPT)
#define TARGET_FRSQRTE (TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT \ #define TARGET_FRSQRTE (TARGET_HARD_FLOAT \
&& (TARGET_PPC_GFXOPT || VECTOR_UNIT_VSX_P (DFmode))) && (TARGET_PPC_GFXOPT || VECTOR_UNIT_VSX_P (DFmode)))
/* Conditions to allow TOC fusion for loading/storing integers. */ /* Conditions to allow TOC fusion for loading/storing integers. */
...@@ -740,9 +716,7 @@ extern int rs6000_vector_align[]; ...@@ -740,9 +716,7 @@ extern int rs6000_vector_align[];
&& TARGET_TOC_FUSION \ && TARGET_TOC_FUSION \
&& (TARGET_CMODEL != CMODEL_SMALL) \ && (TARGET_CMODEL != CMODEL_SMALL) \
&& TARGET_POWERPC64 \ && TARGET_POWERPC64 \
&& TARGET_HARD_FLOAT \ && TARGET_HARD_FLOAT)
&& TARGET_SINGLE_FLOAT \
&& TARGET_DOUBLE_FLOAT)
/* Macro to say whether we can do optimizations where we need to do parts of /* Macro to say whether we can do optimizations where we need to do parts of
the calculation in 64-bit GPRs and then is transfered to the vector the calculation in 64-bit GPRs and then is transfered to the vector
......
gcc/config/rs6000/rs6000.opt
...@@ -463,44 +463,6 @@ mprioritize-restricted-insns= ...@@ -463,44 +463,6 @@ mprioritize-restricted-insns=
Target RejectNegative Joined UInteger Var(rs6000_sched_restricted_insns_priority) Save Target RejectNegative Joined UInteger Var(rs6000_sched_restricted_insns_priority) Save
Specify scheduling priority for dispatch slot restricted insns. Specify scheduling priority for dispatch slot restricted insns.
msingle-float
Target RejectNegative Var(rs6000_single_float) Save
Single-precision floating point unit.
mdouble-float
Target RejectNegative Var(rs6000_double_float) Save
Double-precision floating point unit.
msimple-fpu
Target RejectNegative Var(rs6000_simple_fpu) Save
Floating point unit does not support divide & sqrt.
mfpu=
Target RejectNegative Joined Enum(fpu_type_t) Var(rs6000_fpu_type) Init(FPU_NONE)
-mfpu= Specify FP (sp, dp, sp-lite, dp-lite) (implies -mxilinx-fpu).
Enum
Name(fpu_type_t) Type(enum fpu_type_t)
EnumValue
Enum(fpu_type_t) String(none) Value(FPU_NONE)
EnumValue
Enum(fpu_type_t) String(sp_lite) Value(FPU_SF_LITE)
EnumValue
Enum(fpu_type_t) String(dp_lite) Value(FPU_DF_LITE)
EnumValue
Enum(fpu_type_t) String(sp_full) Value(FPU_SF_FULL)
EnumValue
Enum(fpu_type_t) String(dp_full) Value(FPU_DF_FULL)
mxilinx-fpu
Target Var(rs6000_xilinx_fpu) Save
Specify Xilinx FPU.
mpointers-to-nested-functions mpointers-to-nested-functions
Target Report Var(TARGET_POINTERS_TO_NESTED_FUNCTIONS) Init(1) Save Target Report Var(TARGET_POINTERS_TO_NESTED_FUNCTIONS) Init(1) Save
Use r11 to hold the static link in calls to functions via pointers. Use r11 to hold the static link in calls to functions via pointers.
......
gcc/config/rs6000/singlefp.h deleted 100644 → 0
/* Definitions for PowerPC single-precision floating point unit
such as Xilinx PowerPC 405/440 APU.
Copyright (C) 2008-2018 Free Software Foundation, Inc.
Contributed by Michael Eager (eager@eagercon.com)
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
You should have received a copy of the GNU General Public License
along with GCC; see the file COPYING3. If not see
<http://www.gnu.org/licenses/>. */
/* Undefine definitions from rs6000.h. */
#undef TARGET_SINGLE_FLOAT
#undef TARGET_DOUBLE_FLOAT
#undef TARGET_SINGLE_FPU
#undef TARGET_SIMPLE_FPU
#undef UNITS_PER_FP_WORD
/* FPU operations supported.
If TARGET_SINGLE_FPU set, processor supports single fp options. */
#define TARGET_SINGLE_FLOAT (rs6000_single_float)
#define TARGET_DOUBLE_FLOAT (rs6000_double_float)
#define TARGET_SINGLE_FPU 1
#define TARGET_SIMPLE_FPU (rs6000_simple_fpu)
/* FP word width depends on single/double fp support. */
#define UNITS_PER_FP_WORD ((TARGET_SOFT_FLOAT || TARGET_DOUBLE_FLOAT) ? 8 : 4)
gcc/config/rs6000/sysv4.h
...@@ -608,9 +608,6 @@ ENDIAN_SELECT(" -mbig", " -mlittle", DEFAULT_ASM_ENDIAN) ...@@ -608,9 +608,6 @@ ENDIAN_SELECT(" -mbig", " -mlittle", DEFAULT_ASM_ENDIAN)
#define LINK_OS_DEFAULT_SPEC "" #define LINK_OS_DEFAULT_SPEC ""
#define DRIVER_SELF_SPECS "%{mfpu=none: %<mfpu=* \
%<msingle-float %<mdouble-float}"
/* Override rs6000.h definition. */ /* Override rs6000.h definition. */
#undef CPP_SPEC #undef CPP_SPEC
#define CPP_SPEC "%{posix: -D_POSIX_SOURCE} \ #define CPP_SPEC "%{posix: -D_POSIX_SOURCE} \
......
gcc/config/rs6000/t-rs6000
...@@ -61,7 +61,6 @@ MD_INCLUDES = $(srcdir)/config/rs6000/rs64.md \ ...@@ -61,7 +61,6 @@ MD_INCLUDES = $(srcdir)/config/rs6000/rs64.md \
$(srcdir)/config/rs6000/power8.md \ $(srcdir)/config/rs6000/power8.md \
$(srcdir)/config/rs6000/power9.md \ $(srcdir)/config/rs6000/power9.md \
$(srcdir)/config/rs6000/cell.md \ $(srcdir)/config/rs6000/cell.md \
$(srcdir)/config/rs6000/xfpu.md \
$(srcdir)/config/rs6000/a2.md \ $(srcdir)/config/rs6000/a2.md \
$(srcdir)/config/rs6000/predicates.md \ $(srcdir)/config/rs6000/predicates.md \
$(srcdir)/config/rs6000/constraints.md \ $(srcdir)/config/rs6000/constraints.md \
......
gcc/config/rs6000/t-xilinx deleted 100644 → 0
# Multilibs for Xilinx powerpc embedded ELF targets.
#
# Copyright (C) 2009-2018 Free Software Foundation, Inc.
# Contributed by Michael Eager, eager@eagercon.com
#
# This file is part of GCC.
#
# GCC is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 3, or (at your option)
# any later version.
#
# GCC is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with GCC; see the file COPYING3. If not see
# <http://www.gnu.org/licenses/>.
# Switch synonyms
MULTILIB_MATCHES = mfpu?sp_lite=msingle-float mfpu?dp_lite=mdouble-float mfpu?dp_lite=mhard-float mfpu?sp_lite=mfpu?sp_full mfpu?dp_lite=mfpu?dp_full
MULTILIB_OPTIONS = mfpu=sp_lite/mfpu=dp_lite
MULTILIB_DIRNAMES = single double
gcc/config/rs6000/titan.md
...@@ -148,11 +148,6 @@ ...@@ -148,11 +148,6 @@
(eq_attr "cpu" "titan")) (eq_attr "cpu" "titan"))
"titan_issue,titan_fpdiv*46,titan_fpwb") "titan_issue,titan_fpdiv*46,titan_fpwb")
(define_insn_reservation "titan_fp_single" 12
(and (eq_attr "fp_type" "fp_addsub_s,fp_mul_s,fp_maddsub_s")
(eq_attr "cpu" "titan"))
"titan_issue,titan_fp0*2,nothing*10,titan_fpwb")
;; Make sure the "titan_fp" rule stays last, as it's a catch all for ;; Make sure the "titan_fp" rule stays last, as it's a catch all for
;; double-precision and unclassified (e.g. fsel) FP-instructions ;; double-precision and unclassified (e.g. fsel) FP-instructions
(define_insn_reservation "titan_fp" 10 (define_insn_reservation "titan_fp" 10
......
gcc/config/rs6000/xfpu.h deleted 100644 → 0
/* Definitions for Xilinx PowerPC 405/440 APU.
Copyright (C) 2008-2018 Free Software Foundation, Inc.
Contributed by Michael Eager (eager@eagercon.com)
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
You should have received a copy of the GNU General Public License
along with GCC; see the file COPYING3. If not see
<http://www.gnu.org/licenses/>. */
/* Undefine definitions from rs6000.h. */
#undef TARGET_XILINX_FPU
#define TARGET_XILINX_FPU (rs6000_xilinx_fpu)
gcc/config/rs6000/xfpu.md deleted 100644 → 0
;; Scheduling description for the Xilinx PowerPC 405 APU Floating Point Unit.
;; Copyright (C) 2008-2018 Free Software Foundation, Inc.
;; Contributed by Michael Eager (eager@eagercon.com).
;;
;; This file is part of GCC.
;;
;; GCC is free software; you can redistribute it and/or modify
;; it under the terms of the GNU General Public License as published by
;; the Free Software Foundation; either version 3, or (at your option)
;; any later version.
;;
;; GCC is distributed in the hope that it will be useful,
;; but WITHOUT ANY WARRANTY; without even the implied warranty of
;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
;; GNU General Public License for more details.
;;
;; You should have received a copy of the GNU General Public License
;; along with GCC; see the file COPYING3. If not see
;; <http://www.gnu.org/licenses/>.
;;----------------------------------------------------
;; Xilinx APU FPU Pipeline Description
;;
;; - attr 'type' and 'fp_type' should definitely
;; be cleaned up at some point in the future.
;; ddiv,sdiv,dmul,smul etc are quite confusing.
;; Should use consistent fp* attrs. 'fp_type'
;; should also go away, leaving us only with 'fp'
;;
;;----------------------------------------------------
;; -------------------------------------------------------------------------
;; Latencies
;; Latest latency figures (all in FCB cycles). PowerPC to FPU frequency ratio
;; assumed to be 1/2. (most common deployment)
;; Add 2 PPC cycles for (register file access + wb) and 2 PPC cycles
;; for issue (from PPC)
;; SP DP
;; Loads: 4 6
;; Stores: 1 2 (from availability of data)
;; Move/Abs/Neg: 1 1
;; Add/Subtract: 5 7
;; Multiply: 4 11
;; Multiply-add: 10 19
;; Convert (any): 4 6
;; Divide/Sqrt: 27 56
;; Compares: 1 2
;;
;; bypasses needed for forwarding capability of the FPU.
;; Add this at some future time.
;; -------------------------------------------------------------------------
(define_automaton "Xfpu")
(define_cpu_unit "Xfpu_issue,Xfpu_addsub,Xfpu_mul,Xfpu_div,Xfpu_sqrt" "Xfpu")
(define_insn_reservation "fp-default" 2
(and (and
(eq_attr "type" "fp,fpsimple")
(eq_attr "fp_type" "fp_default"))
(eq_attr "cpu" "ppc405"))
"Xfpu_issue*2")
(define_insn_reservation "fp-compare" 6
(and (eq_attr "type" "fpcompare") ;; Inconsistent naming
(eq_attr "cpu" "ppc405"))
"Xfpu_issue*2,Xfpu_addsub")
(define_insn_reservation "fp-addsub-s" 14
(and (and
(eq_attr "type" "fp,fpsimple")
(eq_attr "fp_type" "fp_addsub_s"))
(eq_attr "cpu" "ppc405"))
"Xfpu_issue*2,Xfpu_addsub")
(define_insn_reservation "fp-addsub-d" 18
(and (and
(eq_attr "type" "fp,fpsimple")
(eq_attr "fp_type" "fp_addsub_d"))
(eq_attr "cpu" "ppc405"))
"Xfpu_issue*2,Xfpu_addsub")
(define_insn_reservation "fp-mul-s" 12
(and (and
(eq_attr "type" "fp")
(eq_attr "fp_type" "fp_mul_s"))
(eq_attr "cpu" "ppc405"))
"Xfpu_issue*2,Xfpu_mul")
(define_insn_reservation "fp-mul-d" 16 ;; Actually 28. Long latencies are killing the automaton formation. Need to figure out why.
(and (and
(eq_attr "type" "fp")
(eq_attr "fp_type" "fp_mul_d"))
(eq_attr "cpu" "ppc405"))
"Xfpu_issue*2,Xfpu_mul")
(define_insn_reservation "fp-div-s" 24 ;; Actually 34
(and (eq_attr "type" "sdiv") ;; Inconsistent attr naming
(eq_attr "cpu" "ppc405"))
"Xfpu_issue*2,Xfpu_div*10") ;; Unpipelined
(define_insn_reservation "fp-div-d" 34 ;; Actually 116
(and (eq_attr "type" "ddiv")
(eq_attr "cpu" "ppc405")) ;; Inconsistent attr naming
"Xfpu_issue*2,Xfpu_div*10") ;; Unpipelined
(define_insn_reservation "fp-maddsub-s" 24
(and (and
(eq_attr "type" "fp")
(eq_attr "fp_type" "fp_maddsub_s"))
(eq_attr "cpu" "ppc405"))
"Xfpu_issue*2,Xfpu_mul,nothing*7,Xfpu_addsub")
(define_insn_reservation "fp-maddsub-d" 34 ;; Actually 42
(and (and
(eq_attr "type" "dmul") ;; Inconsistent attr naming
(eq_attr "fp_type" "fp_maddsub_d"))
(eq_attr "cpu" "ppc405"))
"Xfpu_issue*2,Xfpu_mul,nothing*7,Xfpu_addsub")
(define_insn_reservation "fp-load" 10 ;; FIXME. Is double/single precision the same ?
(and (eq_attr "type" "fpload")
(eq_attr "cpu" "ppc405"))
"Xfpu_issue*10")
(define_insn_reservation "fp-store" 4
(and (eq_attr "type" "fpstore")
(eq_attr "cpu" "ppc405"))
"Xfpu_issue*4")
(define_insn_reservation "fp-sqrt-s" 24 ;; Actually 56
(and (eq_attr "type" "ssqrt")
(eq_attr "cpu" "ppc405"))
"Xfpu_issue*2,Xfpu_sqrt*10") ;; Unpipelined
(define_insn_reservation "fp-sqrt-d" 34 ;; Actually 116
(and (eq_attr "type" "dsqrt")
(eq_attr "cpu" "ppc405"))
"Xfpu_issue*2,Xfpu_sqrt*10") ;; Unpipelined
gcc/config/rs6000/xilinx.h deleted 100644 → 0
/* Support for GCC on Xilinx embedded PowerPC systems
Copyright (C) 2008-2018 Free Software Foundation, Inc.
Contributed by Michael Eager, eager@eagercon.com
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
You should have received a copy of the GNU General Public License
along with GCC; see the file COPYING3. If not see
<http://www.gnu.org/licenses/>. */
/* Set defaults for Xilinx embedded target boards. */
#undef CPP_SPEC
#define CPP_SPEC "\
-mxilinx-fpu \
%{mfpu=sp_lite: -DHAVE_XFPU_SP_LITE} \
%{mfpu=sp_full: -DHAVE_XFPU_SP_FULL} \
%{mfpu=dp_lite: -DHAVE_XFPU_DP_LITE} \
%{mfpu=dp_full: -DHAVE_XFPU_DP_FULL} \
%{mfpu=*: -DHAVE_XFPU}"
#undef LIB_DEFAULT_SPEC
#define LIB_DEFAULT_SPEC "\
%{!nostdlib: --start-group -lxil -lc -lm --end-group \
%{mppcperflib: %{mfpu=*: -lppcstr405 -lgcc} \
%{!mfpu=*: -lppcstr405 -lppcfp -lgcc}} \
%{!mppcperflib: -lgcc}}"
#undef STARTFILE_DEFAULT_SPEC
#define STARTFILE_DEFAULT_SPEC "\
ecrti.o%s %{pg: %{!mno-clearbss: xil-pgcrt0.o%s} \
%{mno-clearbss: xil-sim-pgcrt0.o%s}} \
%{!pg: %{!mno-clearbss: xil-crt0.o%s} \
%{mno-clearbss: xil-sim-crt0.o%s}} crtbegin.o%s"
#undef LINK_START_DEFAULT_SPEC
#define LINK_START_DEFAULT_SPEC "-T xilinx.ld%s"
gcc/config/rs6000/xilinx.opt deleted 100644 → 0
; Xilinx embedded PowerPC options.
; Copyright (C) 2011-2018 Free Software Foundation, Inc.
;
; This file is part of GCC.
;
; GCC is free software; you can redistribute it and/or modify it under
; the terms of the GNU General Public License as published by the Free
; Software Foundation; either version 3, or (at your option) any later
; version.
;
; GCC is distributed in the hope that it will be useful, but WITHOUT ANY
; WARRANTY; without even the implied warranty of MERCHANTABILITY or
; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
; for more details.
;
; You should have received a copy of the GNU General Public License
; along with GCC; see the file COPYING3. If not see
; <http://www.gnu.org/licenses/>.
; See the GCC internals manual (options.texi) for a description of
; this file's format.
; Please try to keep this file in ASCII collating order.
mno-clearbss
Target RejectNegative
mppcperflib
Target RejectNegative
; This comment is to ensure we retain the blank line above.
gcc/doc/invoke.texi
...@@ -1065,7 +1065,6 @@ See RS/6000 and PowerPC Options. ...@@ -1065,7 +1065,6 @@ See RS/6000 and PowerPC Options.
-m64 -m32 -mxl-compat -mno-xl-compat -mpe @gol -m64 -m32 -mxl-compat -mno-xl-compat -mpe @gol
-malign-power -malign-natural @gol -malign-power -malign-natural @gol
-msoft-float -mhard-float -mmultiple -mno-multiple @gol -msoft-float -mhard-float -mmultiple -mno-multiple @gol
-msingle-float -mdouble-float -msimple-fpu @gol
-mupdate -mno-update @gol -mupdate -mno-update @gol
-mavoid-indexed-addresses -mno-avoid-indexed-addresses @gol -mavoid-indexed-addresses -mno-avoid-indexed-addresses @gol
-mfused-madd -mno-fused-madd -mbit-align -mno-bit-align @gol -mfused-madd -mno-fused-madd -mbit-align -mno-bit-align @gol
...@@ -23340,8 +23339,8 @@ following options: ...@@ -23340,8 +23339,8 @@ following options:
@gccoptlist{-maltivec -mfprnd -mhard-float -mmfcrf -mmultiple @gol @gccoptlist{-maltivec -mfprnd -mhard-float -mmfcrf -mmultiple @gol
-mpopcntb -mpopcntd -mpowerpc64 @gol -mpopcntb -mpopcntd -mpowerpc64 @gol
-mpowerpc-gpopt -mpowerpc-gfxopt -msingle-float -mdouble-float @gol -mpowerpc-gpopt -mpowerpc-gfxopt @gol
-msimple-fpu -mmulhw -mdlmzb -mmfpgpr -mvsx @gol -mmulhw -mdlmzb -mmfpgpr -mvsx @gol
-mcrypto -mhtm -mpower8-fusion -mpower8-vector @gol -mcrypto -mhtm -mpower8-fusion -mpower8-vector @gol
-mquad-memory -mquad-memory-atomic -mfloat128 -mfloat128-hardware} -mquad-memory -mquad-memory-atomic -mfloat128 -mfloat128-hardware}
...@@ -23660,30 +23659,6 @@ Generate code that does not use (uses) the floating-point register set. ...@@ -23660,30 +23659,6 @@ Generate code that does not use (uses) the floating-point register set.
Software floating-point emulation is provided if you use the Software floating-point emulation is provided if you use the
@option{-msoft-float} option, and pass the option to GCC when linking. @option{-msoft-float} option, and pass the option to GCC when linking.
@item -msingle-float
@itemx -mdouble-float
@opindex msingle-float
@opindex mdouble-float
Generate code for single- or double-precision floating-point operations.
@option{-mdouble-float} implies @option{-msingle-float}.
@item -msimple-fpu
@opindex msimple-fpu
Do not generate @code{sqrt} and @code{div} instructions for hardware
floating-point unit.
@item -mfpu=@var{name}
@opindex mfpu
Specify type of floating-point unit. Valid values for @var{name} are
@samp{sp_lite} (equivalent to @option{-msingle-float -msimple-fpu}),
@samp{dp_lite} (equivalent to @option{-mdouble-float -msimple-fpu}),
@samp{sp_full} (equivalent to @option{-msingle-float}),
and @samp{dp_full} (equivalent to @option{-mdouble-float}).
@item -mxilinx-fpu
@opindex mxilinx-fpu
Perform optimizations for the floating-point unit on Xilinx PPC 405/440.
@item -mmultiple @item -mmultiple
@itemx -mno-multiple @itemx -mno-multiple
@opindex mmultiple @opindex mmultiple
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment