[AArch64] Fix atomic_cmp_exchange_zero_reg_1.c with +lse

	* config/aarch64/atomics.md (aarch64_compare_and_swap<mode>_lse,
	SHORT): Relax operand 3 to aarch64_reg_or_zero and constraint to Z.
	(aarch64_compare_and_swap<mode>_lse, GPI): Likewise.
	(aarch64_atomic_cas<mode>, SHORT): Likewise for operand 2.
	(aarch64_atomic_cas<mode>, GPI): Likewise.

From-SVN: r249457

gcc/ChangeLog

+2017-06-21  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+
+	* config/aarch64/atomics.md (aarch64_compare_and_swap<mode>_lse,
+	SHORT): Relax operand 3 to aarch64_reg_or_zero and constraint to Z.
+	(aarch64_compare_and_swap<mode>_lse, GPI): Likewise.
+	(aarch64_atomic_cas<mode>, SHORT): Likewise for operand 2.
+	(aarch64_atomic_cas<mode>, GPI): Likewise.
+
 2017-06-21  Martin Liska  <mliska@suse.cz>
 
 	* gimplify.c (gimplify_label_expr): Insert GIMPLE_PREDICT

gcc/config/aarch64/atomics.md

@@ -94,7 +94,7 @@
    (set (match_dup 1)
     (unspec_volatile:SHORT
       [(match_operand:SI 2 "aarch64_plus_operand" "rI")	;; expected
-       (match_operand:SHORT 3 "register_operand" "r")	;; desired
+       (match_operand:SHORT 3 "aarch64_reg_or_zero" "rZ")	;; desired
        (match_operand:SI 4 "const_int_operand")		;; is_weak
        (match_operand:SI 5 "const_int_operand")		;; mod_s
        (match_operand:SI 6 "const_int_operand")]	;; mod_f
@@ -119,7 +119,7 @@
    (set (match_dup 1)
     (unspec_volatile:GPI
       [(match_operand:GPI 2 "aarch64_plus_operand" "rI")	;; expect
-       (match_operand:GPI 3 "register_operand" "r")		;; desired
+       (match_operand:GPI 3 "aarch64_reg_or_zero" "rZ")		;; desired
        (match_operand:SI 4 "const_int_operand")			;; is_weak
        (match_operand:SI 5 "const_int_operand")			;; mod_s
        (match_operand:SI 6 "const_int_operand")]		;; mod_f
@@ -616,7 +616,7 @@
   (set (match_dup 1)
    (unspec_volatile:SHORT
     [(match_dup 0)
-     (match_operand:SHORT 2 "register_operand" "r")	;; value.
+     (match_operand:SHORT 2 "aarch64_reg_or_zero" "rZ")	;; value.
      (match_operand:SI 3 "const_int_operand" "")]	;; model.
     UNSPECV_ATOMIC_CAS))]
  "TARGET_LSE && reload_completed"
@@ -640,7 +640,7 @@
   (set (match_dup 1)
    (unspec_volatile:GPI
     [(match_dup 0)
-     (match_operand:GPI 2 "register_operand" "r")	;; value.
+     (match_operand:GPI 2 "aarch64_reg_or_zero" "rZ")	;; value.
      (match_operand:SI 3 "const_int_operand" "")]	;; model.
     UNSPECV_ATOMIC_CAS))]
   "TARGET_LSE && reload_completed"