[AArch64] PR rtl-optimization/68796: Add patterns for QImode and HImode comparison with zero

	PR rtl-optimization/68796
	* config/aarch64/aarch64.md (*and<mode>_compare0): New pattern.
	* config/aarch64/aarch64.c (aarch64_select_cc_mode): Handle HImode
	and QImode comparisons against zero with CC_NZmode.
	* config/aarch64/iterators.md (short_mask): New mode_attr.

	* gcc.target/aarch64/tst_5.c: New test.
	* gcc.target/aarch64/tst_6.c: Likewise.

From-SVN: r232228

gcc/ChangeLog

+2016-01-11  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+
+	PR rtl-optimization/68796
+	* config/aarch64/aarch64.md (*and<mode>_compare0): New pattern.
+	* config/aarch64/aarch64.c (aarch64_select_cc_mode): Handle HImode
+	and QImode comparisons against zero with CC_NZmode.
+	* config/aarch64/iterators.md (short_mask): New mode_attr.
+
 2016-01-11  H.J. Lu  <hongjiu.lu@intel.com>
 
 	* config/i386/sse.md (<avx512>_load<mode>_mask): Remove

gcc/config/aarch64/aarch64.c

@@ -4142,6 +4142,13 @@ aarch64_select_cc_mode (RTX_CODE code, rtx x, rtx y)
 	}
     }
 
+  /* Equality comparisons of short modes against zero can be performed
+     using the TST instruction with the appropriate bitmask.  */
+  if (y == const0_rtx && REG_P (x)
+      && (code == EQ || code == NE)
+      && (GET_MODE (x) == HImode || GET_MODE (x) == QImode))
+    return CC_NZmode;
+
   if ((GET_MODE (x) == SImode || GET_MODE (x) == DImode)
       && y == const0_rtx
       && (code == EQ || code == NE || code == LT || code == GE)

gcc/config/aarch64/aarch64.md

@@ -3672,6 +3672,16 @@
   }
 )
 
+(define_insn "*and<mode>_compare0"
+  [(set (reg:CC_NZ CC_REGNUM)
+	(compare:CC_NZ
+	 (match_operand:SHORT 0 "register_operand" "r")
+	 (const_int 0)))]
+  ""
+  "tst\\t%<w>0, <short_mask>"
+  [(set_attr "type" "alus_imm")]
+)
+
 (define_insn "*and<mode>3nr_compare0"
   [(set (reg:CC_NZ CC_REGNUM)
 	(compare:CC_NZ

gcc/config/aarch64/iterators.md

@@ -345,6 +345,8 @@
 (define_mode_attr w1 [(SF "w") (DF "x")])
 (define_mode_attr w2 [(SF "x") (DF "w")])
 
+(define_mode_attr short_mask [(HI "65535") (QI "255")])
+
 ;; For constraints used in scalar immediate vector moves
 (define_mode_attr hq [(HI "h") (QI "q")])
 

gcc/testsuite/ChangeLog

 2016-01-11  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
 
+	PR rtl-optimization/68796
+	* gcc.target/aarch64/tst_5.c: New test.
+	* gcc.target/aarch64/tst_6.c: Likewise.
+
+2016-01-11  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+
 	PR rtl-optimization/68841
 	* gcc.dg/pr68841.c: New test.
 	* gcc.c-torture/execute/pr68841.c: New test.

gcc/testsuite/gcc.target/aarch64/tst_5.c

+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+int
+f255 (int x)
+{
+  if (x & 255)
+    return 1;
+  return x;
+}
+
+int
+f65535 (int x)
+{
+  if (x & 65535)
+    return 1;
+  return x;
+}
+
+/* { dg-final { scan-assembler "tst\t(x|w)\[0-9\]+,\[ \t\]*255" } } */
+/* { dg-final { scan-assembler "tst\t(x|w)\[0-9\]+,\[ \t\]*65535" } } */

gcc/testsuite/gcc.target/aarch64/tst_6.c

+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+int
+foo (long x)
+{
+   return ((short) x != 0) ? x : 1;
+}
+
+/* { dg-final { scan-assembler "tst\t(x|w)\[0-9\]+,\[ \t\]*65535" } } */