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Commit 2aa3b677 by Andreas Schwab Committed by Andreas Schwab
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re PR rtl-optimization/54739 (FAIL: gcc.dg/lower-subreg-1.c scan-rtl-dump subreg1 "Splitting reg") 

PR rtl-optimization/54739
* config/m68k/m68k.md (anddi3, iordi3, xordi3, one_cmpldi2):
Remove.

From-SVN: r192156
parent 7d11d296
Showing with 6 additions and 226 deletions
gcc/ChangeLog
2012-10-06 Andreas Schwab <schwab@linux-m68k.org>
PR rtl-optimization/54739
* config/m68k/m68k.md (anddi3, iordi3, xordi3, one_cmpldi2):
Remove.
2012-10-06 Oleg Endo <olegendo@gcc.gnu.org> 2012-10-06 Oleg Endo <olegendo@gcc.gnu.org>
PR target/54760 PR target/54760
......
gcc/config/m68k/m68k.md
...@@ -3597,72 +3597,6 @@ ...@@ -3597,72 +3597,6 @@
;; logical-and instructions ;; logical-and instructions
;; "anddi3" is mainly here to help combine().
(define_insn "anddi3"
[(set (match_operand:DI 0 "nonimmediate_operand" "=o,d")
(and:DI (match_operand:DI 1 "general_operand" "%0,0")
(match_operand:DI 2 "general_operand" "dn,don")))]
"!TARGET_COLDFIRE"
{
CC_STATUS_INIT;
/* We can get CONST_DOUBLE, but also const1_rtx etc. */
if (CONSTANT_P (operands[2]))
{
rtx hi, lo;
split_double (operands[2], &hi, &lo);
switch (INTVAL (hi))
{
case 0 :
output_asm_insn ("clr%.l %0", operands);
break;
case -1 :
break;
default :
{
rtx xoperands[3];
xoperands[0] = operands[0];
xoperands[2] = hi;
output_asm_insn (output_andsi3 (xoperands), xoperands);
}
}
if (GET_CODE (operands[0]) == REG)
operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
else
operands[0] = adjust_address (operands[0], SImode, 4);
switch (INTVAL (lo))
{
case 0 :
output_asm_insn ("clr%.l %0", operands);
break;
case -1 :
break;
default :
{
rtx xoperands[3];
xoperands[0] = operands[0];
xoperands[2] = lo;
output_asm_insn (output_andsi3 (xoperands), xoperands);
}
}
return "";
}
if (GET_CODE (operands[0]) != REG)
{
operands[1] = adjust_address (operands[0], SImode, 4);
return "and%.l %2,%0\;and%.l %R2,%1";
}
if (GET_CODE (operands[2]) != REG)
{
operands[1] = adjust_address (operands[2], SImode, 4);
return "and%.l %2,%0\;and%.l %1,%R0";
}
return "and%.l %2,%0\;and%.l %R2,%R0";
})
;; Prevent AND from being made with sp. This doesn't exist in the machine ;; Prevent AND from being made with sp. This doesn't exist in the machine
;; and reload will cause inefficient code. Since sp is a FIXED_REG, we ;; and reload will cause inefficient code. Since sp is a FIXED_REG, we
;; can't allocate pseudos into it. ;; can't allocate pseudos into it.
...@@ -3780,76 +3714,6 @@ ...@@ -3780,76 +3714,6 @@
return "or%.w %1,%0"; return "or%.w %1,%0";
}) })
;; "iordi3" is mainly here to help combine().
(define_insn "iordi3"
[(set (match_operand:DI 0 "nonimmediate_operand" "=o,d")
(ior:DI (match_operand:DI 1 "general_operand" "%0,0")
(match_operand:DI 2 "general_operand" "dn,don")))]
"!TARGET_COLDFIRE"
{
CC_STATUS_INIT;
/* We can get CONST_DOUBLE, but also const1_rtx etc. */
if (CONSTANT_P (operands[2]))
{
rtx hi, lo;
split_double (operands[2], &hi, &lo);
switch (INTVAL (hi))
{
case 0 :
break;
case -1 :
/* FIXME : a scratch register would be welcome here if operand[0]
is not a register */
output_asm_insn ("move%.l #-1,%0", operands);
break;
default :
{
rtx xoperands[3];
xoperands[0] = operands[0];
xoperands[2] = hi;
output_asm_insn (output_iorsi3 (xoperands), xoperands);
}
}
if (GET_CODE (operands[0]) == REG)
operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
else
operands[0] = adjust_address (operands[0], SImode, 4);
switch (INTVAL (lo))
{
case 0 :
break;
case -1 :
/* FIXME : a scratch register would be welcome here if operand[0]
is not a register */
output_asm_insn ("move%.l #-1,%0", operands);
break;
default :
{
rtx xoperands[3];
xoperands[0] = operands[0];
xoperands[2] = lo;
output_asm_insn (output_iorsi3 (xoperands), xoperands);
}
}
return "";
}
if (GET_CODE (operands[0]) != REG)
{
operands[1] = adjust_address (operands[0], SImode, 4);
return "or%.l %2,%0\;or%.l %R2,%1";
}
if (GET_CODE (operands[2]) != REG)
{
operands[1] = adjust_address (operands[2], SImode, 4);
return "or%.l %2,%0\;or%.l %1,%R0";
}
return "or%.l %2,%0\;or%.l %R2,%R0";
})
(define_expand "iorsi3" (define_expand "iorsi3"
[(set (match_operand:SI 0 "nonimmediate_operand" "") [(set (match_operand:SI 0 "nonimmediate_operand" "")
(ior:SI (match_operand:SI 1 "general_operand" "") (ior:SI (match_operand:SI 1 "general_operand" "")
...@@ -3957,79 +3821,6 @@ ...@@ -3957,79 +3821,6 @@
;; xor instructions ;; xor instructions
;; "xordi3" is mainly here to help combine().
(define_insn "xordi3"
[(set (match_operand:DI 0 "nonimmediate_operand" "=od")
(xor:DI (match_operand:DI 1 "general_operand" "%0")
(match_operand:DI 2 "general_operand" "dn")))]
"!TARGET_COLDFIRE"
{
CC_STATUS_INIT;
/* We can get CONST_DOUBLE, but also const1_rtx etc. */
if (CONSTANT_P (operands[2]))
{
rtx hi, lo;
split_double (operands[2], &hi, &lo);
switch (INTVAL (hi))
{
case 0 :
break;
case -1 :
output_asm_insn ("not%.l %0", operands);
break;
default :
/* FIXME : a scratch register would be welcome here if
-128 <= INTVAL (hi) < -1 */
{
rtx xoperands[3];
xoperands[0] = operands[0];
xoperands[2] = hi;
output_asm_insn (output_xorsi3 (xoperands), xoperands);
}
}
if (GET_CODE (operands[0]) == REG)
operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
else
operands[0] = adjust_address (operands[0], SImode, 4);
switch (INTVAL (lo))
{
case 0 :
break;
case -1 :
output_asm_insn ("not%.l %0", operands);
break;
default :
/* FIXME : a scratch register would be welcome here if
-128 <= INTVAL (lo) < -1 */
operands[2] = lo;
/* FIXME : this should be merged with xorsi3 */
{
rtx xoperands[3];
xoperands[0] = operands[0];
xoperands[2] = lo;
output_asm_insn (output_xorsi3 (xoperands), xoperands);
}
}
return "";
}
if (GET_CODE (operands[0]) != REG)
{
operands[1] = adjust_address (operands[0], SImode, 4);
return "eor%.l %2,%0\;eor%.l %R2,%1";
}
if (GET_CODE (operands[2]) != REG)
{
operands[1] = adjust_address (operands[2], SImode, 4);
return "eor%.l %2,%0\;eor%.l %1,%R0";
}
return "eor%.l %2,%0\;eor%.l %R2,%R0";
})
(define_expand "xorsi3" (define_expand "xorsi3"
[(set (match_operand:SI 0 "nonimmediate_operand" "") [(set (match_operand:SI 0 "nonimmediate_operand" "")
(xor:SI (match_operand:SI 1 "general_operand" "") (xor:SI (match_operand:SI 1 "general_operand" "")
...@@ -4498,23 +4289,6 @@ ...@@ -4498,23 +4289,6 @@
;; one complement instructions ;; one complement instructions
;; "one_cmpldi2" is mainly here to help combine().
(define_insn "one_cmpldi2"
[(set (match_operand:DI 0 "nonimmediate_operand" "=dm")
(not:DI (match_operand:DI 1 "general_operand" "0")))]
"!TARGET_COLDFIRE"
{
CC_STATUS_INIT;
if (GET_CODE (operands[0]) == REG)
operands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
else if (GET_CODE (XEXP (operands[0], 0)) == POST_INC
|| GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
operands[1] = operands[0];
else
operands[1] = adjust_address (operands[0], SImode, 4);
return "not%.l %1\;not%.l %0";
})
(define_expand "one_cmplsi2" (define_expand "one_cmplsi2"
[(set (match_operand:SI 0 "nonimmediate_operand" "") [(set (match_operand:SI 0 "nonimmediate_operand" "")
(not:SI (match_operand:SI 1 "general_operand" "")))] (not:SI (match_operand:SI 1 "general_operand" "")))]
......
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