re PR bootstrap/6315 (sparc64 gcc -mhard-quad-float cannot compile libstdc++-v3)

	PR bootstrap/6315
	* config/sparc/sparc.md (movtf reg<-reg split): Allow spliting
	even if hard quad and register is not floating.
	(movtf reg<-mem split): Disallow splitting if hard quad and
	register is floating.
	(movtf mem<-reg split): Likewise.
	* config/sparc/sparc.c (fp_register_operand): New predicate.
	* config/sparc/sparc.h (PREDICATE_CODES): Add fp_register_operand.

	* gcc.dg/20020416-1.c: New test.

From-SVN: r52412

gcc/ChangeLog

+2002-04-17  Jakub Jelinek  <jakub@redhat.com>
+
+	PR bootstrap/6315
+	* config/sparc/sparc.md (movtf reg<-reg split): Allow spliting
+	even if hard quad and register is not floating.
+	(movtf reg<-mem split): Disallow splitting if hard quad and
+	register is floating.
+	(movtf mem<-reg split): Likewise.
+	* config/sparc/sparc.c (fp_register_operand): New predicate.
+	* config/sparc/sparc.h (PREDICATE_CODES): Add fp_register_operand.
+
 2002-04-17  Zack Weinberg  <zack@codesourcery.com>
 
 	* Makefile.in (PROTO_OBJS): Add cppdefault.o.

gcc/config/sparc/sparc.c

@@ -484,6 +484,20 @@ fp_zero_operand (op, mode)
   return op == CONST0_RTX (mode);
 }
 
+/* Nonzero if OP is a register operand in floating point register.  */
+
+int
+fp_register_operand (op, mode)
+     rtx op;
+     enum machine_mode mode;
+{
+  if (! register_operand (op, mode))
+    return 0;
+  if (GET_CODE (op) == SUBREG)
+    op = SUBREG_REG (op);
+  return GET_CODE (op) == REG && SPARC_FP_REG_P (REGNO (op));
+}
+
 /* Nonzero if OP is a floating point constant which can
    be loaded into an integer register using a single
    sethi instruction.  */

gcc/config/sparc/sparc.h

@@ -2947,6 +2947,7 @@ do {									\
 #define PREDICATE_CODES							\
 {"reg_or_0_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}},		\
 {"fp_zero_operand", {CONST_DOUBLE}},					\
+{"fp_register_operand", {SUBREG, REG}},					\
 {"intreg_operand", {SUBREG, REG}},					\
 {"fcc_reg_operand", {REG}},						\
 {"fcc0_reg_operand", {REG}},						\

gcc/config/sparc/sparc.md

@@ -3840,7 +3840,8 @@
   "reload_completed
    && (! TARGET_ARCH64
        || (TARGET_FPU
-           && ! TARGET_HARD_QUAD))"
+           && ! TARGET_HARD_QUAD)
+       || ! fp_register_operand (operands[0], TFmode))"
   [(clobber (const_int 0))]
   "
 {
@@ -3902,7 +3903,10 @@
   [(set (match_operand:TF 0 "register_operand" "")
         (match_operand:TF 1 "memory_operand" ""))]
   "(reload_completed
-    && offsettable_memref_p (operands[1]))"
+    && offsettable_memref_p (operands[1])
+    && (! TARGET_ARCH64
+	|| ! TARGET_HARD_QUAD
+	|| ! fp_register_operand (operands[0], TFmode)))"
   [(clobber (const_int 0))]
   "
 {
@@ -3935,7 +3939,10 @@
   [(set (match_operand:TF 0 "memory_operand" "")
 	(match_operand:TF 1 "register_operand" ""))]
   "(reload_completed
-    && offsettable_memref_p (operands[0]))"
+    && offsettable_memref_p (operands[0])
+    && (! TARGET_ARCH64
+	|| ! TARGET_HARD_QUAD
+	|| ! fp_register_operand (operands[1], TFmode)))"
   [(clobber (const_int 0))]
   "
 {

gcc/testsuite/ChangeLog

+2002-04-17  Jakub Jelinek  <jakub@redhat.com>
+
+	* gcc.dg/20020416-1.c: New test.
+
 2002-04-16  Jakub Jelinek  <jakub@redhat.com>
 
 	* gcc.dg/altivec-5.c: New test.

gcc/testsuite/gcc.dg/20020416-1.c

+/* PR bootstrap/6315 */
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+/* { dg-options "-O2 -mhard-quad-float" { target sparc*-*-* } } */
+/* { dg-options "-O2" { target sparclet*-*-* sparclite*-*-* sparc86x-*-* } } */
+
+void bar (const char *, ...);
+
+void
+foo (const char *x, long double y, int z)
+{
+  if (z >= 0)
+    bar (x, z, y);
+  else
+    bar (x, y);
+}