Add SImode to comparison operator, prevents ICE during combine

rtl pass with error message;

internal compiler error: in simplify_subreg, at simplify-rtx.c:5725

Use ordered_comparison_operator predicate to limit operators to
those fcmp can handle, and letting compiler reorder insns to
accomodate unordered as necessary

gcc/ChangeLog

2013-11-26  David Holsgrove <david.holsgrove@xilinx.com>

 * config/microblaze/microblaze.md(cstoresf4, cbranchsf4): Replace
   comparison_operator with ordered_comparison_operator.

testsuite/ChangeLog

2014-01-22  David holsgrove <david.holsgrove@xilinx.com>

 * testsuite/gcc.target/microblaze/isa/fcmp4.c: New file.

From-SVN: r207311

gcc/ChangeLog

+2014-01-30  David Holsgrove <david.holsgrove@xilinx.com>
+
+	* config/microblaze/microblaze.md(cstoresf4, cbranchsf4): Replace
+	comparison_operator with ordered_comparison_operator.
+
 2014-01-30  Nick Clifton  <nickc@redhat.com>
 
 	* config/mn10300/mn10300-protos.h (mn10300_store_multiple_operation_p):

gcc/config/microblaze/microblaze.md

@@ -1650,7 +1650,7 @@
 ;;----------------------------------------------------------------
 (define_insn "cstoresf4"
    [(set (match_operand:SI 0 "register_operand" "=r")
-        (match_operator 1 "comparison_operator"
+        (match_operator:SI 1 "ordered_comparison_operator"
 	      [(match_operand:SF 2 "register_operand" "r")
 	       (match_operand:SF 3 "register_operand" "r")]))]
   "TARGET_HARD_FLOAT"
@@ -1679,7 +1679,7 @@
 
 (define_expand "cbranchsf4"
   [(set (pc)
-	(if_then_else (match_operator 0 "comparison_operator"
+	(if_then_else (match_operator 0 "ordered_comparison_operator"
 		       [(match_operand:SF 1 "register_operand")
 		        (match_operand:SF 2 "register_operand")])
 		      (label_ref (match_operand 3 ""))

gcc/testsuite/ChangeLog

+2014-01-30  David Holsgrove <david.holsgrove@xilinx.com>
+
+	* gcc.target/microblaze/isa/fcmp4.c: New.
+
 2014-01-30  Marek Polacek  <polacek@redhat.com>
 
 	PR c/59940

gcc/testsuite/gcc.target/microblaze/isa/fcmp4.c

+/* { dg-options "-O3 -mcpu=v6.00.a -mhard-float" } */
+
+void float_func(float f1, float f2, float f3)
+{
+  /* { dg-final { scan-assembler "fcmp\.eq\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1])\[^0-9]" } } */
+  /* { dg-final { scan-assembler "fcmp\.le\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1])\[^0-9]" } } */
+    if(f1==f2 && f1<=f3)
+        print ("f1 eq f2 && f1 le f3");
+}