mn10300.opt (mliw): New command line option.

	* config/mn10300/mn10300.opt (mliw): New command line option.
	* config/mn10300/mn10300.md (UNSPEC_LIW): New unspec.
	(liw_bundling): New automaton.
	(liw): New attribute.
	(liw_op): New attribute.
	(liw_op1, liw_op2, liw_both, liw_either): New reservations.
	(movsi_internal): Add LIW attributes.
	(andsi3): Likewise.
	(iorsi3): Likewise.
	(xorsi3): Likewise.
	(addsi3): Separate register and immediate alternatives.
	Add LIW attributes.
	(subsi3): Likewise.
	(cmpsi): Likewise.
	(aslsi3): Likewise.
	(lshrsi3): Likewise.
	(ashrsi3): Likewise.
	(liw): New pattern.
	* config/mn10300/mn10300.c (liw_op_names): New
	(mn10300_print_operand): Handle 'W' operand descriptor.
	(extract_bundle): New function.
	(check_liw_constraints): New function.
	(liw_candidate): New function.
	(mn10300_bundle_liw): New function.
	(mn10300_reorg): New function.
	(TARGET_MACHINE_DEPENDENT_REORG): Define.
	(TARGET_DEFAULT_TARGET_FLAGS): Add MASK_ALLOW_LIW.
	* config/mn10300/mn10300.h (TARGET_CPU_CPP_BUILTINS): Define
	__LIW__ or __NO_LIW__.
	* doc/invoke.texi: Describe the -mliw command line option.

From-SVN: r169916

gcc/ChangeLog

+2011-02-08  Nick Clifton  <nickc@redhat.com>
+
+	* config/mn10300/mn10300.opt (mliw): New command line option.
+	* config/mn10300/mn10300.md (UNSPEC_LIW): New unspec.
+	(liw_bundling): New automaton.
+	(liw): New attribute.
+	(liw_op): New attribute.
+	(liw_op1, liw_op2, liw_both, liw_either): New reservations.
+	(movsi_internal): Add LIW attributes.
+	(andsi3): Likewise.
+	(iorsi3): Likewise.
+	(xorsi3): Likewise.
+	(addsi3): Separate register and immediate alternatives.
+	Add LIW attributes.
+	(subsi3): Likewise.
+	(cmpsi): Likewise.
+	(aslsi3): Likewise.
+	(lshrsi3): Likewise.
+	(ashrsi3): Likewise.
+	(liw): New pattern.
+	* config/mn10300/mn10300.c (liw_op_names): New
+	(mn10300_print_operand): Handle 'W' operand descriptor.
+	(extract_bundle): New function.
+	(check_liw_constraints): New function.
+	(liw_candidate): New function.
+	(mn10300_bundle_liw): New function.
+	(mn10300_reorg): New function.
+	(TARGET_MACHINE_DEPENDENT_REORG): Define.
+	(TARGET_DEFAULT_TARGET_FLAGS): Add MASK_ALLOW_LIW.
+	* config/mn10300/mn10300.h (TARGET_CPU_CPP_BUILTINS): Define
+	__LIW__ or __NO_LIW__.
+	* doc/invoke.texi: Describe the -mliw command line option.
+
 2011-02-07  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 
 	* config.gcc (hppa[12]*-*-hpux11*): Don't set extra_parts.

gcc/config/mn10300/mn10300.h

@@ -50,6 +50,10 @@
         }					\
       else if (TARGET_AM33)			\
         builtin_define ("__AM33__=1");		\
+						\
+      builtin_define (TARGET_ALLOW_LIW ?	\
+		      "__LIW__" : "__NO_LIW__");\
+						\
     }						\
   while (0)
 

gcc/config/mn10300/mn10300.md

 ;; GCC machine description for Matsushita MN10300
 ;; Copyright (C) 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004,
-;; 2005, 2006, 2007, 2008, 2009, 2010
+;; 2005, 2006, 2007, 2008, 2009, 2010, 2011
 ;; Free Software Foundation, Inc.
 ;; Contributed by Jeff Law (law@cygnus.com).
 
@@ -39,6 +39,9 @@
 
   (UNSPEC_EXT		6)
   (UNSPEC_BSCH		7)
+
+  ;; This is used to encode LIW patterns.
+  (UNSPEC_LIW		8)
 ])
 
 (include "predicates.md")
@@ -75,6 +78,43 @@
 (define_mode_iterator INT [QI HI SI])
 
 
+;; Bundling of smaller insns into a long instruction word (LIW)
+(define_automaton "liw_bundling")
+(automata_option "ndfa")
+
+(define_cpu_unit "liw_op1_u,liw_op2_u" "liw_bundling")
+
+(define_attr "liw" "op1,op2,both,either"
+  (const_string "both"))
+;; Note: this list must match the one defined for liw_op_names[].
+(define_attr "liw_op" "add,cmp,sub,mov,and,or,xor,asr,lsr,asl,none,max"
+  (const_string "none"))
+
+(define_insn_reservation "liw_op1" 1
+  (and (ior (eq_attr "cpu" "am33")
+            (eq_attr "cpu" "am33_2")
+	    (eq_attr "cpu" "am34"))
+       (eq_attr "liw" "op1"))
+  "liw_op1_u");
+(define_insn_reservation "liw_op2" 1
+  (and (ior (eq_attr "cpu" "am33")
+            (eq_attr "cpu" "am33_2")
+	    (eq_attr "cpu" "am34"))
+       (eq_attr "liw" "op2"))
+  "liw_op2_u");
+(define_insn_reservation "liw_both" 1
+  (and (ior (eq_attr "cpu" "am33")
+            (eq_attr "cpu" "am33_2")
+	    (eq_attr "cpu" "am34"))
+       (eq_attr "liw" "both"))
+  "liw_op1_u + liw_op2_u");
+(define_insn_reservation "liw_either" 1
+  (and (ior (eq_attr "cpu" "am33")
+            (eq_attr "cpu" "am33_2")
+	    (eq_attr "cpu" "am34"))
+       (eq_attr "liw" "either"))
+  "liw_op1_u | liw_op2_u");
+
 ;; ----------------------------------------------------------------------
 ;; Pipeline description.
 ;; ----------------------------------------------------------------------
@@ -417,6 +457,8 @@
     }
 }
   [(set_attr "isa" "*,*,*,*,*,*,*,am33,*,*")
+   (set_attr "liw" "*,*,either,*,*,*,*,*,*,*")
+   (set_attr "liw_op" "mov")
    (set_attr_alternative "timings"
 	 [(const_int 11)
 	  (const_int 22)
@@ -521,13 +563,15 @@
 ;; ----------------------------------------------------------------------
 
 (define_insn "addsi3"
-  [(set (match_operand:SI          0 "register_operand"  "=r,!*y,!r")
-	(plus:SI (match_operand:SI 1 "register_operand"  "%0,  0, r")
-		 (match_operand:SI 2 "nonmemory_operand" "ri,  i, r")))
+  [(set (match_operand:SI          0 "register_operand"  "=r,r,!*y,!r")
+	(plus:SI (match_operand:SI 1 "register_operand"  "%0,0,  0, r")
+		 (match_operand:SI 2 "nonmemory_operand"  "r,i,  i, r")))
    (clobber (reg:CC CC_REG))]
   ""
   { return mn10300_output_add (operands, false); }
-  [(set_attr "timings" "11,11,22")]
+  [(set_attr "timings" "11,11,11,22")
+   (set_attr "liw" "either,*,*,*")
+   (set_attr "liw_op" "add")]
 )
 
 ;; Note that ADD IMM,SP does not set the flags, so omit that here.
@@ -714,22 +758,25 @@
 ;; ----------------------------------------------------------------------
 
 (define_insn "subsi3"
-  [(set (match_operand:SI           0 "register_operand"  "=r,r")
-	(minus:SI (match_operand:SI 1 "register_operand"  " 0,r")
-		  (match_operand:SI 2 "nonmemory_operand" "ri,r")))
+  [(set (match_operand:SI           0 "register_operand"  "=r,r,r")
+	(minus:SI (match_operand:SI 1 "register_operand"   "0,0,r")
+		  (match_operand:SI 2 "nonmemory_operand"  "r,i,r")))
    (clobber (reg:CC CC_REG))]
   ""
   "@
    sub %2,%0
+   sub %2,%0
    sub %2,%1,%0"
-  [(set_attr "isa" "*,am33")
-   (set_attr "timings" "11,22")]
+  [(set_attr "isa" "*,*,am33")
+   (set_attr "liw" "either,*,*")
+   (set_attr "liw_op" "sub")
+   (set_attr "timings" "11,11,22")]
 )
 
 (define_insn "*subsi3_flags"
-  [(set (match_operand:SI           0 "register_operand"  "=r,r")
-	(minus:SI (match_operand:SI 1 "register_operand"  " 0,r")
-		  (match_operand:SI 2 "nonmemory_operand" "ri,r")))
+  [(set (match_operand:SI           0 "register_operand"  "=r, r")
+	(minus:SI (match_operand:SI 1 "register_operand"   "0, r")
+		  (match_operand:SI 2 "nonmemory_operand"  "ri,r")))
    (set (reg CC_REG)
    	(compare (minus:SI (match_dup 1) (match_dup 2))
 		 (const_int 0)))]
@@ -1125,6 +1172,8 @@
    and %2,%0
    and %2,%1,%0"
   [(set_attr "isa" "*,*,am33")
+   (set_attr "liw" "*,op1,*")
+   (set_attr "liw_op" "and")
    (set_attr "timings" "22,11,11")]
 )
 
@@ -1210,6 +1259,8 @@
    or %2,%0
    or %2,%1,%0"
   [(set_attr "isa" "*,*,am33")
+   (set_attr "liw" "*,op1,*")
+   (set_attr "liw_op" "or")
    (set_attr "timings" "22,11,11")]
 )
 
@@ -1244,6 +1295,8 @@
    xor %2,%0
    xor %2,%1,%0"
   [(set_attr "isa" "*,*,am33")
+   (set_attr "liw" "*,op1,*")
+   (set_attr "liw_op" "xor")
    (set_attr "timings" "22,11,11")]
 )
 
@@ -1321,8 +1374,8 @@
 
 (define_insn "*cmpsi"
   [(set (reg CC_REG)
-	(compare (match_operand:SI 0 "register_operand"  "r")
-		 (match_operand:SI 1 "nonmemory_operand" "ri")))]
+	(compare (match_operand:SI 0 "register_operand"  "r,r")
+		 (match_operand:SI 1 "nonmemory_operand" "r,i")))]
   "reload_completed"
 {
   /* The operands of CMP must be distinct registers.  In the case where
@@ -1336,7 +1389,10 @@
     return "cmp %1,%0";
 }
   [(set_attr_alternative "timings"
-     [(if_then_else (eq_attr "cpu" "am34") (const_int 11) (const_int 22))])]
+     [(if_then_else (eq_attr "cpu" "am34") (const_int 11) (const_int 22))
+      (if_then_else (eq_attr "cpu" "am34") (const_int 11) (const_int 22))])
+   (set_attr "liw" "either,*")
+   (set_attr "liw_op" "cmp")]
 )
 
 (define_insn "*integer_conditional_branch"
@@ -1676,10 +1732,10 @@
 ;; ----------------------------------------------------------------------
 
 (define_insn "ashlsi3"
-  [(set (match_operand:SI  0 "register_operand"  "=r,D,d,d, D,r")
+  [(set (match_operand:SI  0 "register_operand"   "=r,D,d,d,D,D,r")
 	(ashift:SI
-	  (match_operand:SI 1 "register_operand"  " 0,0,0,0, 0,r")
-	  (match_operand:QI 2 "nonmemory_operand" " J,K,M,L,Di,r")))
+	  (match_operand:SI 1 "register_operand"  " 0,0,0,0,0,0,r")
+	  (match_operand:QI 2 "nonmemory_operand" " J,K,M,L,D,i,r")))
    (clobber (reg:CC CC_REG))]
   ""
   "@
@@ -1688,35 +1744,44 @@
    asl2 %0\;add %0,%0
    asl2 %0\;asl2 %0
    asl %S2,%0
+   asl %S2,%0
    asl %2,%1,%0"
-  [(set_attr "isa" "*,*,*,*,*,am33")
-   (set_attr "timings" "11,11,22,22,11,11")]
+  [(set_attr "isa" "*,*,*,*,*,*,am33")
+   (set_attr "liw" "*,*,*,*,op2,*,*")
+   (set_attr "liw_op" "asl")
+   (set_attr "timings" "11,11,22,22,11,11,11")]
 )
 
 (define_insn "lshrsi3"
-  [(set (match_operand:SI  0 "register_operand"  "=D,r")
+  [(set (match_operand:SI  0 "register_operand"  "=D,D,r")
 	(lshiftrt:SI
-	  (match_operand:SI 1 "register_operand"  " 0,r")
-	  (match_operand:QI 2 "nonmemory_operand" "Di,r")))
+	  (match_operand:SI 1 "register_operand"  "0,0,r")
+	  (match_operand:QI 2 "nonmemory_operand" "D,i,r")))
    (clobber (reg:CC CC_REG))]
   ""
   "@
    lsr %S2,%0
+   lsr %S2,%0
    lsr %2,%1,%0"
-  [(set_attr "isa" "*,am33")]
+  [(set_attr "isa" "*,*,am33")
+   (set_attr "liw" "op2,*,*")
+   (set_attr "liw_op" "lsr")]
 )
 
 (define_insn "ashrsi3"
-  [(set (match_operand:SI  0 "register_operand"  "=D,r")
+  [(set (match_operand:SI  0 "register_operand"  "=D,D,r")
 	(ashiftrt:SI
-	  (match_operand:SI 1 "register_operand"  " 0,r")
-	  (match_operand:QI 2 "nonmemory_operand" "Di,r")))
+	  (match_operand:SI 1 "register_operand"  "0,0,r")
+	  (match_operand:QI 2 "nonmemory_operand" "D,i,r")))
    (clobber (reg:CC CC_REG))]
   ""
   "@
    asr %S2,%0
+   asr %S2,%0
    asr %2,%1,%0"
-  [(set_attr "isa" "*,am33")]
+  [(set_attr "isa" "*,*,am33")
+   (set_attr "liw" "op2,*,*")
+   (set_attr "liw_op" "asr")]
 )
 
 ;; ----------------------------------------------------------------------
@@ -2029,3 +2094,54 @@
 }
   [(set_attr "timings" "66")]
 )
+
+;; The mode on operand 3 has been deliberately omitted because it
+;; can be either SI (for arithmetic operations) or QI (for shifts).
+(define_insn "liw"
+  [(set (match_operand:SI             0 "register_operand" "=r")
+	(unspec:SI [(match_dup 0)
+                    (match_operand:SI 2 "register_operand" "r")
+                    (match_operand:SI 4 "const_int_operand" "")]
+                   UNSPEC_LIW))
+   (set (match_operand:SI             1 "register_operand" "=r")
+        (unspec:SI [(match_dup 1)
+                    (match_operand    3 "register_operand" "r")
+                    (match_operand:SI 5 "const_int_operand" "")]
+                   UNSPEC_LIW))]
+  "TARGET_ALLOW_LIW"
+  "%W4_%W5 %2, %0, %3, %1"
+  [(set (attr "timings") (if_then_else (eq_attr "cpu" "am34")
+				       (const_int 13) (const_int 12)))]
+)
+
+;; The mode on operand 1 has been deliberately omitted because it
+;; can be either SI (for arithmetic operations) or QI (for shifts).
+(define_insn "cmp_liw"
+  [(set (reg:CC CC_REG)
+	(compare:CC (match_operand:SI 2 "register_operand" "r")
+		    (match_operand:SI 3 "register_operand" "r")))
+   (set (match_operand:SI             0 "register_operand" "=r")
+        (unspec:SI [(match_dup 0)
+                    (match_operand    1 "register_operand" "r")
+                    (match_operand:SI 4 "const_int_operand" "")]
+                   UNSPEC_LIW))]
+  "TARGET_ALLOW_LIW"
+  "cmp_%W4 %2, %3, %0, %1"
+  [(set (attr "timings") (if_then_else (eq_attr "cpu" "am34")
+				       (const_int 13) (const_int 12)))]
+)
+
+(define_insn "liw_cmp"
+  [(set (match_operand:SI             0 "register_operand" "=r")
+        (unspec:SI [(match_dup 0)
+                    (match_operand:SI 1 "register_operand" "r")
+                    (match_operand:SI 4 "const_int_operand" "")]
+                   UNSPEC_LIW))
+   (set (reg:CC CC_REG)
+	(compare:CC (match_operand:SI 2 "register_operand" "r")
+		    (match_operand:SI 3 "register_operand" "r")))]
+  "TARGET_ALLOW_LIW"
+  "%W4_cmp %0, %1, %2, %3"
+  [(set (attr "timings") (if_then_else (eq_attr "cpu" "am34")
+				       (const_int 13) (const_int 12)))]
+)

gcc/config/mn10300/mn10300.opt

 ; Options for the Matsushita MN10300 port of the compiler.
 
-; Copyright (C) 2005, 2007, 2010 Free Software Foundation, Inc.
+; Copyright (C) 2005, 2007, 2010, 2011 Free Software Foundation, Inc.
 ;
 ; This file is part of GCC.
 ;
@@ -46,3 +46,7 @@ Enable linker relaxations
 mreturn-pointer-on-d0
 Target Report Mask(PTR_A0D0)
 Return pointers in both a0 and d0
+
+mliw
+Target Report Mask(ALLOW_LIW)
+Allow gcc to generate LIW instructions

gcc/doc/invoke.texi

@@ -739,7 +739,7 @@ Objective-C and Objective-C++ Dialects}.
 -mno-am33 -mam33 -mam33-2 -mam34 @gol
 -mtune=@var{cpu-type} @gol
 -mreturn-pointer-on-d0 @gol
--mno-crt0  -mrelax}
+-mno-crt0  -mrelax -mliw}
 
 @emph{PDP-11 Options}
 @gccoptlist{-mfpu  -msoft-float  -mac0  -mno-ac0  -m40  -m45  -m10 @gol
@@ -15035,6 +15035,19 @@ to shorten branches, calls and absolute memory addresses.  This option only
 has an effect when used on the command line for the final link step.
 
 This option makes symbolic debugging impossible.
+
+@item -mliw
+@opindex mliw
+Allow the compiler to generate @emph{Long Instruction Word}
+instructions if the target is the @samp{AM33} or later.  This is the
+default.  This option defines the preprocessor macro @samp{__LIW__}.
+
+@item -mnoliw
+@opindex mnoliw
+Do not allow the compiler to generate @emph{Long Instruction Word}
+instructions.  This option defines the preprocessor macro
+@samp{__NO_LIW__}.
+
 @end table
 
 @node PDP-11 Options