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riscv-gcc-1
Commit 292b89b3 by James Greenhalgh Committed by James Greenhalgh
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[AArch64, ARM] Rename the FCPYS type to FMOV 

gcc/
	* config/arm/types.md (type): Rename fcpys to fmov.
	* config/arm/vfp.md
	(*arm_movsi_vfp): Rename type fcpys as fmov.
	(*thumb2_movsi_vfp): Likewise
	(*movhf_vfp_neon): Likewise
	(*movhf_vfp): Likewise
	(*movsf_vfp): Likewise
	(*thumb2_movsf_vfp): Likewise
	(*movsfcc_vfp): Likewise
	(*thumb2_movsfcc_vfp): Likewise
	* config/aarch64/aarch64-simd.md
	(move_lo_quad_<mode>): Replace type mov_reg with fmovs.
	* config/aarch64/aarch64.md
	(*movsi_aarch64): Replace type mov_reg with fmovs.
	(*movdi_aarch64): Likewise
	(*movsf_aarch64): Likewise
	(*movdf_aarch64): Likewise
	* config/arm/arm.c
	(cortexa7_older_only): Rename TYPE_FCPYS to TYPE_FMOV.
	* config/arm/iwmmxt.md
	(*iwmmxt_movsi_insn): Rename type fcpys as fmov.
	* config/arm/arm1020e.md: Update with new attributes.
	* config/arm/cortex-a15-neon.md: Update with new attributes.
	* config/arm/cortex-a5.md: Update with new attributes.
	* config/arm/cortex-a53.md: Update with new attributes.
	* config/arm/cortex-a7.md: Update with new attributes.
	* config/arm/cortex-a8-neon.md: Update with new attributes.
	* config/arm/cortex-a9.md: Update with new attributes.
	* config/arm/cortex-m4-fpu.md: Update with new attributes.
	* config/arm/cortex-r4f.md: Update with new attributes.
	* config/arm/marvell-pj4.md: Update with new attributes.
	* config/arm/vfp11.md: Update with new attributes.

From-SVN: r202331
parent 6a24a83e
Showing with 65 additions and 30 deletions
gcc/ChangeLog
2013-09-06 James Greenhalgh <james.greenhalgh@arm.com> 2013-09-06 James Greenhalgh <james.greenhalgh@arm.com>
* config/arm/types.md (type): Rename fcpys to fmov.
* config/arm/vfp.md
(*arm_movsi_vfp): Rename type fcpys as fmov.
(*thumb2_movsi_vfp): Likewise
(*movhf_vfp_neon): Likewise
(*movhf_vfp): Likewise
(*movsf_vfp): Likewise
(*thumb2_movsf_vfp): Likewise
(*movsfcc_vfp): Likewise
(*thumb2_movsfcc_vfp): Likewise
* config/aarch64/aarch64-simd.md
(move_lo_quad_<mode>): Replace type mov_reg with fmovs.
* config/aarch64/aarch64.md
(*movsi_aarch64): Replace type mov_reg with fmovs.
(*movdi_aarch64): Likewise
(*movsf_aarch64): Likewise
(*movdf_aarch64): Likewise
* config/arm/arm.c
(cortexa7_older_only): Rename TYPE_FCPYS to TYPE_FMOV.
* config/arm/iwmmxt.md
(*iwmmxt_movsi_insn): Rename type fcpys as fmov.
* config/arm/arm1020e.md: Update with new attributes.
* config/arm/cortex-a15-neon.md: Update with new attributes.
* config/arm/cortex-a5.md: Update with new attributes.
* config/arm/cortex-a53.md: Update with new attributes.
* config/arm/cortex-a7.md: Update with new attributes.
* config/arm/cortex-a8-neon.md: Update with new attributes.
* config/arm/cortex-a9.md: Update with new attributes.
* config/arm/cortex-m4-fpu.md: Update with new attributes.
* config/arm/cortex-r4f.md: Update with new attributes.
* config/arm/marvell-pj4.md: Update with new attributes.
* config/arm/vfp11.md: Update with new attributes.
2013-09-06 James Greenhalgh <james.greenhalgh@arm.com>
* config/aarch64/aarch64.md * config/aarch64/aarch64.md
(*madd<mode>): Fix type attribute. (*madd<mode>): Fix type attribute.
(*maddsi_uxtw): Likewise. (*maddsi_uxtw): Likewise.
......
gcc/config/aarch64/aarch64-simd.md
...@@ -1052,7 +1052,7 @@ ...@@ -1052,7 +1052,7 @@
fmov\\t%d0, %1 fmov\\t%d0, %1
dup\\t%d0, %1" dup\\t%d0, %1"
[(set_attr "v8type" "*,fmov,*") [(set_attr "v8type" "*,fmov,*")
(set_attr "type" "*,mov_reg,*") (set_attr "type" "*,fmov,*")
(set_attr "simd_type" "simd_dup,*,simd_dup") (set_attr "simd_type" "simd_dup,*,simd_dup")
(set_attr "simd_mode" "<MODE>") (set_attr "simd_mode" "<MODE>")
(set_attr "simd" "yes,*,yes") (set_attr "simd" "yes,*,yes")
......
gcc/config/aarch64/aarch64.md
...@@ -831,7 +831,7 @@ ...@@ -831,7 +831,7 @@
fmov\\t%s0, %s1" fmov\\t%s0, %s1"
[(set_attr "v8type" "move,move,move,alu,load1,load1,store1,store1,adr,adr,fmov,fmov,fmov") [(set_attr "v8type" "move,move,move,alu,load1,load1,store1,store1,adr,adr,fmov,fmov,fmov")
(set_attr "type" "mov_reg,mov_reg,mov_reg,mov_imm,load1,load1,store1,store1,\ (set_attr "type" "mov_reg,mov_reg,mov_reg,mov_imm,load1,load1,store1,store1,\
adr,adr,mov_reg,mov_reg,mov_reg") adr,adr,fmov,fmov,fmov")
(set_attr "mode" "SI") (set_attr "mode" "SI")
(set_attr "fp" "*,*,*,*,*,yes,*,yes,*,*,yes,yes,yes")] (set_attr "fp" "*,*,*,*,*,yes,*,yes,*,*,yes,yes,yes")]
) )
...@@ -858,7 +858,7 @@ ...@@ -858,7 +858,7 @@
movi\\t%d0, %1" movi\\t%d0, %1"
[(set_attr "v8type" "move,move,move,alu,load1,load1,store1,store1,adr,adr,fmov,fmov,fmov,fmov") [(set_attr "v8type" "move,move,move,alu,load1,load1,store1,store1,adr,adr,fmov,fmov,fmov,fmov")
(set_attr "type" "mov_reg,mov_reg,mov_reg,mov_imm,load1,load1,store1,store1,\ (set_attr "type" "mov_reg,mov_reg,mov_reg,mov_imm,load1,load1,store1,store1,\
adr,adr,mov_reg,mov_reg,mov_reg,mov_reg") adr,adr,fmov,fmov,fmov,fmov")
(set_attr "mode" "DI") (set_attr "mode" "DI")
(set_attr "fp" "*,*,*,*,*,yes,*,yes,*,*,yes,yes,yes,*") (set_attr "fp" "*,*,*,*,*,yes,*,yes,*,*,yes,yes,yes,*")
(set_attr "simd" "*,*,*,*,*,*,*,*,*,*,*,*,*,yes")] (set_attr "simd" "*,*,*,*,*,*,*,*,*,*,*,*,*,yes")]
...@@ -961,8 +961,8 @@ ...@@ -961,8 +961,8 @@
[(set_attr "v8type" "fmovi2f,fmovf2i,\ [(set_attr "v8type" "fmovi2f,fmovf2i,\
fmov,fconst,fpsimd_load,\ fmov,fconst,fpsimd_load,\
fpsimd_store,fpsimd_load,fpsimd_store,fmov") fpsimd_store,fpsimd_load,fpsimd_store,fmov")
(set_attr "type" "f_mcr,f_mrc,mov_reg,fconsts,\ (set_attr "type" "f_mcr,f_mrc,fmov,fconsts,\
f_loads,f_stores,f_loads,f_stores,mov_reg") f_loads,f_stores,f_loads,f_stores,fmov")
(set_attr "mode" "SF")] (set_attr "mode" "SF")]
) )
...@@ -984,7 +984,7 @@ ...@@ -984,7 +984,7 @@
[(set_attr "v8type" "fmovi2f,fmovf2i,\ [(set_attr "v8type" "fmovi2f,fmovf2i,\
fmov,fconst,fpsimd_load,\ fmov,fconst,fpsimd_load,\
fpsimd_store,fpsimd_load,fpsimd_store,move") fpsimd_store,fpsimd_load,fpsimd_store,move")
(set_attr "type" "f_mcr,f_mrc,mov_reg,fconstd,\ (set_attr "type" "f_mcr,f_mrc,fmov,fconstd,\
f_loadd,f_stored,f_loadd,f_stored,mov_reg") f_loadd,f_stored,f_loadd,f_stored,mov_reg")
(set_attr "mode" "DF")] (set_attr "mode" "DF")]
) )
......
gcc/config/arm/arm.c
...@@ -8977,7 +8977,7 @@ cortexa7_older_only (rtx insn) ...@@ -8977,7 +8977,7 @@ cortexa7_older_only (rtx insn)
case TYPE_FADDS: case TYPE_FADDS:
case TYPE_FFARITHD: case TYPE_FFARITHD:
case TYPE_FADDD: case TYPE_FADDD:
case TYPE_FCPYS: case TYPE_FMOV:
case TYPE_F_CVT: case TYPE_F_CVT:
case TYPE_FCMPS: case TYPE_FCMPS:
case TYPE_FCMPD: case TYPE_FCMPD:
......
gcc/config/arm/arm1020e.md
...@@ -279,7 +279,7 @@ ...@@ -279,7 +279,7 @@
;; first execute state. We model this by using 1020a_e in the first cycle. ;; first execute state. We model this by using 1020a_e in the first cycle.
(define_insn_reservation "v10_ffarith" 5 (define_insn_reservation "v10_ffarith" 5
(and (eq_attr "vfp10" "yes") (and (eq_attr "vfp10" "yes")
(eq_attr "type" "fcpys,ffariths,ffarithd,fcmps,fcmpd")) (eq_attr "type" "fmov,ffariths,ffarithd,fcmps,fcmpd"))
"1020a_e+v10_fmac") "1020a_e+v10_fmac")
(define_insn_reservation "v10_farith" 5 (define_insn_reservation "v10_farith" 5
......
gcc/config/arm/cortex-a15-neon.md
...@@ -491,7 +491,7 @@ ...@@ -491,7 +491,7 @@
(define_insn_reservation "cortex_a15_vfp_cpys" 4 (define_insn_reservation "cortex_a15_vfp_cpys" 4
(and (eq_attr "tune" "cortexa15") (and (eq_attr "tune" "cortexa15")
(eq_attr "type" "fcpys")) (eq_attr "type" "fmov"))
"ca15_issue1,ca15_cx_perm") "ca15_issue1,ca15_cx_perm")
(define_insn_reservation "cortex_a15_vfp_ariths" 7 (define_insn_reservation "cortex_a15_vfp_ariths" 7
......
gcc/config/arm/cortex-a5.md
...@@ -168,7 +168,7 @@ ...@@ -168,7 +168,7 @@
(define_insn_reservation "cortex_a5_fpalu" 4 (define_insn_reservation "cortex_a5_fpalu" 4
(and (eq_attr "tune" "cortexa5") (and (eq_attr "tune" "cortexa5")
(eq_attr "type" "ffariths, fadds, ffarithd, faddd, fcpys, fmuls,\ (eq_attr "type" "ffariths, fadds, ffarithd, faddd, fmov, fmuls,\
f_cvt,f_cvtf2i,f_cvti2f,\ f_cvt,f_cvtf2i,f_cvti2f,\
fcmps, fcmpd")) fcmps, fcmpd"))
"cortex_a5_ex1+cortex_a5_fpadd_pipe") "cortex_a5_ex1+cortex_a5_fpadd_pipe")
......
gcc/config/arm/cortex-a53.md
...@@ -209,7 +209,7 @@ ...@@ -209,7 +209,7 @@
(define_insn_reservation "cortex_a53_fpalu" 4 (define_insn_reservation "cortex_a53_fpalu" 4
(and (eq_attr "tune" "cortexa53") (and (eq_attr "tune" "cortexa53")
(eq_attr "type" "ffariths, fadds, ffarithd, faddd, fcpys, fmuls,\ (eq_attr "type" "ffariths, fadds, ffarithd, faddd, fmov, fmuls,\
f_cvt,f_cvtf2i,f_cvti2f,\ f_cvt,f_cvtf2i,f_cvti2f,\
fcmps, fcmpd, fcsel")) fcmps, fcmpd, fcsel"))
"cortex_a53_slot0+cortex_a53_fpadd_pipe") "cortex_a53_slot0+cortex_a53_fpadd_pipe")
......
gcc/config/arm/cortex-a7.md
...@@ -204,7 +204,7 @@ ...@@ -204,7 +204,7 @@
(define_insn_reservation "cortex_a7_fpalu" 4 (define_insn_reservation "cortex_a7_fpalu" 4
(and (eq_attr "tune" "cortexa7") (and (eq_attr "tune" "cortexa7")
(eq_attr "type" "ffariths, fadds, ffarithd, faddd, fcpys,\ (eq_attr "type" "ffariths, fadds, ffarithd, faddd, fmov,\
f_cvt, f_cvtf2i, f_cvti2f, fcmps, fcmpd")) f_cvt, f_cvtf2i, f_cvti2f, fcmps, fcmpd"))
"cortex_a7_ex1+cortex_a7_fpadd_pipe") "cortex_a7_ex1+cortex_a7_fpadd_pipe")
......
gcc/config/arm/cortex-a8-neon.md
...@@ -172,7 +172,7 @@ ...@@ -172,7 +172,7 @@
;; take four cycles, we pick that latency. ;; take four cycles, we pick that latency.
(define_insn_reservation "cortex_a8_vfp_farith" 4 (define_insn_reservation "cortex_a8_vfp_farith" 4
(and (eq_attr "tune" "cortexa8") (and (eq_attr "tune" "cortexa8")
(eq_attr "type" "fcpys,ffariths,ffarithd,fconsts,fconstd,fcmps,fcmpd")) (eq_attr "type" "fmov,ffariths,ffarithd,fconsts,fconstd,fcmps,fcmpd"))
"cortex_a8_vfp,cortex_a8_vfplite*3") "cortex_a8_vfp,cortex_a8_vfplite*3")
(define_insn_reservation "cortex_a8_vfp_cvt" 7 (define_insn_reservation "cortex_a8_vfp_cvt" 7
......
gcc/config/arm/cortex-a9.md
...@@ -207,7 +207,7 @@ cortex_a9_store3_4, cortex_a9_store1_2, cortex_a9_load3_4") ...@@ -207,7 +207,7 @@ cortex_a9_store3_4, cortex_a9_store1_2, cortex_a9_load3_4")
;; Pipelining for VFP instructions. ;; Pipelining for VFP instructions.
;; Issue happens either along load store unit or the VFP / Neon unit. ;; Issue happens either along load store unit or the VFP / Neon unit.
;; Pipeline Instruction Classification. ;; Pipeline Instruction Classification.
;; FPS - fcpys, ffariths, ffarithd,f_mcr,f_mcrr,f_mrc,f_mrrc ;; FPS - fmov, ffariths, ffarithd,f_mcr,f_mcrr,f_mrc,f_mrrc
;; FP_ADD - fadds, faddd, fcmps (1) ;; FP_ADD - fadds, faddd, fcmps (1)
;; FPMUL - fmul{s,d}, fmac{s,d}, ffma{s,d} ;; FPMUL - fmul{s,d}, fmac{s,d}, ffma{s,d}
;; FPDIV - fdiv{s,d} ;; FPDIV - fdiv{s,d}
...@@ -220,7 +220,7 @@ cortex_a9_store3_4, cortex_a9_store1_2, cortex_a9_load3_4") ...@@ -220,7 +220,7 @@ cortex_a9_store3_4, cortex_a9_store1_2, cortex_a9_load3_4")
;; fmrs, fmrrd, fmstat and fmrx - The data is available after 1 cycle. ;; fmrs, fmrrd, fmstat and fmrx - The data is available after 1 cycle.
(define_insn_reservation "cortex_a9_fps" 2 (define_insn_reservation "cortex_a9_fps" 2
(and (eq_attr "tune" "cortexa9") (and (eq_attr "tune" "cortexa9")
(eq_attr "type" "fcpys, fconsts, fconstd, ffariths, ffarithd,\ (eq_attr "type" "fmov, fconsts, fconstd, ffariths, ffarithd,\
f_mcr, f_mcrr, f_mrc, f_mrrc, f_flag")) f_mcr, f_mcrr, f_mrc, f_mrrc, f_flag"))
"ca9_issue_vfp_neon + ca9fps") "ca9_issue_vfp_neon + ca9fps")
......
gcc/config/arm/cortex-m4-fpu.md
...@@ -35,7 +35,7 @@ ...@@ -35,7 +35,7 @@
(define_insn_reservation "cortex_m4_vmov_1" 1 (define_insn_reservation "cortex_m4_vmov_1" 1
(and (eq_attr "tune" "cortexm4") (and (eq_attr "tune" "cortexm4")
(eq_attr "type" "fcpys,fconsts")) (eq_attr "type" "fmov,fconsts"))
"cortex_m4_ex_v") "cortex_m4_ex_v")
(define_insn_reservation "cortex_m4_vmov_2" 2 (define_insn_reservation "cortex_m4_vmov_2" 2
......
gcc/config/arm/cortex-r4f.md
...@@ -48,7 +48,7 @@ ...@@ -48,7 +48,7 @@
(define_insn_reservation "cortex_r4_fcpys" 2 (define_insn_reservation "cortex_r4_fcpys" 2
(and (eq_attr "tune_cortexr4" "yes") (and (eq_attr "tune_cortexr4" "yes")
(eq_attr "type" "fcpys")) (eq_attr "type" "fmov"))
"cortex_r4_issue_ab") "cortex_r4_issue_ab")
(define_insn_reservation "cortex_r4_ffariths" 2 (define_insn_reservation "cortex_r4_ffariths" 2
......
gcc/config/arm/iwmmxt.md
...@@ -189,7 +189,7 @@ ...@@ -189,7 +189,7 @@
gcc_unreachable (); gcc_unreachable ();
}" }"
[(set_attr "type" "*,*,*,*,load1,store1,*,*,*,*,f_mcr,f_mrc,\ [(set_attr "type" "*,*,*,*,load1,store1,*,*,*,*,f_mcr,f_mrc,\
fcpys,f_loads,f_stores") fmov,f_loads,f_stores")
(set_attr "length" "*,*,*,*,*, *,*,*, 16, *,*,*,*,*,*") (set_attr "length" "*,*,*,*,*, *,*,*, 16, *,*,*,*,*,*")
(set_attr "pool_range" "*,*,*,*,4096, *,*,*,1024, *,*,*,*,1020,*") (set_attr "pool_range" "*,*,*,*,4096, *,*,*,1024, *,*,*,*,1020,*")
(set_attr "neg_pool_range" "*,*,*,*,4084, *,*,*, *, 1012,*,*,*,1008,*") (set_attr "neg_pool_range" "*,*,*,*,4084, *,*,*, *, 1012,*,*,*,1008,*")
......
gcc/config/arm/marvell-pj4.md
...@@ -208,7 +208,7 @@ ...@@ -208,7 +208,7 @@
(define_insn_reservation "pj4_vfp_cpy" 4 (define_insn_reservation "pj4_vfp_cpy" 4
(and (eq_attr "tune" "marvell_pj4") (and (eq_attr "tune" "marvell_pj4")
(eq_attr "type" "fcpys,ffariths,ffarithd,fconsts,fconstd,\ (eq_attr "type" "fmov,ffariths,ffarithd,fconsts,fconstd,\
fcmps,fcmpd,f_cvt,f_cvtf2i,f_cvti2f")) fcmps,fcmpd,f_cvt,f_cvtf2i,f_cvti2f"))
"pj4_is,nothing*2,vissue,vfast,nothing*2") "pj4_is,nothing*2,vissue,vfast,nothing*2")
......
gcc/config/arm/types.md
...@@ -71,13 +71,13 @@ ...@@ -71,13 +71,13 @@
; fadd[d,s] double/single floating-point scalar addition. ; fadd[d,s] double/single floating-point scalar addition.
; fcmp[d,s] double/single floating-point compare. ; fcmp[d,s] double/single floating-point compare.
; fconst[d,s] double/single load immediate. ; fconst[d,s] double/single load immediate.
; fcpys single precision floating point cpy.
; fcsel From ARMv8-A: Floating-point conditional select. ; fcsel From ARMv8-A: Floating-point conditional select.
; fdiv[d,s] double/single precision floating point division. ; fdiv[d,s] double/single precision floating point division.
; ffarith[d,s] double/single floating point abs/neg/cpy. ; ffarith[d,s] double/single floating point abs/neg/cpy.
; ffma[d,s] double/single floating point fused multiply-accumulate. ; ffma[d,s] double/single floating point fused multiply-accumulate.
; float floating point arithmetic operation. ; float floating point arithmetic operation.
; fmac[d,s] double/single floating point multiply-accumulate. ; fmac[d,s] double/single floating point multiply-accumulate.
; fmov floating point to floating point register move.
; fmul[d,s] double/single floating point multiply. ; fmul[d,s] double/single floating point multiply.
; fsqrt[d,s] double/single precision floating point square root. ; fsqrt[d,s] double/single precision floating point square root.
; load_acq load-acquire. ; load_acq load-acquire.
...@@ -337,7 +337,6 @@ ...@@ -337,7 +337,6 @@
fcmps,\ fcmps,\
fconstd,\ fconstd,\
fconsts,\ fconsts,\
fcpys,\
fcsel,\ fcsel,\
fdivd,\ fdivd,\
fdivs,\ fdivs,\
...@@ -348,6 +347,7 @@ ...@@ -348,6 +347,7 @@
float,\ float,\
fmacd,\ fmacd,\
fmacs,\ fmacs,\
fmov,\
fmuld,\ fmuld,\
fmuls,\ fmuls,\
fsqrts,\ fsqrts,\
......
gcc/config/arm/vfp.md
...@@ -53,7 +53,7 @@ ...@@ -53,7 +53,7 @@
} }
" "
[(set_attr "predicable" "yes") [(set_attr "predicable" "yes")
(set_attr "type" "mov_reg,mov_reg,mvn_imm,mov_imm,load1,store1,f_mcr,f_mrc,fcpys,f_loads,f_stores") (set_attr "type" "mov_reg,mov_reg,mvn_imm,mov_imm,load1,store1,f_mcr,f_mrc,fmov,f_loads,f_stores")
(set_attr "pool_range" "*,*,*,*,4096,*,*,*,*,1020,*") (set_attr "pool_range" "*,*,*,*,4096,*,*,*,*,1020,*")
(set_attr "neg_pool_range" "*,*,*,*,4084,*,*,*,*,1008,*")] (set_attr "neg_pool_range" "*,*,*,*,4084,*,*,*,*,1008,*")]
) )
...@@ -100,7 +100,7 @@ ...@@ -100,7 +100,7 @@
" "
[(set_attr "predicable" "yes") [(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "yes,no,yes,no,no,no,no,no,no,no,no,no,no,no") (set_attr "predicable_short_it" "yes,no,yes,no,no,no,no,no,no,no,no,no,no,no")
(set_attr "type" "mov_reg,mov_reg,mov_reg,mvn_reg,mov_reg,load1,load1,store1,store1,f_mcr,f_mrc,fcpys,f_loads,f_stores") (set_attr "type" "mov_reg,mov_reg,mov_reg,mvn_reg,mov_reg,load1,load1,store1,store1,f_mcr,f_mrc,fmov,f_loads,f_stores")
(set_attr "length" "2,4,2,4,4,4,4,4,4,4,4,4,4,4") (set_attr "length" "2,4,2,4,4,4,4,4,4,4,4,4,4,4")
(set_attr "pool_range" "*,*,*,*,*,1018,4094,*,*,*,*,*,1018,*") (set_attr "pool_range" "*,*,*,*,*,1018,4094,*,*,*,*,*,1018,*")
(set_attr "neg_pool_range" "*,*,*,*,*, 0, 0,*,*,*,*,*,1008,*")] (set_attr "neg_pool_range" "*,*,*,*,*, 0, 0,*,*,*,*,*,1008,*")]
...@@ -261,7 +261,7 @@ ...@@ -261,7 +261,7 @@
" "
[(set_attr "conds" "unconditional") [(set_attr "conds" "unconditional")
(set_attr "type" "neon_vld1_1_2_regs,neon_vst1_1_2_regs_vst2_2_regs,\ (set_attr "type" "neon_vld1_1_2_regs,neon_vst1_1_2_regs_vst2_2_regs,\
load1,store1,fcpys,mov_reg,f_mcr,f_mrc,multiple") load1,store1,fmov,mov_reg,f_mcr,f_mrc,multiple")
(set_attr "length" "4,4,4,4,4,4,4,4,8")] (set_attr "length" "4,4,4,4,4,4,4,4,8")]
) )
...@@ -311,7 +311,7 @@ ...@@ -311,7 +311,7 @@
} }
" "
[(set_attr "conds" "unconditional") [(set_attr "conds" "unconditional")
(set_attr "type" "load1,store1,fcpys,mov_reg,f_mcr,f_mrc,multiple") (set_attr "type" "load1,store1,fmov,mov_reg,f_mcr,f_mrc,multiple")
(set_attr "length" "4,4,4,4,4,4,8")] (set_attr "length" "4,4,4,4,4,4,8")]
) )
...@@ -351,7 +351,7 @@ ...@@ -351,7 +351,7 @@
" "
[(set_attr "predicable" "yes") [(set_attr "predicable" "yes")
(set_attr "type" (set_attr "type"
"f_mcr,f_mrc,fconsts,f_loads,f_stores,load1,store1,fcpys,mov_reg") "f_mcr,f_mrc,fconsts,f_loads,f_stores,load1,store1,fmov,mov_reg")
(set_attr "pool_range" "*,*,*,1020,*,4096,*,*,*") (set_attr "pool_range" "*,*,*,1020,*,4096,*,*,*")
(set_attr "neg_pool_range" "*,*,*,1008,*,4080,*,*,*")] (set_attr "neg_pool_range" "*,*,*,1008,*,4080,*,*,*")]
) )
...@@ -388,7 +388,7 @@ ...@@ -388,7 +388,7 @@
[(set_attr "predicable" "yes") [(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no") (set_attr "predicable_short_it" "no")
(set_attr "type" (set_attr "type"
"f_mcr,f_mrc,fconsts,f_loads,f_stores,load1,store1,fcpys,mov_reg") "f_mcr,f_mrc,fconsts,f_loads,f_stores,load1,store1,fmov,mov_reg")
(set_attr "pool_range" "*,*,*,1018,*,4090,*,*,*") (set_attr "pool_range" "*,*,*,1018,*,4090,*,*,*")
(set_attr "neg_pool_range" "*,*,*,1008,*,0,*,*,*")] (set_attr "neg_pool_range" "*,*,*,1008,*,0,*,*,*")]
) )
...@@ -509,7 +509,7 @@ ...@@ -509,7 +509,7 @@
fmrs%D3\\t%0, %2\;fmrs%d3\\t%0, %1" fmrs%D3\\t%0, %2\;fmrs%d3\\t%0, %1"
[(set_attr "conds" "use") [(set_attr "conds" "use")
(set_attr "length" "4,4,8,4,4,8,4,4,8") (set_attr "length" "4,4,8,4,4,8,4,4,8")
(set_attr "type" "fcpys,fcpys,fcpys,f_mcr,f_mcr,f_mcr,f_mrc,f_mrc,f_mrc")] (set_attr "type" "fmov,fmov,fmov,f_mcr,f_mcr,f_mcr,f_mrc,f_mrc,f_mrc")]
) )
(define_insn "*thumb2_movsfcc_vfp" (define_insn "*thumb2_movsfcc_vfp"
...@@ -532,7 +532,7 @@ ...@@ -532,7 +532,7 @@
ite\\t%D3\;fmrs%D3\\t%0, %2\;fmrs%d3\\t%0, %1" ite\\t%D3\;fmrs%D3\\t%0, %2\;fmrs%d3\\t%0, %1"
[(set_attr "conds" "use") [(set_attr "conds" "use")
(set_attr "length" "6,6,10,6,6,10,6,6,10") (set_attr "length" "6,6,10,6,6,10,6,6,10")
(set_attr "type" "fcpys,fcpys,fcpys,f_mcr,f_mcr,f_mcr,f_mrc,f_mrc,f_mrc")] (set_attr "type" "fmov,fmov,fmov,f_mcr,f_mcr,f_mcr,f_mrc,f_mrc,f_mrc")]
) )
(define_insn "*movdfcc_vfp" (define_insn "*movdfcc_vfp"
......
gcc/config/arm/vfp11.md
...@@ -51,7 +51,7 @@ ...@@ -51,7 +51,7 @@
(define_insn_reservation "vfp_ffarith" 4 (define_insn_reservation "vfp_ffarith" 4
(and (eq_attr "generic_vfp" "yes") (and (eq_attr "generic_vfp" "yes")
(eq_attr "type" "fcpys,ffariths,ffarithd,fcmps,fcmpd")) (eq_attr "type" "fmov,ffariths,ffarithd,fcmps,fcmpd"))
"fmac") "fmac")
(define_insn_reservation "vfp_farith" 8 (define_insn_reservation "vfp_farith" 8
......
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