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riscv-gcc-1
Commit 285a5742 by Kazu Hirata Committed by Kazu Hirata
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alpha-interix.h: Fix comment formatting. 

	* config/alpha/alpha-interix.h: Fix comment formatting.
	* config/alpha/alpha.c: Likewise.
	* config/alpha/alpha.h: Likewise.
	* config/alpha/alpha32.h: Likewise.
	* config/alpha/freebsd.h: Likewise.
	* config/alpha/unicosmk.h: Likewise.
	* config/alpha/vms.h: Likewise.

From-SVN: r46949
parent 96eaf358
Showing with 72 additions and 62 deletions
gcc/ChangeLog
2001-11-12 Kazu Hirata <kazu@hxi.com>
* config/alpha/alpha-interix.h: Fix comment formatting.
* config/alpha/alpha.c: Likewise.
* config/alpha/alpha.h: Likewise.
* config/alpha/alpha32.h: Likewise.
* config/alpha/freebsd.h: Likewise.
* config/alpha/unicosmk.h: Likewise.
* config/alpha/vms.h: Likewise.
2001-11-12 Kazu Hirata <kazu@hxi.com>
* config/h8300/h8300.c (get_shift_alg): Remove redundant code.
2001-11-12 Jakub Jelinek <jakub@redhat.com>
......
gcc/config/alpha/alpha-interix.h
......@@ -129,7 +129,7 @@ const_section () \
#define INT_ASM_OP "\t.long\t"
/* The linker will take care of this, and having them causes problems with
ld -r (specifically -rU). */
ld -r (specifically -rU). */
#define CTOR_LISTS_DEFINED_EXTERNALLY 1
#define SET_ASM_OP "\t.set\t"
......@@ -157,11 +157,11 @@ while (0)
#define PCC_BITFIELD_TYPE_TEST TYPE_NATIVE(rec)
#define GROUP_BITFIELDS_BY_ALIGN TYPE_NATIVE(rec)
/* DWARF2 Unwinding doesn't work with exception handling yet. */
/* DWARF2 Unwinding doesn't work with exception handling yet. */
#undef DWARF2_UNWIND_INFO
#define DWARF2_UNWIND_INFO 0
/* Don't assume anything about the header files. */
/* Don't assume anything about the header files. */
#define NO_IMPLICIT_EXTERN_C
/* The definition of this macro implies that there are cases where
......@@ -169,7 +169,7 @@ while (0)
On NT (according to the spec) anything except strings/array that fits
in 64 bits is returned in the registers (this appears to differ from
the rest of the Alpha family). */
the rest of the Alpha family). */
#undef RETURN_IN_MEMORY
#define RETURN_IN_MEMORY(TYPE) \
......@@ -189,7 +189,7 @@ while (0)
}
/* The current Interix assembler (consistent with the DEC documentation)
uses a=b NOT .set a,b; .set is for assembler options. */
uses a=b NOT .set a,b; .set is for assembler options. */
#undef ASM_OUTPUT_DEFINE_LABEL_DIFFERENCE_SYMBOL
#define ASM_OUTPUT_DEFINE_LABEL_DIFFERENCE_SYMBOL(FILE, SY, HI, LO) \
do { \
......
gcc/config/alpha/alpha.c
......@@ -50,7 +50,7 @@ Boston, MA 02111-1307, USA. */
/* External data. */
extern int rtx_equal_function_value_matters;
/* Specify which cpu to schedule for. */
/* Specify which cpu to schedule for. */
enum processor_type alpha_cpu;
static const char * const alpha_cpu_name[] =
......@@ -217,7 +217,7 @@ static unsigned int unicosmk_section_type_flags PARAMS ((tree, const char *,
struct gcc_target targetm = TARGET_INITIALIZER;
/* Parse target option strings. */
/* Parse target option strings. */
void
override_options ()
......@@ -365,7 +365,7 @@ override_options ()
error ("bad value `%s' for -mcpu switch", alpha_tune_string);
}
/* Do some sanity checks on the above options. */
/* Do some sanity checks on the above options. */
if (TARGET_ABI_UNICOSMK && alpha_fptm != ALPHA_FPTM_N)
{
......@@ -420,7 +420,7 @@ override_options ()
{
{ 3, 30, -1 }, /* ev4 -- Bcache is a guess */
{ 2, 12, 38 }, /* ev5 -- Bcache from PC164 LMbench numbers */
{ 3, 12, 30 }, /* ev6 -- Bcache from DS20 LMbench. */
{ 3, 12, 30 }, /* ev6 -- Bcache from DS20 LMbench. */
};
lat = alpha_mlat_string[1] - '0';
......@@ -460,7 +460,7 @@ override_options ()
/* Align labels and loops for optimal branching. */
/* ??? Kludge these by not doing anything if we don't optimize and also if
we are writing ECOFF symbols to work around a bug in DEC's assembler. */
we are writing ECOFF symbols to work around a bug in DEC's assembler. */
if (optimize > 0 && write_symbols != SDB_DEBUG)
{
if (align_loops <= 0)
......@@ -812,7 +812,7 @@ input_operand (op, mode)
case SUBREG:
if (register_operand (op, mode))
return 1;
/* ... fall through ... */
/* ... fall through ... */
case MEM:
return ((TARGET_BWX || (mode != HImode && mode != QImode))
&& general_operand (op, mode));
......@@ -2011,7 +2011,7 @@ alpha_emit_set_const (target, mode, c, n)
rtx pat;
int i;
/* Try 1 insn, then 2, then up to N. */
/* Try 1 insn, then 2, then up to N. */
for (i = 1; i <= n; i++)
if ((pat = alpha_emit_set_const_1 (target, mode, c, i)) != 0)
return pat;
......@@ -2047,7 +2047,7 @@ alpha_emit_set_const_1 (target, mode, c, n)
/* If this is a sign-extended 32-bit constant, we can do this in at most
three insns, so do it if we have enough insns left. We always have
a sign-extended 32-bit constant when compiling on a narrow machine. */
a sign-extended 32-bit constant when compiling on a narrow machine. */
if (HOST_BITS_PER_WIDE_INT != 64
|| c >> 31 == -1 || c >> 31 == 0)
......@@ -2162,7 +2162,7 @@ alpha_emit_set_const_1 (target, mode, c, n)
/* Now try high-order 1 bits. We get that with a sign-extension.
But one bit isn't enough here. Be careful to avoid shifting outside
the mode and to avoid shifting outside the host wide int size. */
the mode and to avoid shifting outside the host wide int size. */
if ((bits = (MIN (HOST_BITS_PER_WIDE_INT, GET_MODE_SIZE (mode) * 8)
- floor_log2 (~ c) - 2)) > 0)
......@@ -2607,7 +2607,7 @@ alpha_emit_conditional_branch (code)
case NE:
case ORDERED:
/* These must be reversed. */
/* These must be reversed. */
cmp_code = reverse_condition (code), branch_code = EQ;
break;
......@@ -2819,7 +2819,7 @@ alpha_emit_setcc (code)
a conditional move (if_then_else CMP ...).
If both of the operands that set cc0 are non-zero we must emit
an insn to perform the compare (it can't be done within
the conditional move). */
the conditional move). */
rtx
alpha_emit_conditional_move (cmp, mode)
rtx cmp;
......@@ -2894,7 +2894,7 @@ alpha_emit_conditional_move (cmp, mode)
}
/* We may be able to use a conditional move directly.
This avoids emitting spurious compares. */
This avoids emitting spurious compares. */
if (signed_comparison_operator (cmp, VOIDmode)
&& (!fp_p || local_fast_math)
&& (op0 == CONST0_RTX (cmp_mode) || op1 == CONST0_RTX (cmp_mode)))
......@@ -2915,7 +2915,7 @@ alpha_emit_conditional_move (cmp, mode)
break;
case NE:
/* This must be reversed. */
/* This must be reversed. */
code = reverse_condition (code);
cmov_code = EQ;
break;
......@@ -2992,7 +2992,7 @@ alpha_split_conditional_move (code, dest, cond, t_rtx, f_rtx)
if (f == 0 && exact_log2 (diff) > 0
/* On EV6, we've got enough shifters to make non-arithmatic shifts
viable over a longer latency cmove. On EV5, the E0 slot is a
scarce resource, and on EV4 shift has the same latency as a cmove. */
scarce resource, and on EV4 shift has the same latency as a cmove. */
&& (diff <= 8 || alpha_cpu == PROCESSOR_EV6))
{
tmp = gen_rtx_fmt_ee (code, DImode, cond, const0_rtx);
......@@ -4689,7 +4689,7 @@ alpha_adjust_cost (insn, link, dep_insn, cost)
break;
}
/* Otherwise, return the default cost. */
/* Otherwise, return the default cost. */
return cost;
}
......@@ -4798,7 +4798,7 @@ alpha_ra_ever_killed ()
/* Return the trap mode suffix applicable to the current
instruction, or NULL. */
instruction, or NULL. */
static const char *
get_trap_mode_suffix ()
......@@ -4865,7 +4865,7 @@ get_trap_mode_suffix ()
}
/* Return the rounding mode suffix applicable to the current
instruction, or NULL. */
instruction, or NULL. */
static const char *
get_round_mode_suffix ()
......@@ -5282,7 +5282,7 @@ alpha_initialize_trampoline (tramp, fnaddr, cxt, fnofs, cxtofs, jmpofs)
emit_move_insn (gen_rtx_MEM (mode, addr), cxt);
/* This has been disabled since the hint only has a 32k range, and in
no existing OS is the stack within 32k of the text segment. */
no existing OS is the stack within 32k of the text segment. */
if (0 && jmpofs >= 0)
{
/* Compute hint value. */
......@@ -5597,7 +5597,7 @@ alpha_va_arg (valist, type)
/* These variables are used for communication between the following functions.
They indicate various things about the current function being compiled
that are used to tell what kind of prologue, epilogue and procedure
descriptior to generate. */
descriptior to generate. */
/* Nonzero if we need a stack procedure. */
static int alpha_is_stack_procedure;
......@@ -6318,7 +6318,7 @@ alpha_start_function (file, fnname, decl)
{
/* Set flags in procedure descriptor to request IEEE-conformant
math-library routines. The value we set it to is PDSC_EXC_IEEE
(/usr/include/pdsc.h). */
(/usr/include/pdsc.h). */
fputs ("\t.eflag 48\n", file);
}
......@@ -6514,7 +6514,7 @@ alpha_expand_epilogue ()
FRP (emit_move_insn (sa_reg, sa_reg_exp));
}
/* Restore registers in order, excepting a true frame pointer. */
/* Restore registers in order, excepting a true frame pointer. */
mem = gen_rtx_MEM (DImode, plus_constant (sa_reg, reg_offset));
if (! eh_ofs)
......
gcc/config/alpha/alpha.h
......@@ -71,20 +71,20 @@ enum alpha_trap_precision
{
ALPHA_TP_PROG, /* No precision (default). */
ALPHA_TP_FUNC, /* Trap contained within originating function. */
ALPHA_TP_INSN /* Instruction accuracy and code is resumption safe. */
ALPHA_TP_INSN /* Instruction accuracy and code is resumption safe. */
};
enum alpha_fp_rounding_mode
{
ALPHA_FPRM_NORM, /* Normal rounding mode. */
ALPHA_FPRM_MINF, /* Round towards minus-infinity. */
ALPHA_FPRM_CHOP, /* Chopped rounding mode (towards 0). */
ALPHA_FPRM_CHOP, /* Chopped rounding mode (towards 0). */
ALPHA_FPRM_DYN /* Dynamic rounding mode. */
};
enum alpha_fp_trap_mode
{
ALPHA_FPTM_N, /* Normal trap mode. */
ALPHA_FPTM_N, /* Normal trap mode. */
ALPHA_FPTM_U, /* Underflow traps enabled. */
ALPHA_FPTM_SU, /* Software completion, w/underflow traps */
ALPHA_FPTM_SUI /* Software completion, w/underflow & inexact traps */
......@@ -113,7 +113,7 @@ extern enum alpha_fp_trap_mode alpha_fptm;
#define MASK_GAS (1 << 2)
#define TARGET_GAS (target_flags & MASK_GAS)
/* This means that we should mark procedures as IEEE conformant. */
/* This means that we should mark procedures as IEEE conformant. */
#define MASK_IEEE_CONFORMANT (1 << 3)
#define TARGET_IEEE_CONFORMANT (target_flags & MASK_IEEE_CONFORMANT)
......@@ -298,13 +298,13 @@ extern const char *alpha_mlat_string; /* For -mmemory-latency= */
/* Attempt to describe CPU characteristics to the preprocessor. */
/* Corresponding to amask... */
/* Corresponding to amask... */
#define CPP_AM_BWX_SPEC "-D__alpha_bwx__ -Acpu=bwx"
#define CPP_AM_MAX_SPEC "-D__alpha_max__ -Acpu=max"
#define CPP_AM_FIX_SPEC "-D__alpha_fix__ -Acpu=fix"
#define CPP_AM_CIX_SPEC "-D__alpha_cix__ -Acpu=cix"
/* Corresponding to implver... */
/* Corresponding to implver... */
#define CPP_IM_EV4_SPEC "-D__alpha_ev4__ -Acpu=ev4"
#define CPP_IM_EV5_SPEC "-D__alpha_ev5__ -Acpu=ev5"
#define CPP_IM_EV6_SPEC "-D__alpha_ev6__ -Acpu=ev6"
......@@ -420,7 +420,7 @@ extern const char *alpha_mlat_string; /* For -mmemory-latency= */
/* target machine storage layout */
/* Define to enable software floating point emulation. */
/* Define to enable software floating point emulation. */
#define REAL_ARITHMETIC
/* Define the size of `int'. The default is the same as the word size. */
......@@ -482,7 +482,7 @@ extern const char *alpha_mlat_string; /* For -mmemory-latency= */
numbered.
For Alpha we can decide arbitrarily since there are no machine instructions
for them. Might as well be consistent with bytes. */
for them. Might as well be consistent with bytes. */
#define WORDS_BIG_ENDIAN 0
/* number of bits in an addressable storage unit */
......@@ -737,7 +737,7 @@ enum reg_class {
#define N_REG_CLASSES (int) LIM_REG_CLASSES
/* Give names of register classes as strings for dump file. */
/* Give names of register classes as strings for dump file. */
#define REG_CLASS_NAMES \
{"NO_REGS", "R24_REG", "R25_REG", "R27_REG", \
......@@ -867,7 +867,7 @@ enum reg_class {
QImode and HImode from an aligned address to a general register
unless byte instructions are permitted.
We also cannot load an unaligned address or a paradoxical SUBREG into an
FP register. */
FP register. */
#define SECONDARY_INPUT_RELOAD_CLASS(CLASS,MODE,IN) \
secondary_reload_class((CLASS), (MODE), (IN), 1)
......@@ -972,7 +972,7 @@ extern int alpha_memory_latency;
We have two registers that can be eliminated on the Alpha. First, the
frame pointer register can often be eliminated in favor of the stack
pointer register. Secondly, the argument pointer register can always be
eliminated; it is replaced with either the stack or frame pointer. */
eliminated; it is replaced with either the stack or frame pointer. */
/* This is an array of structures. Each structure initializes one pair
of eliminable registers. The "from" register number is given first,
......@@ -1136,7 +1136,7 @@ extern int alpha_memory_latency;
reference. If nonzero for an argument, a copy of that argument is
made in memory and a pointer to the argument is passed instead of
the argument itself. The pointer is passed in whatever way is
appropriate for passing a pointer to that type. */
appropriate for passing a pointer to that type. */
#define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) \
((MODE) == TFmode || (MODE) == TCmode)
......@@ -1266,7 +1266,7 @@ extern struct alpha_compare alpha_compare;
/* Output assembler code to FILE to initialize this source file's
basic block profiling info, if that has not already been done.
This assumes that __bb_init_func doesn't garble a1-a5. */
This assumes that __bb_init_func doesn't garble a1-a5. */
#define FUNCTION_BLOCK_PROFILER(FILE, LABELNO) \
do { \
......@@ -1352,7 +1352,7 @@ do { \
#define RETURN_ADDR_RTX alpha_return_addr
/* Before the prologue, RA lives in $26. */
/* Before the prologue, RA lives in $26. */
#define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, 26)
#define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (26)
......@@ -1428,7 +1428,7 @@ do { \
that may eliminate to the frame pointer. These will be allowed to
have offsets greater than 32K. This is done because register
elimination offsets will change the hi/lo split, and if we split
before reload, we will require additional instructions. */
before reload, we will require additional instructions. */
#define NONSTRICT_REG_OK_FP_BASE_P(X) \
(REGNO (X) == 31 || REGNO (X) == 63 \
|| (REGNO (X) >= FIRST_PSEUDO_REGISTER \
......@@ -1501,7 +1501,7 @@ do { \
#define ADDRESS_COST(X) 0
/* Machine-dependent reorg pass. */
/* Machine-dependent reorg pass. */
#define MACHINE_DEPENDENT_REORG(X) alpha_reorg(X)
/* Specify the machine mode that this machine uses
......@@ -1544,7 +1544,7 @@ do { \
move-instruction pairs, we will do a movstr or libcall instead.
Without byte/word accesses, we want no more than four instructions;
with, several single byte accesses are better. */
with, several single byte accesses are better. */
#define MOVE_RATIO (TARGET_BWX ? 7 : 2)
......@@ -1613,7 +1613,7 @@ do { \
between pointers and any other objects of this machine mode. */
#define Pmode DImode
/* Mode of a function address in a call instruction (for indexing purposes). */
/* Mode of a function address in a call instruction (for indexing purposes). */
#define FUNCTION_MODE Pmode
......@@ -1630,7 +1630,7 @@ do { \
#define NO_FUNCTION_CSE
/* Define this to be nonzero if shift instructions ignore all but the low-order
few bits. */
few bits. */
#define SHIFT_COUNT_TRUNCATED 1
/* Compute the cost of computing a constant rtl expression RTX
......@@ -1716,7 +1716,7 @@ do { \
if (GET_CODE (XEXP (X, 1)) == CONST_INT \
&& INTVAL (XEXP (X, 1)) <= 3) \
break; \
/* ... fall through ... */ \
/* ... fall through ... */ \
case ASHIFTRT: case LSHIFTRT: \
switch (alpha_cpu) \
{ \
......@@ -1776,7 +1776,7 @@ do { \
case NEG: case ABS: \
if (! FLOAT_MODE_P (GET_MODE (X))) \
break; \
/* ... fall through ... */ \
/* ... fall through ... */ \
case FLOAT: case UNSIGNED_FLOAT: case FIX: case UNSIGNED_FIX: \
case FLOAT_EXTEND: case FLOAT_TRUNCATE: \
switch (alpha_cpu) \
......@@ -1847,7 +1847,7 @@ literal_section () \
/* If a variable is weakened, made one only or moved into a different
section, it may be necessary to redo the section info to move the
variable out of sdata. */
variable out of sdata. */
#define REDO_SECTION_INFO_P(DECL) \
((TREE_CODE (DECL) == VAR_DECL) \
......@@ -1906,7 +1906,7 @@ do { \
#define ASM_GLOBALIZE_LABEL(FILE,NAME) \
do { fputs ("\t.globl ", FILE); assemble_name (FILE, NAME); fputs ("\n", FILE);} while (0)
/* The prefix to add to user-visible assembler symbols. */
/* The prefix to add to user-visible assembler symbols. */
#define USER_LABEL_PREFIX ""
......@@ -1918,7 +1918,7 @@ do { \
/* This is how to output a label for a jump table. Arguments are the same as
for ASM_OUTPUT_INTERNAL_LABEL, except the insn for the jump table is
passed. */
passed. */
#define ASM_OUTPUT_CASE_LABEL(FILE,PREFIX,NUM,TABLEINSN) \
{ ASM_OUTPUT_ALIGN (FILE, 2); ASM_OUTPUT_INTERNAL_LABEL (FILE, PREFIX, NUM); }
......@@ -2328,7 +2328,7 @@ do { \
mips-tdump.c to print them out.
These must match the corresponding definitions in gdb/mipsread.c.
Unfortunately, gcc and gdb do not currently share any directories. */
Unfortunately, gcc and gdb do not currently share any directories. */
#define CODE_MASK 0x8F300
#define MIPS_IS_STAB(sym) (((sym)->index & 0xFFF00) == CODE_MASK)
......@@ -2347,5 +2347,5 @@ do { \
/* The system headers under Alpha systems are generally C++-aware. */
#define NO_IMPLICIT_EXTERN_C
/* Generate calls to memcpy, etc., not bcopy, etc. */
/* Generate calls to memcpy, etc., not bcopy, etc. */
#define TARGET_MEM_FUNCTIONS 1
gcc/config/alpha/alpha32.h
......@@ -36,7 +36,7 @@ Boston, MA 02111-1307, USA. */
/* WinNT (and thus Interix) use unsigned int */
#define SIZE_TYPE "unsigned int"
/* Pointer is 32 bits but the hardware has 64-bit addresses, sign extended. */
/* Pointer is 32 bits but the hardware has 64-bit addresses, sign extended. */
#undef POINTER_SIZE
#define POINTER_SIZE 32
#define POINTERS_EXTEND_UNSIGNED 0
......@@ -73,7 +73,7 @@ Boston, MA 02111-1307, USA. */
/* Emit RTL insns to initialize the variable parts of a trampoline.
FNADDR is an RTX for the address of the function's pure code.
CXT is an RTX for the static chain value for the function. */
CXT is an RTX for the static chain value for the function. */
#undef INITIALIZE_TRAMPOLINE
#define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
......
gcc/config/alpha/freebsd.h
......@@ -82,7 +82,7 @@ Boston, MA 02111-1307, USA. */
/* Output assembler code to FILE to increment profiler label # LABELNO
for profiling a function entry. Under FreeBSD/Alpha, the assembler does
nothing special with -pg. */
nothing special with -pg. */
#undef FUNCTION_PROFILER
#define FUNCTION_PROFILER(FILE, LABELNO) \
......
gcc/config/alpha/unicosmk.h
......@@ -47,7 +47,7 @@ Boston, MA 02111-1307, USA. */
#undef INT_TYPE_SIZE
#define INT_TYPE_SIZE 64
/* This is consistent with the definition Cray CC uses. */
/* This is consistent with the definition Cray CC uses. */
#undef WCHAR_TYPE
#define WCHAR_TYPE "int"
#undef WCHAR_TYPE_SIZE
......@@ -229,7 +229,7 @@ do { \
#undef FUNCTION_ARG_PADDING
/* An argument is passed either entirely in registers or entirely on stack. */
/* An argument is passed either entirely in registers or entirely on stack. */
#undef FUNCTION_ARG_PARTIAL_NREGS
/* #define FUNCTION_ARG_PARTIAL_NREGS(CUM,MODE,TYPE,NAMED) 0 */
......@@ -325,7 +325,7 @@ do { fprintf (FILE, "\tbr $1,0\n"); \
/* Specify the machine mode that this machine uses for the index in the
tablejump instruction. On Unicos/Mk, we don't support relative case
vectors yet, thus the entries should be absolute addresses. */
vectors yet, thus the entries should be absolute addresses. */
#undef CASE_VECTOR_MODE
#define CASE_VECTOR_MODE DImode
......@@ -401,7 +401,7 @@ ssib_section () \
#undef ASM_FILE_END
#define ASM_FILE_END(FILE) unicosmk_asm_file_end (FILE)
/* We take care of that in ASM_FILE_START. */
/* We take care of that in ASM_FILE_START. */
#undef ASM_OUTPUT_SOURCE_FILENAME
......
gcc/config/alpha/vms.h
......@@ -52,7 +52,7 @@ Boston, MA 02111-1307, USA. */
%{!static:%{shared:-shared} %{!shared:-call_shared}} %{pg} %{taso} \
%{rpath*}"
/* We allow $'s in identifiers unless -ansi is used .. */
/* We allow $'s in identifiers unless -ansi is used .. */
#define DOLLARS_IN_IDENTIFIERS 2
......@@ -87,7 +87,7 @@ Boston, MA 02111-1307, USA. */
#undef LONG_TYPE_SIZE
#define LONG_TYPE_SIZE 32
/* Pointer is 32 bits but the hardware has 64-bit addresses, sign extended. */
/* Pointer is 32 bits but the hardware has 64-bit addresses, sign extended. */
#undef POINTER_SIZE
#define POINTER_SIZE 32
#define POINTERS_EXTEND_UNSIGNED 0
......@@ -201,7 +201,7 @@ typedef struct {int num_args; enum avms_arg_type atypes[6];} avms_arg_info;
However, if NO registers need to be saved, don't allocate any space.
This is not only because we won't need the space, but because AP includes
the current_pretend_args_size and we don't want to mess up any
ap-relative addresses already made. */
ap-relative addresses already made. */
#undef SETUP_INCOMING_VARARGS
#define SETUP_INCOMING_VARARGS(CUM,MODE,TYPE,PRETEND_SIZE,NO_RTL) \
......
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