[Patch AArch64] Make integer vabs intrinsics UNSPECs

gcc/

	* config/aarch64/aarch64-simd.md (aarch64_abs<mode>): New.
	* config/aarch64/aarch64-simd-builtins.def (abs): Split by
	integer and floating point variants.
	* config/aarch64/iterators.md (unspec): Add UNSPEC_ABS.

gcc/testsuite/

	* gcc.target/aarch64/abs_2.c: New.

From-SVN: r220202

gcc/ChangeLog

+2015-01-28  James Greenhalgh  <james.greenhalgh@arm.com>
+
+	* config/aarch64/aarch64-simd.md (aarch64_abs<mode>): New.
+	* config/aarch64/aarch64-simd-builtins.def (abs): Split by
+	integer and floating point variants.
+	* config/aarch64/iterators.md (unspec): Add UNSPEC_ABS.
+
 2015-01-28  Robert Suchanek  <robert.suchanek@imgtec.com>
 
 	* config/mips/mips.c (mips_hard_regno_mode_ok_p): Prohibit accumulators

gcc/config/aarch64/aarch64-simd-builtins.def

@@ -358,7 +358,8 @@
 
   /* Implemented by a mixture of abs2 patterns.  Note the DImode builtin is
      only ever used for the int64x1_t intrinsic, there is no scalar version.  */
-  BUILTIN_VALLDI (UNOP, abs, 2)
+  BUILTIN_VSDQ_I_DI (UNOP, abs, 0)
+  BUILTIN_VDQF (UNOP, abs, 2)
 
   VAR1 (UNOP, vec_unpacks_hi_, 10, v4sf)
   VAR1 (BINOP, float_truncate_hi_, 0, v4sf)

gcc/config/aarch64/aarch64-simd.md

@@ -384,6 +384,19 @@
   [(set_attr "type" "neon_abs<q>")]
 )
 
+;; The intrinsic version of integer ABS must not be allowed to
+;; combine with any operation with an integerated ABS step, such
+;; as SABD.
+(define_insn "aarch64_abs<mode>"
+  [(set (match_operand:VSDQ_I_DI 0 "register_operand" "=w")
+	  (unspec:VSDQ_I_DI
+	    [(match_operand:VSDQ_I_DI 1 "register_operand" "w")]
+	   UNSPEC_ABS))]
+  "TARGET_SIMD"
+  "abs\t%<v>0<Vmtype>, %<v>1<Vmtype>"
+  [(set_attr "type" "neon_abs<q>")]
+)
+
 (define_insn "abd<mode>_3"
   [(set (match_operand:VDQ_BHSI 0 "register_operand" "=w")
 	(abs:VDQ_BHSI (minus:VDQ_BHSI

gcc/config/aarch64/iterators.md

@@ -184,6 +184,7 @@
  [
     UNSPEC_ASHIFT_SIGNED	; Used in aarch-simd.md.
     UNSPEC_ASHIFT_UNSIGNED	; Used in aarch64-simd.md.
+    UNSPEC_ABS		; Used in aarch64-simd.md.
     UNSPEC_FMAX		; Used in aarch64-simd.md.
     UNSPEC_FMAXNMV	; Used in aarch64-simd.md.
     UNSPEC_FMAXV	; Used in aarch64-simd.md.

gcc/testsuite/ChangeLog

+2015-01-28  James Greenhalgh  <james.greenhalgh@arm.com>
+
+	* gcc.target/aarch64/abs_2.c: New.
+
 2015-01-28  Robert Suchanek  <robert.suchanek@imgtec.com>
 
 	* lib/target-supports.exp (check_effective_target_mips_nanlegacy): New.

gcc/testsuite/gcc.target/aarch64/abs_2.c

+/* { dg-do run } */
+/* { dg-options "-O2 --save-temps" } */
+
+#include "arm_neon.h"
+
+extern void abort (void);
+
+int
+main (int argc, char **argv)
+{
+  uint64_t got;
+  uint64_t exp = UINT64_C (0x0001000100003b9b);
+  int16x4_t val1 = vcreate_s16 (0x7fff800080007ffful);
+  int16x4_t val2 = vcreate_s16 (0x80007fff80004464ul);
+  int16x4_t result;
+  /* Avoid folding away the sub early.  */
+  asm volatile ("mov %d0, %0.d[0]":"+w"(val1));
+
+  /* Expect "result" = 0001000100003b9b.  */
+  result = vabs_s16 (vsub_s16 (val1, val2));
+
+  got = vget_lane_u64 (vreinterpret_u64_s16 (result), 0);
+  if (exp != got)
+    abort ();
+
+  return 0;
+}
+
+
+/* { dg-final { scan-assembler-not "sabd" } } */
+/* { dg-final { cleanup-saved-temps } } */