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riscv-gcc-1
Commit 283b5296 by Venkataramanan Kumar Committed by Venkataramanan Kumar
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Document AMD bdver2 in invoke.texi 

From-SVN: r184688
parent bedcedc1
Showing with 11 additions and 2 deletions
gcc/ChangeLog
2012-03-01 Venkataramanan Kumar <venkataramanan.kumar@amd.com>
* doc/invoke.texi: Document AMD bdver2 and remove mentioning
3DNow from bdver1.
2012-02-29 Jakub Jelinek <jakub@redhat.com>
Uros Bizjak <ubizjak@gmail.com>
......
gcc/doc/invoke.texi
......@@ -13084,8 +13084,12 @@ instruction set extensions.)
@item bdver1
AMD Family 15h core based CPUs with x86-64 instruction set support. (This
supersets FMA4, AVX, XOP, LWP, AES, PCL_MUL, CX16, MMX, SSE, SSE2, SSE3, SSE4A,
SSSE3, SSE4.1, SSE4.2, 3DNow!, enhanced 3DNow!, ABM and 64-bit
instruction set extensions.)
SSSE3, SSE4.1, SSE4.2, ABM and 64-bit instruction set extensions.)
@item bdver2
AMD Family 15h core based CPUs with x86-64 instruction set support. (This
supersets BMI, TBM, F16C, FMA, AVX, XOP, LWP, AES, PCL_MUL, CX16, MMX, SSE,
SSE2, SSE3, SSE4A, SSSE3, SSE4.1, SSE4.2, ABM and 64-bit instruction set
extensions.)
@item btver1
AMD Family 14h core based CPUs with x86-64 instruction set support. (This
supersets MMX, SSE, SSE2, SSE3, SSSE3, SSE4A, CX16, ABM and 64-bit
......
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