Commit 28350fd1 by Richard Sandiford Committed by Richard Sandiford

[AArch64] Extend SVE reverse permutes to predicates

This is tested by the main SVE ACLE patches, but since it affects
the evpc routines, it seemed worth splitting out.

2019-10-29  Richard Sandiford  <richard.sandiford@arm.com>

gcc/
	* config/aarch64/aarch64-sve.md (@aarch64_sve_rev<PRED_ALL:mode>):
	New pattern.
	* config/aarch64/aarch64.c (aarch64_evpc_rev_global): Handle all
	SVE modes.

From-SVN: r277562
parent 183bfdaf
2019-10-29 Richard Sandiford <richard.sandiford@arm.com>
* config/aarch64/aarch64-sve.md (@aarch64_sve_rev<PRED_ALL:mode>):
New pattern.
* config/aarch64/aarch64.c (aarch64_evpc_rev_global): Handle all
SVE modes.
2019-10-29 Richard Sandiford <richard.sandiford@arm.com>
* config/aarch64/aarch64.md (FFR_REGNUM, FFRT_REGNUM): New constants.
* config/aarch64/aarch64.h (FIRST_PSEUDO_REGISTER): Bump to
FFRT_REGNUM + 1.
......@@ -111,6 +111,7 @@
;; ---- [INT,FP] General permutes
;; ---- [INT,FP] Special-purpose unary permutes
;; ---- [INT,FP] Special-purpose binary permutes
;; ---- [PRED] Special-purpose unary permutes
;; ---- [PRED] Special-purpose binary permutes
;;
;; == Conversions
......@@ -4750,6 +4751,20 @@
)
;; -------------------------------------------------------------------------
;; ---- [PRED] Special-purpose unary permutes
;; -------------------------------------------------------------------------
;; Includes:
;; - REV
;; -------------------------------------------------------------------------
(define_insn "@aarch64_sve_rev<mode>"
[(set (match_operand:PRED_ALL 0 "register_operand" "=Upa")
(unspec:PRED_ALL [(match_operand:PRED_ALL 1 "register_operand" "Upa")]
UNSPEC_REV))]
"TARGET_SVE"
"rev\t%0.<Vetype>, %1.<Vetype>")
;; -------------------------------------------------------------------------
;; ---- [PRED] Special-purpose binary permutes
;; -------------------------------------------------------------------------
;; Includes:
......
......@@ -18156,7 +18156,7 @@ aarch64_evpc_rev_global (struct expand_vec_perm_d *d)
{
poly_uint64 nelt = d->perm.length ();
if (!d->one_vector_p || d->vec_flags != VEC_SVE_DATA)
if (!d->one_vector_p || d->vec_flags == VEC_ADVSIMD)
return false;
if (!d->perm.series_p (0, 1, nelt - 1, -1))
......
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