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riscv-gcc-1
Commit 27a2c2b5 by Richard Kenner
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(emit_move_sequence): Refine previous change. 

From-SVN: r13087
parent 9593ce03
Showing with 8 additions and 2 deletions
gcc/config/pa/pa.c
...@@ -1066,7 +1066,10 @@ emit_move_sequence (operands, mode, scratch_reg) ...@@ -1066,7 +1066,10 @@ emit_move_sequence (operands, mode, scratch_reg)
else if (reload_in_progress && GET_CODE (operand0) == SUBREG else if (reload_in_progress && GET_CODE (operand0) == SUBREG
&& GET_CODE (SUBREG_REG (operand0)) == REG && GET_CODE (SUBREG_REG (operand0)) == REG
&& REGNO (SUBREG_REG (operand0)) >= FIRST_PSEUDO_REGISTER) && REGNO (SUBREG_REG (operand0)) >= FIRST_PSEUDO_REGISTER)
SUBREG_REG (operand0) = reg_equiv_mem[REGNO (SUBREG_REG (operand0))]; {
SUBREG_REG (operand0) = reg_equiv_mem[REGNO (SUBREG_REG (operand0))];
operand0 = alter_subreg (operand0);
}
if (reload_in_progress && GET_CODE (operand1) == REG if (reload_in_progress && GET_CODE (operand1) == REG
&& REGNO (operand1) >= FIRST_PSEUDO_REGISTER) && REGNO (operand1) >= FIRST_PSEUDO_REGISTER)
...@@ -1074,7 +1077,10 @@ emit_move_sequence (operands, mode, scratch_reg) ...@@ -1074,7 +1077,10 @@ emit_move_sequence (operands, mode, scratch_reg)
else if (reload_in_progress && GET_CODE (operand1) == SUBREG else if (reload_in_progress && GET_CODE (operand1) == SUBREG
&& GET_CODE (SUBREG_REG (operand1)) == REG && GET_CODE (SUBREG_REG (operand1)) == REG
&& REGNO (SUBREG_REG (operand1)) >= FIRST_PSEUDO_REGISTER) && REGNO (SUBREG_REG (operand1)) >= FIRST_PSEUDO_REGISTER)
SUBREG_REG (operand1) = reg_equiv_mem[REGNO (SUBREG_REG (operand1))]; {
SUBREG_REG (operand1) = reg_equiv_mem[REGNO (SUBREG_REG (operand1))];
operand1 = alter_subreg (operand1);
}
/* Handle secondary reloads for loads/stores of FP registers from /* Handle secondary reloads for loads/stores of FP registers from
REG+D addresses where D does not fit in 5 bits, including REG+D addresses where D does not fit in 5 bits, including
......
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